JPS5544649A - Input control unit - Google Patents

Input control unit

Info

Publication number
JPS5544649A
JPS5544649A JP11820978A JP11820978A JPS5544649A JP S5544649 A JPS5544649 A JP S5544649A JP 11820978 A JP11820978 A JP 11820978A JP 11820978 A JP11820978 A JP 11820978A JP S5544649 A JPS5544649 A JP S5544649A
Authority
JP
Japan
Prior art keywords
signal
data
sampling
sent
central processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11820978A
Other languages
Japanese (ja)
Inventor
Hiroyuki Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11820978A priority Critical patent/JPS5544649A/en
Publication of JPS5544649A publication Critical patent/JPS5544649A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To realize the sampling in the optimum timing and according to the properties of the data input signal and the process contents by selecting either the data ready signal sent from the data transmitter or the signal from the timer unit.
CONSTITUTION: A selection is given at selection designation circuit 2 and by selection signal 10 given from the central processor between timing signal 11 which is generated at timer unit 1 in the time interval designated by designation signal sent from the central processor and data ready signal 6 sent from the data transmitter. And sampling signal 7 is generated at sampling signal generation circuit 3. Data input signals 5 on plural number of signal lines and sent from the data transmitter are sampled at sampling circuit 4 based on sampling signal 7, and then data 8 is transmitted to the central processor.
COPYRIGHT: (C)1980,JPO&Japio
JP11820978A 1978-09-25 1978-09-25 Input control unit Pending JPS5544649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11820978A JPS5544649A (en) 1978-09-25 1978-09-25 Input control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11820978A JPS5544649A (en) 1978-09-25 1978-09-25 Input control unit

Publications (1)

Publication Number Publication Date
JPS5544649A true JPS5544649A (en) 1980-03-29

Family

ID=14730896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11820978A Pending JPS5544649A (en) 1978-09-25 1978-09-25 Input control unit

Country Status (1)

Country Link
JP (1) JPS5544649A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182750A (en) * 1982-04-21 1983-10-25 Hitachi Ltd Analog-digital converting circuit
JPS63267409A (en) * 1987-02-20 1988-11-04 ザルトリウス・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Integrated filter and filter casing for separating fluid content

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182750A (en) * 1982-04-21 1983-10-25 Hitachi Ltd Analog-digital converting circuit
JPH0410094B2 (en) * 1982-04-21 1992-02-24
JPS63267409A (en) * 1987-02-20 1988-11-04 ザルトリウス・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Integrated filter and filter casing for separating fluid content

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