JPS6221427B2 - - Google Patents
Info
- Publication number
- JPS6221427B2 JPS6221427B2 JP8782379A JP8782379A JPS6221427B2 JP S6221427 B2 JPS6221427 B2 JP S6221427B2 JP 8782379 A JP8782379 A JP 8782379A JP 8782379 A JP8782379 A JP 8782379A JP S6221427 B2 JPS6221427 B2 JP S6221427B2
- Authority
- JP
- Japan
- Prior art keywords
- information
- bits
- shift register
- circuit
- information code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】
この発明は１つの情報が複数個（奇数）のビツ
トで表わされている情報符号を判定するための多
数決判定回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a majority decision circuit for determining an information code in which one piece of information is represented by a plurality of (odd number) bits.
従来、１つの情報Ａに対して３ビツトの符号
“111”を割当て、Ａでないという情報に対して
“000”を割当て、これを受信側において多数決判
定回路により判定し、受信信号が“111”，
“101”，“110”および“011”のいずれかであるな
らば受信信号を情報Ａと判断し、“000”，“001”，
“010”および“100”のいずれかであるならば情
報と判断している。従来このような判定は、第
１図に示すように３ビツトの内の２ビツトづつの
組合せをレジスタ３０，４０および５０により作
り、
NAND回路６０〜９０においてそれらの組合せの
内に１つでも“11”の組合わせ（３ビツトのうち
２ビツト以上が“１”であること）が検出されれ
ば、受信信号を情報Ａと判断し、それ以外の場合
には情報と判断している。なお、この組合せの
数は3C2＝３であることは言を待たない。 Conventionally, a 3-bit code "111" is assigned to one piece of information A, and "000" is assigned to information that is not A. This is determined by a majority decision circuit on the receiving side, and the received signal is "111". ，
If it is any of “101”, “110” and “011”, the received signal is judged to be information A, and “000”, “001”,
If it is either "010" or "100", it is determined to be information. Conventionally, such a determination is made by creating combinations of two out of three bits using registers 30, 40, and 50, as shown in FIG. If a combination of "11" (two or more of the three bits are "1") is detected, the received signal is determined to be information A; otherwise, it is determined to be information. It goes without saying that the number of this combination is 3 C 2 =3.
ところで、情報伝送に高い信頼性が要求される
場合には、１つの情報伝送に、より多くのビツト
数を割り当てることが必要となる。例えば、１情
報に５ビツトを割り当てたとすると、この組合せ
の数は「相異なる５つものから３つをとる組合
せ」となり5C3＝10すなわち10通りとなる。７ビ
ツトの場合には7C4＝35通りとなる。このため第
１図の回路構成により多数決判定回路を実現しよ
うとすると、情報に要求される信頼性が高くなる
につれて判定回路の規模が大きくなり複雑化する
という欠点がある。 By the way, when high reliability is required for information transmission, it is necessary to allocate a larger number of bits to one information transmission. For example, if 5 bits are assigned to one piece of information, the number of combinations is ``a combination of 3 out of 5 different things'', which is 5 C 3 =10, that is, 10 combinations. In the case of 7 bits, there are 7 C 4 =35 ways. Therefore, if an attempt is made to realize a majority decision circuit using the circuit configuration shown in FIG. 1, there is a drawback that as the reliability required for information increases, the scale of the decision circuit becomes larger and more complex.
この発明の目的は上述の欠点を除去した多数決
判定回路を提供することにある。 An object of the present invention is to provide a majority decision circuit that eliminates the above-mentioned drawbacks.
次に本発明を図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第２図は本発明の一実施例を示す回路図で、こ
の実施例では１つの情報Ａに対して５ビツトが割
当てられている。図において、端子１には情報Ａ
を周期的に含むデータが与えられる。この情報Ａ
は、タイミング発生回路２から供給されるタイミ
ングパルス１２０によつてゲート回路１３０にお
いてデータから検出される。この情報符号は３ビ
ツトの容易を持つシフトレジスタ１５０のタイミ
ング信号として供給される。シフトレジスタ１５
０は、信号発生回路３（この例ではグランド）か
らレジスタ入力１４０（“０”）をゲート１３０か
らのタイミング信号に応じて（ここでは“０”）
１ビツトづつシフトする。もし、５ビツトの情報
符号が３ビツト以上“１”を有している場合、レ
ジスタ入力１４０は３ビツトシフトされ、シフト
レジスタ１５０の３段目に“０”を出力する。こ
の出力はラツチ回路１７０に与えられる。また、
情報符号が３ビツト未満の“１”を有する場合に
は、シフトレジスタ１５０の３段目にはレジスタ
入力１４０は現われず、情報はであると判断さ
れる。ここでシフトレジスタ１５０とラツチ回路
１７０は、多数決判定回路終了後にクリアパルス
発生回路４からの情報Ａの周期に同期したクリア
パルス１６０によつて自動的にクリアされ、次の
情報を判定するための待ち状態となる。なお、シ
フトレジスタの容量は、１つの情報に割当てられ
るビツト数をＸ（奇数）とすると、Ｘ＋１／２で表わ
される。 FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which 5 bits are allocated to one piece of information A. In the figure, terminal 1 has information A.
Data containing periodically is given. This information A
is detected from the data in the gate circuit 130 using the timing pulse 120 supplied from the timing generation circuit 2. This information code is provided as a timing signal for a shift register 150 with 3 bits. shift register 15
0 means that the register input 140 (“0”) is input from the signal generation circuit 3 (ground in this example) according to the timing signal from the gate 130 (“0” in this example).
Shift one bit at a time. If the 5-bit information code has 3 or more bits of "1", the register input 140 is shifted by 3 bits and outputs "0" to the third stage of the shift register 150. This output is provided to latch circuit 170. Also,
If the information code has less than 3 bits of "1", the register input 140 does not appear in the third stage of the shift register 150, and the information is determined to be . Here, the shift register 150 and the latch circuit 170 are automatically cleared by a clear pulse 160 synchronized with the cycle of information A from the clear pulse generating circuit 4 after the majority decision circuit is completed, and are used to determine the next information. It will be in a waiting state. Note that the capacity of the shift register is expressed as X+1/2, where X (odd number) is the number of bits allocated to one piece of information.
以上、１つの情報に対し５ビツトを割り当てた
ときの構成を説明したが、割り当てるビツト数が
７ビツト，９ビツト，11ビツト……と増えてもシ
フトレジスタの段数を増加することにより多数決
判定回路が容易に実現できる。また、情報Ａを
“１”の集合で表わしているが、“０”と“１”の
組合わせでもよく、この場合には多数決判定回路
の前段でこのような情報を“１”の集合に変換す
ればよい。 The configuration above has been explained when 5 bits are allocated to one piece of information, but even if the number of bits allocated increases to 7 bits, 9 bits, 11 bits... can be easily realized. Also, although information A is expressed as a set of "1", it may also be a combination of "0" and "1", and in this case, such information is expressed as a set of "1" at the stage before the majority decision circuit. Just convert it.
以上のように、本発明では、シフトレジスタを
用いて多数決判定回路を実現しているため回路規
模が小さく消費電流が少なくてすみ、低価格とな
る。 As described above, in the present invention, since the majority decision circuit is implemented using shift registers, the circuit scale is small and current consumption is small, resulting in low cost.
第１図は従来の多数決判定回路を示す回路図お
よび第２図は本発明の一実施例を示す回路図であ
る。
第２図において、１１０……入力情報、１２０
……サンプリングパルス、１３０……ゲート回
路、１４０……レジスタ入力、１５０……３ビツ
トシフトレジスタ、１６０……クリアパルス、１
７０……ラツチ回路。
FIG. 1 is a circuit diagram showing a conventional majority decision circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In FIG. 2, 110...input information, 120
...Sampling pulse, 130...Gate circuit, 140...Register input, 150...3-bit shift register, 160...Clear pulse, 1
70...Latch circuit.
Claims (1)
れる情報符号列を受ける入力端子と、前記情報符
号と同一ビツトレートのタイミングパルスを発生
するタイミングパルス発生手段と、Ｘ＋１／２ビツト の容量を有し前記それぞれの情報符号の各ビツト
値に応答して前記入力発生手段から与えられる信
号をシフトするシフトレジスタと、このシフトレ
ジスタの出力をラツチするラツチ回路と、前記シ
フトレジスタおよび前記ラツチ回路をクリアする
ためのクリア信号を発生する手段とから構成され
たことを特徴とする多数決判定回路。[Scope of Claims] 1. An input terminal for receiving an information code string in which one information code is represented by X (odd number) bits, a timing pulse generating means for generating a timing pulse having the same bit rate as the information code, and X+1/ a shift register having a capacity of 2 bits and shifting a signal applied from the input generating means in response to each bit value of each of the information codes; a latch circuit that latches the output of the shift register; and the shift register. and means for generating a clear signal for clearing the latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8782379A JPS5612153A (en) | 1979-07-11 | 1979-07-11 | Majority-deciding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8782379A JPS5612153A (en) | 1979-07-11 | 1979-07-11 | Majority-deciding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5612153A JPS5612153A (en) | 1981-02-06 |
| JPS6221427B2 true JPS6221427B2 (en) | 1987-05-12 |
Family
ID=13925667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8782379A Granted JPS5612153A (en) | 1979-07-11 | 1979-07-11 | Majority-deciding circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5612153A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0240952U (en) * | 1988-09-12 | 1990-03-20 |
-
1979
- 1979-07-11 JP JP8782379A patent/JPS5612153A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0240952U (en) * | 1988-09-12 | 1990-03-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5612153A (en) | 1981-02-06 |
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