SU1181154A1 - Ternary coder - Google Patents

Abstract

The THERMAL KO.riA encoder contains two ternary logic elements, with the first and second encoder information inputs connected to the first and second inputs of the first ternary logic element, the third and quarters of the encoder information inputs connected to the first and second inputs of the second layer, respectively ternary logic element, the fifth and sixth information inputs of the encoder are connected respectively to the first inputs of the subtraction of the first and second ternary logic elements, the third and p. element, the seventh and eighth InSL formation encoder inputs are connected respectively to the third inputs of the addition and subtraction of the first ternary logic element, the outputs of the first and W The third ternary logic elements are the outputs of the first and second digits of the encoder, respectively. 00

Description

11 The invention relates to computing and can be used in the construction of discrete information processing systems. The purpose of the invention is to simplify the encoder. FIG. 1 shows a block terminator block diagram (1.0, 1) in FIG. 2 - phase-pulse diagrams of its operation with the conventions. The encoder contains ternary logic elements 1 and 2, information inputs 3-10 and outputs 11 and 12. The device works as follows. The encoder contains two ternary logic elements, each of which performs ternary operations, described in Table. 1. These operations form a functionally complete system of logical functions. The ternary log-elements can be implemented, for example, on magnetic logic cells. Table 1 42 Indicated also (fit. 2) phase pulse diagrams 13 and 14, the first and second phases of the clock supply, respectively diagrams 15-22 signals at the corresponding inputs 3-10, diagrams 23-24 signals at the outputs of the elements 1 and 2 respectively. The clock supply system of the encoder is two-phase, and the signal of positive polarity to one of the information inputs 3-10 of elements 1 and 2 is received through two phases (one clock) of transmitting information on the elements of the encoder (Fig. 2). The signals arrive at one of the information inputs during the clock pulse of the first phase. The second-phase clock pulse reads information from elements 1 and 2. One of the information inputs 3-10 is given a positive polarity signal, and at the outputs 11 and 12 (at the outputs of elements 1 and 2) the code combinations appear. form (on output 11 with a natural weight of 3, on output 12-3), which unambiguously correspond to

one

- 1 I ,, j

one

ABOUT

The clock pulse of the first phase of the first cycle, according to the logic of the element recorded in the table. 1, the positive polarity signal from input 3 is transmitted to the first input of element 1 and the third input

3118

adding element 2, a clock of the second phase, the positive polarity signals from outputs 11 and 12 (from the outputs of elements 1 and 2) exit the encoder, forming the output 5 combination (11) corresponding to the signal at input 3.

1st 2nd 3rd if-J 5th 6th and 7-0 at

time, time tat time, time tat

FIG. 2

1544

Similarly (Figs. 1, 2 and Table 2), the signal is converted at subsequent information inputs D-10, while the outputs of the positive polarity signal correspond to code 1, and the negative polarity signal corresponds to code 1.

Claims (1)

Ternary CO Encoder, YES, containing two ternary logic elements, the first and second information inputs of the encoder are connected respectively to the first and second inputs of addition of the first ternary logic element, the third and fourth information inputs of the encoder are connected respectively to the first and second inputs of addition of the second ternary logic of the element, the fifth and sixth information inputs of the encoder are connected respectively to the first inputs of reading the first and second ternary logic elements, the third and fifth the information inputs of the encoder are connected respectively to the second inputs of the subtraction of the first and second ternary logic elements, characterized in that, in order to simplify the encoder, the first and second information inputs of the encoder are connected respectively to the third inputs of addition and subtraction of the second ternary logic element, the seventh and the eighth information inputs of the encoder are connected respectively to the third inputs of addition and subtraction of the first ternary logic element, the outputs of the first and second are ternary logic elements are respectively first and second output bits of the encoder. > Fig 1 1111