SU1092488A1 - Translator from ternary-coded decimal code to code of seven-segment indicator - Google Patents

Abstract

The TREASURY-DECIMAL CODE CONVERTER TO THE SEMISS-TERM INDICATOR CODE, containing eleven ternary elements, the input of the first discharge of the converter connected to the addition input of the first and first input of the second ternary reading, the input of the second discharge of the converter connected to the input of the first reading and the first input of the reading of the threefold elements the input of the addition of the fourth ternary elements, the input of the third bit of the converter is connected to the first input of the subtraction of the second ternary element, the output of the third ternary element is connected to the input of the subtraction of the fifth ternary element, the input of the first phase of the clock supply is connected to the first push-fit inputs of the sixth, seventh, eighth, ninth and input of the tenth threefold elements, outputs of the fifth, sixth, seventh, eighth, ninth, tenth This and the eleventh ternary elements are transducer outputs, characterized in that, in order to simplify and speed up the transducer, the first discharge input of the transducer is connected to the second subtraction input of the third and first and second The fourth-termination input subtraction inputs, the second discharge input of the converter is connected to the second addition and subtraction inputs of the second and the first addition input of the fifth ternary elements, the third discharge input of the converter is connected to the second addition input of the fifth ternary element, the output of the first threefold element is connected i with the second input of the addition of the sixth, the first inputs of the subtraction of the seventh and (L of the eighth, first and second inputs of the subtraction of the tenth ternary elements, the output of the second ternary element is connected to The first subtraction input of the sixth and the subtraction input of the eleventh ternary elements, the output of the third ternary element is connected to the second addition inputs of the eighth and ninth and the first input of the ND eleventh ternary elements, the output of the fourth ternary element so00 00 is the same as the input of the subtraction of the ninth, second inputs subtracting the sixth, seventh and eighth and the second input of the addition of the eleventh ternary elements, the inputs of the first and second phases of the clock supply are connected to the second input of the seventh and the next input third voltage ternary elements, respectively.

Description

11 The invention relates to automation and computing, can be used in designing output transducers for indication, and is intended to convert a ternary code of a number into a code to highlight a decimal digit on an indicator element having seven segments. A known binary code converter into a seven-segment indicator code, containing thirteen logical elements tl3. The disadvantages of this converter are the impossibility of converting ternary codes and low reliability due to the use of a large number of logical elements. The closest to the proposed technical essence and circuit construction is a converter of a three-decimal code into a seven-segment indicator code containing thirteen three-fold elements, and the input of the first discharge of the converter is connected to the first inputs of the first and second ternary elements of the input of the second discharge of the converter with the first inputs of the subtraction of the first and third and the first input of the addition of the fourth ternary elements, the input of the third bit of the converter is connected to the first input subtracting the second ternary element; the output of the third ternary element is connected to the first input; subtracting the eleventh ternary element; the input of the first phase of the clock supply is connected to the first inputs of the addition of the fifth, sixth, seventh, eighth and tenth threefold elements, outputs of the fifth, sixth, seventh the eighth, ninth, tenth and eleventh threefold elements are outputs of converter 2. A disadvantage of the known converter is its low speed, since the conversion of input signals to It is produced over the three phases of the clock supply, and the relative complexity is due to the use of a large amount of hardware and, as a result, the reliability is low. The purpose of the invention is to simplify and increase the speed of the transducer. The goal is achieved by the fact that in the converter there is a triple 82 decimal code in the code of a seven-segment indicator containing eleven ternary elements, and the input of the first discharge of the converter is connected to the input of the first and the first input of the second ternary elements, the input of the second bit of the converter is connected the first subtraction input and the first subtraction input of the third and the addition input of the fourth ternary elements, the third bit input of the converter is connected to the first subtraction input of the second ternary element, the output of the third ternary element is connected to the subtraction input of the fifth ternary element, the input of the first phase of the clock supply is connected to the first inputs of the sixth, seventh, eighth, ninth and input of the tenth threefold elements, outputs of the fifth, sixth, seventh, eighth The ninth, tenth and eleventh ternary elements are the transducer outputs, the input of the first discharge transducer is connected to the second subtraction input of the third and first and second subtraction inputs of the fourth three-element element the input of the second bit of the converter is connected to the second inputs of the addition and subtraction of the second and first input of the addition of the fifth ternary elements; the input of the third bit of the converter is connected to the second input of the addition of the fifth ternary element 5; the output of the first threefold element is connected to the second input of the sixth, first inputs subtracting the seventh and eighth, the first and second inputs of the subtraction of the tenth ternary elements, the output of the second ternary element is connected to the first input of the subtraction of the sixth and the subtraction input of one of the third ternary element, the output of the third ternary element is connected to the second inputs of the eighth and ninth addition and the first input of the eleventh ternary elements, the output of the fourth ternary element is connected to the subtraction input of the ninth, second subtraction inputs of the sixth, seventh and eighth and second addition inputs of the eleventh threefold elements, the inputs of the first and second phases of the clock supply are connected to the second input of the seventh and seventh ternary elements, respectively. 3.1 Figure 1 shows the scheme of the proposed Converter; 2, the numbering of the segments (c) of the indicator element; FIG. 3 is a timing diagram of the operation of the converter. The circuit contains ternary elements 1-11, inputs 12, 13, and 14 of the first, second, and third bits of the converter, having weights 3 and 3, respectively, inputs 15 and 16 of the first and second phases of the clock supply, respectively, outputs 17-23 of the converter. Diagrams (FIG. 3) 24 25 and 26 denote, respectively, the pulses of the first, second and third phases of the clock supply of the converter, diagrams 27, 28 and 29 respectively represent signals at the inputs (12, 13 and 14) of the first second and third bits of the converter, diagrams 30-40 - respectively, the signals at the outputs of the elements 1-11. The converter is made on elements, each of which performs ternary operations in accordance with Table 1. Table

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These operations form a functionally complete system of logical functions and can be implemented on the basis of ternary elements (for example, on ferrite logic elements).

The inputs 12, 13, and 14 of the first, second, and third bits of the converter, respectively, are input combinations in ternary form (at input 12 with a weight of 3 °, at input 13-3, at the input M-Z), and at outputs 17-23 A transducer (positive signals at the outputs of elements 5-11) appears code combinations that uniquely correspond to the input combination of signals. When the ternary code is applied to the inputs 12, 13 and 14 of the converter 1, it is represented by a signal of positive polarity, 1 is a signal of negative polarity, and O is the absence of a signal. At outputs 17-23 of the converter, positive signals appear in accordance with Table 2.

table 2

If outputs 17-23 (positive signals) of the converter are connected through amplifiers to segments 1c-7c of the indicator element (for example, phosphor) one-to-one, then on the indicator element one can visually observe the decimal digit corresponding to the ternary at the converter input.

The clock supply system of the converter is three-phase, and the input code combination of signals to the inputs 12-14 of the converter of elements 1-4 and 11 enters through three phases (one clock cycle) of information transmission over the elements of the device. The first phase clock pulse reads information from elements 1–4, the second phase reads from elements 5–11, and signals arrive at converter inputs 12–14 during the third phase clock pulse.

The inputs 16 and 15 of the second phase of the clock supply and the first phase of the clock supply are respectively connected to the first 1M input of the addition of element 3 and the first inputs of the addition of elements

5, 6, 7 and the input of the addition 10, the first second inputs of the addition of the element 7, respectively (in the graphic image of the element - T). This means that signals are fed to these inputs during the clock pulse of the second and first phases of each clock, i.e. in the absence of information at the inputs 12-14 of the converter, these elements are the generators of positive polarity signals. In this case, the pulse of the second phase of the second cycle positive signals from elements 6-11 (element 5 is read zero signal) output from the converter, forming the output combination (0111111), corresponding to the input combination (000) and the digit Zero

The operation of the converter in accordance with the input combination (001) is as follows.

The third-phase clock pulse of the second clock according to the logic of the element recorded in Table 1, a positive signal from the input 12 of the converter is transmitted to the first input

addition of element 1 and the second inputs of the subtraction of elements 3 and 4 and recording +1 and -1 in them, respectively, a positive signal from element 1 is transmitted to the second input of the element 6 and the first input of the subtraction of element 8 by a pulse of the third phase, the second input of the subtracting element 10 and writes +1 and -1, respectively, and the negative signal from element 4 is transmitted to the first subtraction input of element 9 and the second subtraction inputs of elements 7 and 8 and writes -1 to them. The clock pulse of the second phase of the third clock cycle positive signals from elements 6 and 7 out of the converter, forming the output combination

(0000110) corresponding to the input combination (001) and the number One.

Similarly (in accordance with Figures 1 and 3 and Table 2), transformations of the following input combinations occur.

The proposed converter of the ternary-decimal code into the code of a seven-segment indicator provides, in comparison with a well-known technical solution, an increase in speed and simplification of the converter and, as a result, an increase in its reliability. All this allows us to simplify the converter into three ternary elements and increase its speed by 1.5 times and, as a result, increase the reliability of the entire instrument.

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Claims (1)

A Ternary Decimal Code Converter for a Seven-Segment Indicator Code containing eleven ternary elements, the input of the first bit of the converter connected to the input of addition of the first and first input of the addition of the second ternary elements, the input of the second bit of the converter connected to the subtraction input of the first and first subtraction of the third and the input of addition the fourth ternary elements, the input of the third category of the Converter is connected to the first input of the subtraction of the second ternary element, the output of the third ternary the element is connected to the subtraction input of the fifth ternary element, the input of the first phase of the clock power supply is connected to the first inputs of the addition of the sixth, seventh, eighth, ninth and the input of the tenth ternary elements, the outputs of the fifth, sixth, seventh, eighth, ninth, tenth and eleventh ternary cops are the outputs of the converter, characterized in that, in order to simplify and improve the speed of the converter, the input of the first discharge of the converter is connected to the second subtraction input of the third and the first and second inputs of the subtractor of the fourth ternary element input, the input of the second digit of the converter is connected to the second inputs of addition and subtraction of the second and first input of the fifth ternary elements input, the input of the third digit of the converter is connected to the second input of the fifth ternary element, the output of the first ternary element is connected to the second input of the sixth addition, g the first inputs of the subtraction of the seventh and eighth, the first and second inputs of the subtraction of the tenth ternary elements, the output of the second ternary element is connected to the first input of the subtraction of the sixth and the subtraction input of the eleventh ternary elements, the output of the third ternary element is connected to the second inputs of the addition of the eighth and ninth and the first input of the addition of the eleventh ternary elements, the output of the fourth ternary element is connected to the subtraction of the ninth, the second subtraction inputs of the sixth, seventh and eighth and second input of addition of the eleventh ternary elements, the inputs of the first and second phases of clock power are connected to the second input of the addition of the seventh and the input of the addition of the third ternary elements, respectively etstvenno. > ί log;