JPS63202132A - Digital pulse demodulation circuit - Google Patents

Abstract

PURPOSE:To demodulate an input data in parallel simultaneously by converting an input data comprising a serial data inputted sequentially into a parallel data having an input data for reference before and after the data. CONSTITUTION:An input M<2>FM data DMM is converted into 4-bit M<2>FM data M<0>, M<1>, M<2> and M<3> by a serial/parallel conversion circuit 2. Then, the data is subject to parallel processing by 2-bit each according to the NRZ system format, the NRZ data NRZ0, NRZ1...NRZ6, NRZ7 by 8-bit are latched in the four period of the 1st clock CK2 and demodulated into a serial NRZ data DN by a parallel/serial conversion circuit 10. Since the parallel processing circuit part is constituted by using logic circuits having a slow processing speed, the power consumption is reduced remarkably.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Overview of the invention C: Prior art (Figs. 6 and 7) D: Problem to be solved by the invention E: Means for solving the problem (Fig. 1) F: Effect (Fig. 1) 1
Figure) G Embodiment (Gl) Principle of demodulation (G2) C Pattern detection method (G3) Window detection method (G4) Structure of the embodiment (Figures 1 to 5) H Effects of the invention A Industrial Field of Application The present invention relates to a digital pulse demodulation circuit, and can be applied to, for example, a digital video tape recorder (digital VTR).

B. Summary of the Invention The present invention provides a digital pulse demodulation circuit that converts input data consisting of sequentially input serial data into parallel data having input data for reference before and after, thereby simultaneously inputting data in parallel. Thus, input data with a high repetition frequency can be demodulated with a simple configuration that consumes less power overall.

C. Prior Art Conventionally, in a digital VTR, when recording a digitally encoded video signal, a digital pulse modulation circuit is used to convert the signal into a recording signal in a desired signal form and record the signal.

That is, as shown in FIG. 6, the video signal is sampled and sequentially encoded into, for example, 8-bit digital information, and then converted to a predetermined clock signal GK (FIG. 6 (A)) via a parallel-to-serial conversion circuit. Serial data DS (FIG. 6(B)) synchronized with the rising timing of is obtained.

NRZ(n) whose logic level is inverted in synchronization with the rising timing of the clock signal CK so as to correspond to the logic level of the serial data DS.

By obtaining the modulation data of the modulation method of n return to zero), the NRZ data DN (Fig.
C)) is obtained.

Furthermore, M F M (modified frequency)
When the NRZ data DN is logic "0", the logic level is set to "0" at the rising edge of the clock cycle only when the logic level of the NRZ data DN one clock cycle before is logic "O". (hereinafter referred to as the first condition), NRZ
When the logic level of data DN is logic "1", the logic level is inverted at the falling timing of clock signal CK (that is, at the middle point of one clock cycle of clock signal CK) (hereinafter, this will be referred to as the second condition). call) MFM data D
M (Fig. 6(D)) is obtained.

By recording the MFM data DM on a magnetic tape, even if the serial data DS contains consecutive pieces of information at the same logic level, a recording signal with less low frequency components can be obtained, and the clock signal CK can also be recorded at the same time. It can be easily demodulated without having to do so.

However, as shown in FIG.
Since the image shown in FIG. 7(A) contains a DC component, there is a problem in that the DC level SD (FIG. 7(B)) changes greatly due to the continuous addition of the DC component depending on the video signal.

In order to solve this problem, in digital VTRs, as proposed in, for example, Japanese Patent Application Laid-open No. 114206/1983, M less FM (modified
mirror frequency modulati
On) type digital pulse modulation circuit is used to prevent the DC level from fluctuating beyond a predetermined value.

In other words, in addition to the first and second conditions of the modulation method of the MFM data DM, the logic level of the NRZ data DN is
The data is separated from the first data of "0" to the second data of logic "0" that appears next, and the data of logic "1" in between is counted, and when the count value is an even number (hereinafter this is called C pattern). ), this continuous last logic ``1
” and prohibits the inversion of the logic level of the MFM data DM in
Setting the third condition of re-dividing the M data DM,
By reversing the inversion direction of the logic level for the entire MFM data DM, the DC level SDI (Fig. 7 (
C)) M2FM data with little change (Figure 6 (E))
and (FIG. 7(D)).

Problems to be Solved by Invention DHowever, in a digital pulse demodulation circuit used when reproducing a magnetic tape recorded in the M"FM method, the exclusive OR of 2-bit M"FM data DMM is is used to demodulate to NRZ data DN and C
It is necessary to detect the presence or absence of a pattern, and for this reason, in conventional digital pulse demodulation circuits of this type, read M'' FM data DMM are sequentially processed in series.

Therefore, in the digital pulse demodulation circuit for such an M'' FM data DMM, processing must be performed using a clock signal having twice the frequency of the clock signal GK for the NRZ data DN.

Actually, in digital VTR, NRZ data DN
Because the clock frequency of the NTSC video signal is high, approximately 120 (MH
For PAL video signals, approximately 160
(MH), and further considering the video signal in the special playback mode, there was a problem in that the M''FM data DMM had to be processed with a clock signal of about 200 (MHz).

When the lock frequency becomes like this, TTL (transistor
transistor logic), CM OS
(complementary metal oxl
It has become difficult to stably demodulate digital signals using integrated circuits, and for this reason, in digital VTRs, for example, E CL (emter c), which can perform high-speed switching operations, has become difficult to demodulate digital signals stably using integrated circuits.

A digital pulse demodulation circuit was constructed using a digital integrated circuit (upled logic).

However, when configured in this way, the power consumption of the digital pulse demodulation circuit becomes large and it becomes difficult to achieve high integration, and it is unavoidable that the digital VTR as a whole becomes large in size, consumes a lot of power, and becomes expensive. There wasn't.

The present invention has been made in consideration of the above points, and provides a digital pulse demodulation circuit that can easily demodulate data with a high repetition frequency without using high-power consumption circuit elements that can perform high-speed switching operations. This is what I am trying to propose.

E Means for Solving Problems In order to solve these problems, the present invention provides a first parallel system that receives input data DMM consisting of serial data and shifts the input data DMM by a predetermined bit at a predetermined clock cycle. The first data that is converted into data MO to M3 and outputs second parallel data QMO to QM8 that has data that overlaps by a predetermined bit with the first parallel data MO to M3 that are output in the previous and subsequent clock cycles. Conversion circuit 2.3 and second parallel data Q
Third parallel data Go-G based on MONQM8
7, and refers to the third parallel data GO-07 to output fourth parallel data QX, QY consisting of predetermined bits in the third parallel data GO-G7. 6.7 and the fourth parallel data QX
, QY by predetermined bits to obtain fifth parallel data NRZO-NRZ7, and a second data conversion circuit 8.9.10 that converts the fifth parallel data NRZO-NRZ7 into serial data DN. Please provide one.

The F-action input data DMM is converted into second parallel data QMO-QM8 having data that overlaps with the first parallel data MO-M3 before and after by a predetermined bit, and based on this second parallel data QMO-QM8. The third parallel data GO to G7 are obtained by referring to the third parallel data GO to G7, and the fourth parallel data QX and QY made up of predetermined bits in the third parallel data GO to G7 are obtained. input data DMM to predetermined serial data DN
Therefore, even input data with a high repetition frequency can be easily demodulated.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(Gl) Principle of demodulation M”FM data DMM converted from NRZ data DN
is modulated according to the first, second, and third conditions, and considering the first and second conditions, M'' FM data D
When demodulating from MM to NRZ data DN, M”F
It is sufficient to divide the M data DMM into two bits at a time (hereinafter referred to as windows) and obtain the exclusive OR of the divided two bits.

However, when considering the third condition in addition to the first and second conditions, the logic "l", "1", r
When a pattern following OJ is included (that is, when it is a C pattern), the NRZ data DN of the central logic "1"
Since inversion is prohibited when modulating M'', even when demodulating from FM data DMM to NRZ data DN, N
It is necessary to correctly detect whether the C pattern of RZ data DN is modulated M''FM data DMM or not.

Here, assuming that the window of the M" FM data DMM is correct, the bit string of the 6 bits (hereinafter referred to as the C pattern end) of the M" FM data DMM in which the last 3 bits of the C pattern of the NRZ data DN are modulated is as follows. ,logic"
0'', ``1'', ``1'', ``1'', ``1'', ``1'', or ``1'', ``0'', ``0'', ``0'', ``0'', ``
0”, so the middle 2 bits are N
When demodulating to RZ data DN, logic “1” is unconditionally set.
”, the C pattern M”FM data DMM is converted to NRZ
It is possible to correctly demodulate the data DN.

Also, as a way to set the window correctly, use NRZ
The bit string of data DN is logical “1”, “0”, “1”
We pay attention to cases where . In other words, NRZ data DN is C
When the 3-bit bit string of the NRZ data DN is logical "1", "0", rlJ, except when it is a pattern, when this NRZ data DN is modulated into the M" FM data DMM, the M" FM data DMM is modulated. The 6-bit bit string is logical "1", "0", "0", "0", "0", "
l” or “0”, “1”, “1”, “1”,
There are two ways to set the window: "1" and "0", and since there is only one way to set the window, if this 6-bit bit string of the FM data DMM is detected, the window set will be updated. Can be done.

Note that the window can be updated using, for example, M”FM data DMM.
QMOlQMI, QM2, QM
3, QM4 and QM5, the adjacent 2 bits, namely QMO and QMl, QMI and QM2, Q
M2 and QM3, QM3 and QM4, QM4 and QM5
5-bit output data GO1G1 consisting of the exclusive OR of
, G2, G3 and G4, which is a logic "1", ro
j, "0", "0", "1", NRZ data DN
The output data Go, G2, and G4 are obtained as follows.

As mentioned above, 6 bits of the M"FM data DMM are required to detect the window and the end of the C pattern. For example, 2 bits QM2 of the M"FM data DMM
In order to demodulate QM3 and QM3 into 1 bit of NRZ data DN, 6 bits QMO, QM of M”FM data DMM are
I, QM2, QM3, QM4 and QM5 are required.

Therefore, in order to correctly demodulate the 4 bits of the M"FM data DMM into the 2 bits of the NRZ data DN, 9 bits of data QMO to QM8 are required as the M"FM data DMM, taking into account the difference in windows. .

That is, for example, the 4-bit QM of M''FM data DMM
2. When demodulating QM3, QM4 and QM5 to obtain 2 bits of NRZ data DN, M”FM data DMM
NR with the combination of QM2 and QM3, QM4 and QM5
When demodulating Z data DN to QA and QB, and M”F
M data DMM QM3 and QM4, QM5 and QM6
The combination of demodulation into QC and QD of NRZ data DN is used depending on the window.

Here, when obtaining NRZ data QA, use M" FM data QMO to QM5, when obtaining NRZ data QB, use M" FM data QM2 to QM7, and when obtaining NRZ data QC, use M" FM data QMI to QM.
6, and when obtaining the NRZ data QD, M"FM data QM3 to QM8 are used. Thus, each M"F
Correct NRZ can be achieved by detecting the C pattern and window using 6 bits of M data DMM.
Data DN can be obtained.

(G2) How to detect C pattern As mentioned above, M”FM data DMM at the end of C pattern
is logical "0", "1", "1", "1", "1", "
1” or logical rlJ, “0”, “0”, rO
J, is a combination of "0" and "0", and when exclusive OR is obtained for each adjacent bit, it becomes logical "1", "
This is one combination of "0", "0", "0", and "0".

Therefore, adjacent bits of 9 bits QMO to QM8 of M''FM data, that is, QMO, QMI, and QMI
and QM2, QM2 and QM3, QM3 and QM4, Q
M4 and QM5, QM5 and QM6, QM6 and QM7
, QM7 and QM8 as output data CO2G1, G2, G3, G4, G5, G6, G
7, when obtaining NRZ data QA, when the bit strings of output data GO, Gl, G2, G3 and G4 are logical "1", "0", "0", rOJ, rOJ,
When setting the logic level of NRZ data QA to logic "1" as the C pattern end, and obtaining NRZ data QB, the bit strings of output data G2, G3, G4, G5, and G6 are set to logic "1", "0", "0", "0", "0"
”, the NRZ data Q is used as the C pattern end.
The logic level of B is set to logic "1", and when obtaining NRZ data QC or QD, the bit string of output data 01 to G5 or 63 to G7 is set to logic "1".
”, “0”, “0”, “0”, “0”, the NRZ data QC or QD is set to logic “1” as the C pattern end.
”.

(G3) Window detection method Also, as mentioned above, the detection of whether the window is correct or not is N
Logic "1", "0", "
1”, that is, this M” FM
Confirm when the 5-bit output data obtained by exclusive ORing of each adjacent bit of the 6-bit bit string of the data DMM is logical "1", "0", rOJ, "0", "1". It is made to be obtained.

Therefore, 9 bits QMO to QM8 of M”FM data DMM
If the exclusive OR output of each adjacent bit is output data GO-G7, the output data GO-G4 or G
2-G6 5-bit data is logic “1” or “
0”, “0”, “0”, and “1”, N
RZ data QA and QB are a combination of correct NRZ data DN, and any of the 5 bits of output data 01 to G5 or G3 to G7 is logic "1", "0", "0", "0"
, "1", the NRZ data QC and Q
D is set to be a correct combination of NRZ data DN.

(G4) Configuration of the Embodiment In FIG. 1, 1 indicates the digital pulse demodulation circuit as a whole, and the input M''FM data DMM is serial data obtained at the rising and falling timings of the basic clock CK of the NRZ data DN. In the serial-parallel conversion circuit 2, the basic clock C of the NRZ data DN is
4-bit M”FM data MO obtained at the rising timing of the first clock CK2, which is obtained by dividing K by 1/2.
.

Convert to Ml, M2 and M3.

The M'' FM data MO, Ml, M2, and M3 are converted into 2 pieces according to the NRZ format by an input data latch circuit 3, a data demodulation circuit 4, a C pattern detection circuit 5, a window detection circuit 6, a data selection circuit 7, and a shift circuit 8. After parallel processing bit by bit, the output data latch circuit 9 outputs 8 bits (7) of NRZ data in 4 cycles of the first clock CK2.
1...-N RZ6 and NRZ7 are latched, and in the parallel-serial conversion circuit 10, the basic tally clock C
Serial data N obtained at the rising edge of K
It is designed to demodulate into RZ data DN.

The input data latch circuit 2 has a first
When the clock CK2 rises, the input parallel data M''FM data MO1M1, M2, M3 are latched into the 4-bit first latch circuit 31, and when the subsequent clock CK2 rises, the output of the first latch circuit 31 is latched into the 4-bit first latch circuit 31. Latched in the second latch circuit 32, and the subsequent clock CK
2, the fourth latch circuit 32 of the second latch circuit 32
The output Q3 is latched into a 1-bit third latch circuit 33.

As a result, the input data latch circuit 3 becomes the latch circuit 31.
04-bit latch output QO1Q1, G2, G3 together with the 5-bit M''FM data previously latched by the second and third latch circuits 32 and 33.
Bit parallel data QMO1QMI, 0M2, QM
3. Send it to the data demodulation circuit 4 as QM4, QM5, QM6, QM7 and QM8.

The data demodulation circuit 4 receives 9-bit parallel data QMO1QMI, . . . input from the input data latch circuit 3.
..., QM7, QM8, respectively, are subjected to exclusive OR circuits 40, 41, . . .
42.43.44.45.46.47 and consists of 8 bits demodulated data GO5G1, G2, G3, G4,
G5, G6 and G7 are obtained.

The C pattern detection circuit 5 receives 8-bit demodulated data GO to G input from the data demodulation circuit 4 as shown in FIG.
7, 5-bit parallel data consisting of demodulated data GO-04 is used to generate M'' FM data QM2 and QM3.
Determine whether the demodulated data G2 is the center bit of the C pattern end or not, and if it is the center bit, set the logic level of the NRZ data QA to logic "1", and if not, set the demodulated data G2 to logic "1". , NRZ data QA.

That is, among demodulated data GO to G4, demodulated data Gi
G2 and G3 are inverters 51A, 52A, and 5, respectively.
3A to the first NAND circuit 5 along with the demodulated data CO.
4A, its output is inputted together with demodulated data G4 to OR circuit 55A, and its output is given to NAND circuit 56A together with the output of inverter 52A.

Thus, only when the demodulated data Go, Gl, G2, G3, G4 are logic "1", "0", rOJ, "0", "0" (that is, at the end of C pattern), will the logic "0", and Otherwise, the logic is "1", so the output QA of the second NAND circuit 56A is the demodulated data GO
When ~G4 is the C pattern end, it is always logic "1" regardless of the logic level of demodulated data G2, and at other times it is the same value as the logic level of demodulated data G2. As a result, the demodulated output G is output to the output terminal of the NAND circuit 56A.
2, the end of the C pattern is detected, and when the end of the C pattern is detected, the NRZ data QA of the logic "1" level is always obtained.

Demodulated data G4, G3, and G5 are also constructed using the same circuit configuration as described above using demodulated data 02 to G6.01 to G5.03 to G7 (the reference numeral attached to the corresponding part to the circuit configuration for demodulated data G2). Among them, the last code rAJ
are replaced with rBJ, "C", and rDJ, respectively)
, the C pattern end is detected, and when the C pattern end is detected, the NRZ data QB of logic "1" level is detected.
.

It is designed to obtain QC and QD.

As shown in FIG. 4, the window detection circuit 6 detects whether any of the demodulated data Go-04 and Go-02 to G6 is logical "1", "0", "0", "0", or "1". Only when
The first window detection output WAB of logic "1" level is sent out, and any one of the demodulated data G1-G5 and G3-G7 is logic "1", "0", "0", rOJ,
When it is "1", the second window detection output WCD of logic "1" level is sent out. Note that the first
And the second window detection outputs WAB and WCD are designed so that they do not become logic "1" at the same time due to the input conditions.

That is, demodulated data G1, G2, and G3 are input to the first NAND circuit 65A together with demodulated data GO via inverters 61A, 62A, and 63A, and the output thereof is inputted to the first NAND circuit 65A together with demodulated data G4 inputted via inverter 64A. is applied to a NAND circuit 67AB through an OR circuit 66A.

Thus, the output of the OR circuit 66A is demodulated data GO1G1.
, G2, G3, and G4 are logical "1", "0", "0", "
It becomes the logic "O" level only when it becomes "0" or "1".

Also, the demodulated data 02 to G6 have a similar circuit configuration (corresponding parts are shown with the last sign replaced with rBJ), and the output of the second OR circuit 66B is the demodulated data G2, G3,
G4, G5, G6 are logical "1", "0", "0", "0"
”, is set to the logic rOJ level only when it is “1”, and this is given to the NAND circuit 67AB. Thus, the first window detection output WAB of the NAND circuit 67AB is output from the first or second OR circuit 66A or 66
A logic "1" is sent out only when one of the outputs of the output terminal B is a logic "0".

In addition, the second window detection output WCD is generated by demodulating data Gl, G2, G3, G4,
Either G5 or G3, G4, G5, G6, G7 is
The logic level is set to "1" when the logic is "1", "0", "0", rOJ, and "1".

As shown in FIG. 5, the data select circuit 7 includes a latch circuit 71 having a 4-bit configuration, a selector circuit 72 having a JK flip-flop circuit configuration, and a switch circuit 73.

The latch circuit 71 receives 4-bit NRZ data QASQB input from the C pattern detection circuit 5.

After receiving QC and QD, 4-bit NRZ data QASQB is generated at the rising edge of the first clock GK.

QC and QD are output to the switch circuit 73.

Further, the selector circuit 72 generates first and second select signals SAB and SCD based on the first and second window detection outputs WAB and WCD input from the window detection circuit 6, and transmits them to the latch circuit 71. It outputs to the select terminals SO and SL of the switch circuit 73 at the same timing. - That is, the first window detection output WAB is logic "1" and the second window detection output WC
When D is logic "0", the first select signal SAB is logic "1" and the second select signal SCD is logic "0".
, and the first window detection output WAB becomes logic “
0” and the second window detection output WCD is logic “1”
In this case, the first select signal SAB becomes logic "0" and the second select signal SCD becomes logic "1".

In addition, the first and second window detection outputs WAB and W
When CD are both logic "0", the first and second select signals SAB and SCD maintain the previous logic level.

Note that after the digital pulse demodulation circuit 1 starts operating, the first
When the second window detection signals WAB and WCD are both logic "0", the selector circuit 72 sets the first select signal SAB to logic "1" as an initial value,
Moreover, the second select signal SCD is set to logic "0".

Here, the switch circuit 73 receives the first and second select signals SAB and SCD input to the select terminals SO and SL.
For example, the first select signal S
When AB is logic "1", the NRZ data QA and QB input to the first and second input terminals DO and Dl are output from the first and second output terminals QO and Ql, and the second select signal is outputted from the first and second output terminals QO and Ql. NRZ data QC and QD input to the third and fourth input terminals D2 and D3 when SCD is logic “1”
is output from the first and second output terminals QO and Ql.

Thus, the data select circuit 7 selects the 4-bit NRZ data QA output from the C pattern detection circuit 5.
Among SQB, QC, and QD, N according to the correct window
A combination of RZ data QA and QB or QC and QD is selected based on the first and second window detection outputs WAB and WCD of the window detection circuit 6 and sent to the shift circuit 8.

The shift circuit 8 is connected to the first output terminal QO of the switch circuit 73.
The first output data QX outputted from the first
and a second shift register 82 into which the second output data QY output from the second output terminal Q1 is input.

The first and second shift registers 81 and 82 are 4-bit shift registers, and shift operations one bit at a time in response to the rising edge of the first clock CK2 to which the first and second output data QX and QY are input. At the same time, each parallel data QXO, QX
I, QX2, QX3 and QYOlQYI, QY2, QY
3 to the first and second latch circuits 91 and 92 of the output data latch circuit 9.

Here, the output terminal QO of the first shift register 81.

Ql, Q2, and Q3 are each a first latch circuit 910
It is connected to the input terminals DO, D2 and the input terminals DO, D2 of the second latch circuit 92, and also connected to the second shift register 82.
Output terminals QO1Q1, Q2, Q3 are connected to input terminals D1, D3 of the first latch circuit 91 and input terminals D1, D3 of the second latch circuit 92, respectively.

Thus, in the configuration shown in FIG.
M” FM data MOS M1, M2, which is input in synchronization with the rising timing of the first clock CK via
M3 is sequentially processed in parallel at the timing of the first clock CK2 to obtain 2-bit NRZ data QX and QY, and the first clock CK2 is frequency-divided by 1/4 in the output data latch circuit 9 via the shift circuit 8. By latching in synchronization with the rising timing of the second clock CK8, the NRZ is made up of 8-bit parallel data.
Data NRZO to NRZ7 are obtained, and NRZ data DN consisting of serial data is further obtained via a parallel-serial conversion circuit 10.

According to the above configuration, M" input as serial data
The NRZ data DN can be obtained by converting the FM data DMM into parallel data, processing it simultaneously in parallel, converting the code, and then converting it back into serial data. Therefore, in a parallel data processing circuit,
Data can be processed at a slow processing speed of 1/2 and 1/8 of the clock cycle of the NRZ data DN.

In fact, in a digital VTR, conventionally there are 160 (
The PAL input data latch circuit 3, which required a clock frequency of 80 (MHz), uses the clock signal CK (in this case, the clock frequency of NRZ data is 80 (MHz)).
It is sufficient to operate at the timing of the clock signal CK2, which is obtained by dividing the frequency of
The frequency is approximately 0 (MHz).

Similarly, in the data select circuit 7 and shift circuit 8 that operate at the timing of the clock signal CK2, the clock frequency is 40 (MB2).

In the output data latch circuit 9 which operates at the timing of the clock signal CK8 which is further divided into 1/8, the clock frequency becomes 10 (MB2).

Therefore, in a digital VTR, the parallel processing circuit part can be configured using a logic circuit with a slow processing speed, and this part, which could conventionally only be configured using an ECL digital circuit, can be replaced with, for example, a CMO3 integrated circuit configuration. It can be done.

As a result, power consumption can be further reduced,
For example, CMO where the entire parallel processing circuit part is integrated.
3 integrated circuits.

In this way, it is possible to easily obtain a digital VTR that consumes less power as a whole and is small and inexpensive as a whole.

In the above embodiment, a case has been described in which the M''FM data is processed by cutting out each 4 bits, but the present invention is not limited to this, and may be cut out in 8 bits each, for example.

Further, in the embodiments described above, the present invention is applied to digital V
Although the case has been described in which the present invention is applied to a digital pulse demodulation circuit of a TR, the present invention is not limited to this.
(Pulse code modulation) It can be widely applied to demodulation circuits and the like.

Further, in the above-mentioned embodiment, a case was described in which the present invention was applied to an M2FM digital pulse demodulation circuit, but the present invention is not limited to this, and can be widely applied to, for example, an MFM digital pulse demodulation circuit. can.

H Effects of the Invention As described above, according to the present invention, sequentially input serial data can be processed simultaneously and in parallel, so even input data with a high repetition frequency can be processed without using logic circuits capable of high-speed switching. Can be easily modulated.

In this way, it is possible to easily obtain a digital VTR having a small and simple structure and having low power consumption as a whole.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digital pulse demodulation circuit according to the present invention, FIG. 2 is a block diagram showing its input data latch circuit and data demodulation circuit, and FIG.
4 is a block diagram showing a window detection circuit, FIG. 5 is a block diagram showing a data select circuit, a shift circuit, and an output data latch circuit, and FIGS. 6 and 7 are conventional techniques. FIG. 2 is a signal waveform diagram for explaining. 1...Digital pulse demodulation circuit, 2...
... Serial parallel conversion circuit, 3 ... Input data latch circuit, 4 ... Data demodulation circuit, 5.
...C pattern detection circuit, 6 ... Window detection circuit, 7 ... Data selection circuit, 8
......Shift circuit, 9...Output data latch circuit, 10...Parallel-serial conversion circuit. Human or data wort circuit and data 01 circuit $2
Fig. Wishido detection circuit No. 4 @ Digital selector external surface, shift 5] path and block data detection circuit $ 5 Digital pulse modification format Fig. 6

Claims (1)

[Claims] By receiving input data consisting of serial data and converting the input data into first parallel data shifted by a predetermined bit at a predetermined clock cycle, the above-mentioned first parallel data is output at the previous and subsequent clock cycles. a first data conversion circuit that outputs second parallel data having data that overlaps the first parallel data by a predetermined bit; and a first data conversion circuit that obtains third parallel data based on the second parallel data, and a code conversion circuit that refers to the parallel data and outputs fourth parallel data consisting of predetermined bits in the third parallel data; and a code conversion circuit that shifts the fourth parallel data by predetermined bits to produce fifth parallel data. and a second data conversion circuit that converts the fifth parallel data into serial data.