JP2008242209A - Lcd data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LCD driving system which is capable of lowering a frequency of a driving clock and is reducing the number of terminals. <P>SOLUTION: An LCD controller 101 transfers data DATA of respective colors of RGB display data in serial and transfers a clock having a 1/2 frequency of a clock by which the display data is sent, as a driving clock LCLK. An LCD module 102 samples the display data DATA at a leading edge and a falling edge of the driving clock LCLK. Because of serial transfer of RGB display data, the number of terminals is reduced. Since the frequency of the driving clock is 1/2 of that of the clock by which display data is sent, the frequency of the driving clock can be lowered. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an LCD data transfer system comprising an LCD (Liquid Crystal Display) module and an LCD controller for driving the LCD module.

  The LCD data transfer system includes an LCD controller and an LCD module. For example, as shown in Patent Document 1, the LCD controller sends image data, horizontal and vertical synchronization signals, and a drive clock to the LCD module.

  Here, in recent years, the number of pixels of the LCD module has increased. For example, as an LCD module disposed in a digital camera, a QVGA (Quarter VGA (Video Graphics Array)) screen has been used in the past, but recently, a VGA (Video Graphics Array) size LCD module is mounted. It is requested. Along with this, the frequency of the drive clock has increased. In addition, if each color data of R (red), G (green), and B (blue) is transferred in parallel in order to reduce the frequency of the drive clock, the number of terminals of the LCD controller increases, which hinders miniaturization.

  FIG. 23 shows an example of a conventional LCD data transfer system. In FIG. 23, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a drive clock LCLK, 8-bit display data DATA, a CS signal, an SCK signal, and a DT signal are sent between the LCD controller 701 and the LCD module 702. Here, as the display data DATA, RGB color data is serially transferred with 8 bits [7: 0].

  FIG. 24 shows an outline of a memory map, screen, and LCD screen of a conventional LCD data transfer system. As shown in FIG. 24, assuming a (320 × 240) QVGA screen, (960 × 240) color data is sent in RGB. The display rate is, for example, 54.70 fields / second, the color data clock frequency is 13.5 MHz, and the drive clock LCLK is a clock of 13.5 MHz which is equal to this.

  As shown in FIG. 25, the LCD module 702 samples the display data DATA at the rising edge of the drive clock LCLK. Thereby, the data of each color of R, G, and B can be acquired for every sample.

  FIG. 26 shows another example of a conventional LCD data transfer system. In this example, RGB color data is transferred in parallel between the LCD controller 801 and the LCD module 802. For this reason, an RDATA terminal, a GDATA terminal, and a BDATA terminal are required, and the number of terminals increases. However, since the data of each color of RGB is transferred in parallel, the frequency of the drive clock LCLK can be lowered.

  FIG. 27 shows an outline of a memory map, a screen, and an LCD screen of another example of a conventional LCD data transfer system. As shown in FIG. 27, assuming a (640 × 240) VGA screen, the display rate is, for example, 79.57 fields / second, and the clock frequency of the color data is 27 MHz.

As shown in FIG. 28, the LCD module 802 samples the display data DATA at the rising edge of the drive clock LCLK. As a result, R, G, and B color data can be acquired in parallel for each sample.
JP 2005-265939 A

  As described above, the conventional LCD data transfer system has a problem that the drive clock increases when the number of pixels of the LCD module increases. Further, when RGB color data is transferred in parallel, there is a problem that the number of terminals of the LCD controller increases.

  Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide an LCD data transfer system capable of reducing the frequency of the drive clock and reducing the number of terminals. .

The present invention proposes the following items in order to solve the above-described problems.
(1) The present invention is an LCD driving system comprising an LCD module and an LCD controller for driving the LCD module, serial transfer means for serially transferring data of each color of display data, and a clock for sending the display data Drive clock transfer means for transferring a clock having a frequency of 1/2 as a drive clock, sampling means for sampling the display data at the rising and falling edges of the drive clock, and 2/3 the frequency of the drive clock And a conversion means for converting the serial display data into parallel display data for each color at the same clock.

  (2) The present invention proposes an LCD data transfer system according to (1), wherein the display data is QVGA display data.

  (3) The LCD data transfer system according to (1) proposes an LCD data transfer system in which the display data is VGA display data.

  (4) The present invention is an LCD drive system comprising an LCD module and an LCD controller for driving the LCD module, and serial transfer means for serially transferring each color of display data into upper bits and lower bits. Driving clock transfer means for transferring, as a driving clock, a clock having a frequency half that of the clock that sent the display data, and the upper bit display data and the lower order at the rising and falling edges of the driving clock. An LCD data transfer system comprising: sampling means for sampling each bit display data; and combining means for synthesizing the upper bit display data and the lower bit display data with the drive clock. is suggesting.

  (5) The present invention is an LCD driving system comprising an LCD module and an LCD controller for driving the LCD module, and serial transfer means for serially transferring each color data and a driving signal including a synchronizing signal as display data. Driving clock transfer means for transferring, as a driving clock, a clock having a frequency ½ of the clock for sending the display data; sampling means for sampling the display data at the rising edge and falling edge of the driving clock; An LCD data transfer system comprising: a decoding means for decoding a drive signal including a synchronization signal with a drive clock.

  (6) The present invention is an LCD drive system comprising a first and second LCD module and an LCD controller for driving the first and second LCD modules, wherein display data for the first LCD module is displayed. Serial transfer means for serial transfer including each color data and each color data of display data for the second LCD module, and a clock having a frequency ½ of the clock for sending the display data as a drive clock. Drive clock transfer means; and sampling means for sampling the display data at a rising edge and a falling edge of the drive clock, wherein one of the first and second LCD modules is a rising edge of the drive clock. The display data is sampled at an edge, and the other is Proposes an LCD data transfer system characterized by sampling said display data on the falling edge of the dynamic clock.

  (7) According to the present invention, in the LCD data transfer system according to (6), the LCD controller separately supplies a drive signal including a synchronization signal to the first and second LCD modules. An LCD data transfer system is proposed.

  (8) In the LCD data transfer system according to (6), the LCD controller supplies a drive signal including a synchronization signal to the first and second LCD modules in common. An LCD data transfer system is proposed.

  According to the present invention, since the frequency of the drive clock is ½ that of the clock synchronized with the display data and sampling is performed at both the rising and falling edges of the driving clock, the driving clock frequency is lowered. And the number of terminals can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the constituent elements in the present embodiment can be appropriately replaced with existing constituent elements and the like, and various variations including combinations with other existing constituent elements are possible. Therefore, the description of the present embodiment does not limit the contents of the invention described in the claims.

<First Embodiment>
FIG. 1 shows an LCD data transfer system according to a first embodiment of the present invention.
In this embodiment, the frequency of the drive clock is halved by performing data sampling using both edges of the drive clock.

  In FIG. 1, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a drive clock LCLK, 8-bit display data DATA, a CS signal, a SCK signal, and a DT signal are sent from the LCD controller 101 to the LCD module 102. Here, as the display data DATA, RGB color data is serially transferred with 8 bits [7: 0]. The drive clock LCLK has a frequency half that of the transmission clock used by the LCD controller 101 for serial transfer of the display data DATA.

FIG. 2 shows an outline of the memory map, screen, and LCD screen of the LCD drive system of this embodiment.
As shown in FIG. 2, assuming a (320 × 240) QVGA screen, (960 × 240) color data is sent in RGB. The display rate is, for example, 54.70 fields / second, and the clock frequency of the display data is 13.5 MHz. For example, the clock frequency of the display data DATA is 13.5 MHz, while the drive clock LCLK is 6.75 MHz.

  In the LCD module 102, the display data of each color of 8-bit serial sent with the clock of the frequency of 13.5 MHz is sampled at both edges of the driving clock LCLK of 6.75 MHz of the half frequency. The parallel display data of each color of RGB is obtained by performing serial-parallel conversion with a clock of 4.5 MHz having a 1/3 frequency of 13.5 MHz.

FIG. 3 shows a specific example for performing sampling at both edges of the drive clock LCLK and performing serial-parallel conversion at a cycle three times the display data frequency to be serially transferred.
In FIG. 3, the register 11a samples the display data DATA at the rising edge of the drive clock LCLK. The register 11b samples the display data DATA at the falling edge of the drive clock LCLK.

  The register 12a delays the output of the register 11a by one clock, and the register 13a delays the output of the register 12a by one clock.

  The register 12b delays the output of the register 11b by one clock, and the register 13b delays the output of the register 12b by one clock.

  The selector 15a selects the output of the register 11a and the output of the register 11b and outputs it to the register 16a. The selector 15b selects the output of the register 12a and the output of the register 12b and outputs them to the register 16b. The selector 15c selects the output of the register 13a and the output of the register 13b and outputs the selected output to the register 16b.

  The register 16a samples the output of the selector 15a with the clock LCLK2. The register 16b samples the output of the selector 15b with the clock LCLK2. The register 16c samples the output of the selector 15c with the clock LCLK2.

FIG. 4 is a timing chart of each part.
FIG. 4A shows display data transmission clock CLK, and FIG. 4B shows display data DATA. Here, the frequency of the transmission clock CLK is 13.5 MHz. The display data is 8 bits, red data R1, R2, R3,..., Green G1, G2, G3,..., Blue B1, B2, B3,. It is input in the order of B1, R2, G2, B2,. As shown in FIG. 4C, the drive clock LCLK is half the frequency of the transmission clock CLK, and is 6.75 MHz here.

  As shown in FIG. 4D, the display data is sampled by the register 11a at the rising edge of the drive clock LCLK. Further, as shown in FIG. 4E, the display data is sampled by the register 11b at the falling edge of the drive clock LCLK.

  The output of the register 11a is delayed by one clock in the register 12a as shown in FIG. 4F, and further delayed by one clock in the register 13a as shown in FIG. 4H. The output of the register 11b is delayed by one clock in the register 12b as shown in FIG. 4G, and further delayed by one clock in the register 13b as shown in FIG. 4I.

  The clock LCK2 is a clock for converting serial color data into parallel color data, and as shown in FIG. 4J, is a clock having a frequency of 1/3 of the display data transmission clock CLK. Here, the clock LCK2 is 4.5 MHz (1/3 of the display data frequency 13.5 MHz).

  The output of the register 11a (FIG. 4D) and the output of the register 11b (FIG. 4E) are alternately selected by the selector 15a. As a result, as shown in FIG. 4K, red data R1, R2, R3,... Are output from the register 11a.

  The output of the register 12a (FIG. 4F) and the output of the register 12b (FIG. 4G) are alternately selected by the selector 15b. As a result, as shown in FIG. 4L, green data G1, G2, G3,... Are output from the register 11b.

  The output of the register 13a (FIG. 4 (H)) and the output of the register 13b (FIG. 4 (I)) are alternately selected by the selector 15c. As a result, as shown in FIG. 4L, green data B1, B2, B3,... Are output from the register 11b.

  As described above, in this embodiment, the frequency of the drive clock LCLK is set to ½ of the clock obtained by synchronizing the display data of each color of 8-bit serial, sampling is performed at both edges of the drive clock LCLK, and serial transfer is performed. By performing serial-parallel conversion at 1/3 of the display data frequency, display data in which each color of RGB is parallel can be obtained, and the drive clock frequency and the number of terminals can be reduced.

<Second Embodiment>
FIG. 5 shows the LCD data transfer system of this embodiment.
In the present embodiment, as in the first embodiment described above, between the LCD controller 201 and the LCD module 202, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a drive clock LCLK, 8-bit display data DATA, CS Signal, SCK signal, DT signal are sent. As for the display data DATA, data of each color of RGB is serially transferred with 8 bits [7: 0]. The drive clock LCLK has a frequency half that of the clock synchronized to serially transfer the display data DATA.

  FIG. 6 shows an overview of the memory map, screen, and LCD screen of the LCD drive system of this embodiment.

  As shown in FIG. 6, assuming a (640 × 480) VGA screen, (1920 × 480) color data is transmitted in RGB. The display rate is, for example, 56.47 fields / second, and the clock frequency of display data is 54 MHz. For example, the clock frequency of the display data DATA is 54 MHz, while the drive clock LCLK is 27 MHz.

  The configuration for performing sampling at both edges of the drive clock LCLK and performing serial-parallel conversion at 1/3 of the display data frequency for serial transfer is the same as in the first embodiment. FIG. 7 is a timing chart of each part. Since the operation of each part is the same as that of the first embodiment described above, description thereof is omitted.

  In the present embodiment, since the RGB color data is serially transferred, the number of terminals can be reduced by (8 × 2 = 16) compared to the conventional example shown in FIG.

<Third Embodiment>
FIG. 8 shows this embodiment.
In the present embodiment, between the LCD controller 301 and the LCD module 302, each color data is divided into upper bits and lower bits and serially transferred as display data DATA, and each color data at the rising edge of the drive clock LCLK. Are sampled, and the lower bits of the data of each color are sampled at the falling edge of the drive clock LCLK.

  As shown in FIG. 9, assuming a (320 × 240) QVGA screen, (960 × 240) color data is transmitted in RGB. The display rate is 54.70 fields / second, for example, and the clock frequency of the display data is 27 MHz because it is divided into upper bits and lower bits. For example, the clock frequency synchronized to serially transfer the display data DATA divided into upper bits and lower bits is 27 MHz, whereas the drive clock LCLK is 13.5 Hz.

FIG. 10 shows a specific example for sampling the upper bits of the data of each color at the rising edge of the driving clock LCLK and sampling the lower bits of the data of each color at the falling edge of the driving clock LCLK.
In FIG. 10, the register 31a samples the input display data DATA at the rising edge of the drive clock LCLK, and the register 31b samples the input display data DATA at the falling edge of the drive clock LCLK. The outputs of the registers 31a and 31b are taken into the register 32 by the drive clock LCLK2, and the upper bit data and the lower bit data are synthesized.

FIG. 11 is a timing chart of each part.
FIG. 11A shows the display data transmission clock CLK, and FIG. 11B shows the display data DATA. For each color data, 8-bit data is divided into upper 4-bit data (subscript H data) and lower 4-bit data (subscript L data). As shown in FIG. 11C, the frequency of the drive clock LCLK is 13.5 MHz.

  As shown in FIG. 11D, the upper bit data is sampled by the register 31a at the rising edge of the drive clock LCLK. Further, as shown in FIG. 11E, the register 31b samples lower-order bit data at the falling edge of the drive clock LCLK. The output of the register 31a (FIG. 11D) and the output of the register 31b (FIG. 11E) are supplied to the register 32 by the clock LCLK2 (FIG. 11G) as shown in FIG. The data is taken in and the driving data is composed of the upper bit data and the lower bit data.

  In the above example, the upper bits of the data of each color are sampled at the rising edge of the drive clock LCLK, and the lower bits of the data of each color are sampled at the falling edge of the drive clock LCLK. The low-order bits of the data of each color may be sampled, and the high-order bits of the data of each color may be sampled at the falling edge of the drive clock LCLK.

  As described above, in this embodiment, the upper bits of the data of each color are sampled at the rising edge of the driving clock LCLK, and the lower bits of the data of each color are sampled at the falling edge of the driving clock LCLK. The number of bits of the color data can be increased without increasing the frequency of the color or the number of terminals.

<Fourth Embodiment>
FIG. 12 shows the LCD data transfer system of this embodiment.
In this embodiment, between the LCD controller 401 and the LCD module 402, the display data DATA is sent together with the data of each color including the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the CS signal, the SCK signal, and the DT signal. I am doing so. Each color data is sampled at the rising edge of the driving clock LCLK, and at the falling edge of the driving clock LCLK, the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the CS signal, the SCK signal, the DT signal, and the like are sampled as driving signals. I have to.

FIG. 13 shows an overview of the memory map, screen, and LCD screen of the LCD drive system of this embodiment.
As shown in FIG. 13, assuming a (320 × 240) QVGA screen, (960 × 240) color data is transmitted in RGB. The display rate is 54.70 fields / second, for example, and the clock frequency of the display data is 27 MHz. For example, the clock frequency for synchronizing the display data DATA including the vertical sync signal VSYNC, horizontal sync signal HSYNC, CS signal, SCK signal, DT signal and the like as the drive signal is 27 MHz, whereas the drive clock LCLK is 13.2. 5 MHz.

FIG. 14 samples the data of each color at the rising edge of the driving clock LCLK, and samples the vertical synchronizing signal VSYNC, horizontal synchronizing signal HSYNC, CS signal, SCK signal, DT signal, etc. as the driving signal at the falling edge of the driving clock LCLK. This is a specific example.
In FIG. 14, the register 41a samples the input display data DATA at the rising edge of the drive clock LCLK, and the register 41b samples the input display data DATA at the falling edge of the drive clock LCLK. The output signal of the register 41b is taken into the decoder 42. The decoder 42 decodes and outputs drive signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a CS signal, an SCK signal, and a DT signal at the falling timing of the drive clock LCLK.

FIG. 15 is a timing chart of each part.
FIG. 15A shows the display data transmission clock CLK, and FIG. 15B shows the display data DATA. As the display data DATA, each color data R1, G1, B1,... Is transferred at the rising edge of the drive clock LCLK, and the vertical sync signal VSYNC, horizontal sync signal HSYNC, CS signal, SCK signal, DT signal, etc. Drive signals (IF1, IF2,...) Are transferred at the falling edge.

  As shown in FIG. 15D, the register 41a samples data of each color at the rising edge of the drive clock LCLK. Further, the driving signals (IF1, IF2,...) Are sampled by the register 41b at the falling edge of the driving clock LCLK. From this drive signal, as shown in FIGS. 15E to 15I, the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the CS signal, the SCK signal, and the DT signal are decoded.

  In the above-described embodiment, data of each color is sampled at the rising edge of the driving clock LCLK, and the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the CS signal, the SCK signal, the DT signal, and the like are sampled at the falling edge of the driving clock LCLK. Although sampling is performed as the drive signal, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the CS signal, the SCK signal, the DT signal, etc. are sampled as the drive signal at the rise of the drive clock LCLK, and at the fall of the drive clock LCLK, You may make it sample the data of each color.

  In the present embodiment, the display data DATA is sent together with the data of each color together with the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the CS signal, the SCK signal, and the DT signal, and at the rising edge of the drive clock LCLK, each color is transmitted. Data is sampled, and at the falling edge of the drive clock LCLK, the vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, CS signal, SCK signal, DT signal, and the like are sampled as drive signals. For this reason, the number of terminals can be reduced. Further, in this example, as shown in FIG. 12, the terminals of the LCD controller 401 can be only the terminal of the drive clock LCLK and the terminal of the display data DATA.

<Fifth Embodiment>
FIG. 16 shows this embodiment.
In the present embodiment, two LCD modules 502 a and 502 b are connected to one LCD controller 501. Then, the display data DATA, the drive clock LCLK, the SCK signal, and the DT signal are sent in common to the LCD module 502a and the LCD module 502b, and the data of each color for the LCD module 502a is sent at the rising edge of the drive clock LCLK. Sampling is performed, and data of each color for the LCD module 502b is sampled at the falling edge of the drive clock LCLK.

FIG. 17 shows an outline of the memory map, screen, and LCD screen of the LCD drive system of this embodiment.
As shown in FIG. 17, assuming that each LCD module is a (320 × 240) QVGA screen, (960 × 240) color data is sent in RGB. The display rate is 54.70 fields / second, for example, and the clock frequency of the display data is 27 MHz. For example, since data for two LCD modules is sent, the clock frequency for synchronizing the display data DATA is 27 MHz. On the other hand, the drive clock LCLK is 13.5 MHz which is a half of the frequency.

  FIG. 18 shows a specific example for sampling data of each color in each LCD module. In FIG. 18, the register 51a of the LCD module 502a samples the input display data DATA at the rising edge of the driving clock LCLK, and the register 51b of the LCD module 502b samples the input display data DATA at the rising edge of the driving clock LCLK. In this example, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the CS signal are separately sent by the LCD module 502a and the LCD module 502b.

FIG. 19 is a timing chart of each part.
FIG. 19A shows the display data transmission clock CLK, and FIG. 19B shows the display data DATA. As the display data DATA, the data of each color for the LCD module 502a is transferred at the rising edge of the drive clock LCLK, and the data of each color for the LCD module 502b is transferred at the falling edge of the driving clock LCLK.

  As shown in FIG. 19D, the register 51a of the LCD module 502a samples data of each color for the LCD module 502a at the rising edge of the drive clock LCLK. Further, as shown in FIG. 19E, the register 51b of the LCD module 502b samples the data of each color for the LCD module 502b as the drive clock LCLK falls. Further, as shown in FIGS. 19 (F) and 19 (G), a horizontal synchronization signal HSYNC is sent to the LCD module 502a and the LCD module 502a.

  The LCD module 502a is driven by a clock LCLK1 as shown in FIG. The LCD module 502a is driven by a 13.5 MHz clock LCLK2 as shown in FIG.

  In this embodiment, each color data for the LCD module 502a is sampled at the rise of the drive clock LCLK, and each color data for the LCD module 502b is sampled at the fall of the drive clock LCLK. The data of each color for the LCD module 502b may be sampled at the rising edge of the LCD module 502b, and the data of each color for the LCD module 502a may be sampled at the falling edge of the drive clock LCLK.

  In this embodiment, one LCD controller 501 can drive two LCD modules 502a and 502b independently. Further, the LCD modules 502a and 502b can be configured in exactly the same manner by providing a function for determining whether to sample data at the rising edge of the clock or to sample data at the falling edge of the clock. Alternatively, an inverter may be provided at the input terminal of the drive clock LCLK of one LCD module.

<Sixth Embodiment>
FIG. 20 shows this embodiment.
In the present embodiment, two LCD modules 602 a and 602 b are connected to the LCD controller 601. Then, the display data DATA and the drive clock LCLK are sent in common to the LCD module 602a and the LCD module 602b, the data of each color for the LCD module 602a is sampled at the rise of the drive clock LCLK, and the rise of the drive clock LCLK. The data of each color for the LCD module 602b is sampled at the fall.

  Further, in this embodiment, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the CS signal, the SCK signal, and the DT signal are sent in common to the LCD module 502a and the LCD module 502b.

FIG. 21 shows an overview of the memory map, screen, and LCD screen of the LCD drive system of this embodiment.
As shown in FIG. 21, assuming a (320 × 240) QVGA screen, (960 × 240) color data is sent in RGB. The display rate is 54.70 fields / second, for example, and the clock frequency of the display data is 27 MHz. For example, the clock frequency obtained by synchronizing the display data DATA is 27 MHz, while the drive clock LCLK is 13.5 MHz.

  The configuration for sampling the data of each color for the LCD module 602a at the rising edge of the driving clock LCLK and sampling the data of each color for the LCD module 602b at the falling edge of the driving clock LCLK is the same as in the fifth embodiment. It is the same. FIG. 22 is a timing chart of each part. Since the operation is the same as that of the fifth embodiment, the description thereof is omitted.

  In the present embodiment, the two LCD modules 502a and 502b can be independently driven by one LCD controller 501 as in the fifth embodiment. Further, the LCD modules 502a and 502b can be configured in exactly the same manner by providing a function for determining whether to sample data at the rising edge of the clock or to sample data at the falling edge of the clock. Alternatively, an inverter may be provided at the input terminal of the drive clock LCLK of one LCD module. In the present embodiment, since the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are common, the screen of the LCD module 502a and the screen of the LCD module 502b can be completely synchronized.

  The present invention is not limited to the above-described embodiments, and various modifications and applications can be made without departing from the gist of the present invention.

It is a block diagram which shows the LCD drive system of the 1st Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 1st Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a block diagram used for description of the LCD drive system of the 1st Embodiment of this invention. It is a timing chart used for description of the LCD drive system of the 1st Embodiment of this invention. It is a block diagram which shows the LCD drive system of the 2nd Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 2nd Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a timing diagram used for description of the LCD drive system of the 2nd Embodiment of this invention. It is a block diagram which shows the LCD drive system of the 3rd Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 3rd Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a block diagram used for description of the LCD drive system of the 3rd Embodiment of this invention. It is a timing diagram used for description of the LCD drive system of the 3rd Embodiment of this invention. It is a block diagram which shows the LCD drive system of the 4th Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 4th Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a block diagram used for description of the LCD drive system of the 4th Embodiment of this invention. It is a timing diagram used for description of the LCD drive system of the 4th Embodiment of this invention. It is a block diagram which shows the LCD drive system of the 5th Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 5th Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a block diagram used for description of the LCD drive system of the 5th Embodiment of this invention. It is a timing diagram used for description of the LCD drive system of the 5th Embodiment of this invention. It is a block diagram which shows the LCD drive system of the 6th Embodiment of this invention. It is explanatory drawing which shows the memory map of the LCD drive system of the 6th Embodiment of this invention, a screen, and the outline | summary of a LCD screen. It is a timing diagram used for description of the LCD drive system of the 5th Embodiment of this invention. It is a block diagram which shows an example of the conventional LCD drive system. It is explanatory drawing which shows the memory map of an example of the conventional LCD drive system, a screen, and the outline | summary of a LCD screen. It is a timing diagram used for description of an example of the conventional LCD drive system. It is a block diagram which shows the other example of the conventional LCD drive system. It is explanatory drawing which shows the outline | summary of the memory map of another example of the conventional LCD drive system, a screen, and an LCD screen. It is a timing diagram used for description of the other example of the conventional LCD drive system.

Explanation of symbols

101, 201, 301, 401, 501, 601, 701, 801 ... LCD controller, 102, 202, 302, 402, 502, 602, 702, 802 ... LCD module

Claims (8)

An LCD driving system comprising an LCD module and an LCD controller for driving the LCD module,
Serial transfer means for serially transferring data of each color of display data;
Drive clock transfer means for transferring, as a drive clock, a clock having a frequency half that of the clock that sent the display data;
Sampling means for sampling the display data at a rising edge and a falling edge of the drive clock;
Conversion means for converting the serial display data into parallel display data for each color at a clock frequency of 2/3 of the drive clock;
An LCD data transfer system comprising:   2. The LCD data transfer system according to claim 1, wherein the display data is QVGA display data.   2. The LCD data transfer system according to claim 1, wherein the display data is VGA display data. An LCD driving system comprising an LCD module and an LCD controller for driving the LCD module,
Serial transfer means for serially transferring the data of each color of the display data into upper bits and lower bits;
Drive clock transfer means for transferring, as a drive clock, a clock having a frequency half that of the clock that sent the display data;
Sampling means for sampling the upper bit display data and the lower bit display data, respectively, at the rising edge and the falling edge of the drive clock;
A combining means for combining the display data of the upper bits and the display data of the lower bits with the drive clock;
An LCD data transfer system comprising: An LCD driving system comprising an LCD module and an LCD controller for driving the LCD module,
Serial transfer means for serially transferring each color data and a drive signal including a synchronization signal as display data;
Drive clock transfer means for transferring, as a drive clock, a clock having a frequency half that of the clock that sent the display data;
Sampling means for sampling the display data at a rising edge and a falling edge of the drive clock;
Decoding means for decoding a drive signal including a synchronization signal with the drive clock;
An LCD data transfer system comprising: An LCD driving system comprising first and second LCD modules and an LCD controller for driving the first and second LCD modules,
Serial transfer means for serial transfer including each color data of display data for the first LCD module and each color data of display data for the second LCD module;
Drive clock transfer means for transferring, as a drive clock, a clock having a frequency half that of the clock that sent the display data;
Sampling means for sampling the display data at a rising edge and a falling edge of the drive clock; and
One of the first and second LCD modules samples the display data at the rising edge of the driving clock, and the other samples the display data at the falling edge of the driving clock. LCD data transfer system.   7. The LCD data transfer system according to claim 6, wherein the LCD controller supplies a driving signal including a synchronization signal separately to the first and second LCD modules.   The LCD data transfer system according to claim 6, wherein the LCD controller supplies a driving signal including a synchronization signal to the first and second LCD modules in common.

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