TWI466084B - Display controllers and methods for controlling transmission - Google Patents

Description

Display controller and transmission control method

The present invention relates to a display controller and a transmission control method, and more particularly to a display controller suitable for use in a high-resolution display panel to control a large amount of data transmission.

The display panel is currently a necessary component for portable electronic devices. In order to attract the attention of consumers, the size and/or resolution of the display panel disposed in the portable electronic device has also continued to increase. However, as the size and/or resolution of the display panel increases, many problems arise. One of the problems is that the amount of pixels is also increased. Since the amount of pixel data will increase greatly as the size and/or resolution of the display panel increases, some traditional transmission interfaces with limited transmission bandwidth, such as Serial Peripheral Interface (SPI), cannot reuse.

In order to solve this problem, a high-speed transmission interface with a wide transmission bandwidth is used, for example, a Mobile Industry Processor Interface (MIPI) having a 1 GHz transmission bandwidth, and other high-resolution display panels and display systems. Transferring pixel data between devices is a viable solution. However, once a high speed transmission interface is employed, the clock of the system must be correspondingly increased to achieve synchronization between the device and the transmission operation of the high speed transmission interface. However, some existing devices, such as display panel drive integrated circuits and flexible printed circuit boards, operate at low speed clocks and therefore cannot operate with system clocks being increased.

In view of this, a new display controller and transmission control side are needed. Method, which is suitable for high-resolution display panels to control a large amount of data transmission.

According to an embodiment of the invention, a display controller is configured to control transmission of a plurality of data bits from a data source to an image or video signal of a display module, including a data rearrangement unit and a shift register. Module and multi-channel interface controller. The data rearrangement unit is configured to rearrange the data bits received from the data source such that the data bits are substantially evenly distributed to the plurality of groups. The shift register module includes a plurality of shift registers, each for receiving a group of data bits from the data rearrangement unit, and outputting the group data bits to the display module according to a clock signal One of the multiple data lines. The multi-channel interface controller is used to control the operation of the data rearrangement unit and the shift register module.

According to another embodiment of the present invention, a transmission control method for controlling transmission of a plurality of data bits of an image or video signal includes: receiving data bits from a data source; rearranging the data bits such that The predetermined rules generally distribute the data bits evenly to the plurality of groups; and output the group data bits to one of the plurality of data lines according to a clock signal.

With the display controller and transmission control method provided by the present invention, a low clock rate can be used in the display system, and a small number of data lines can be used to simplify circuit design and layout and save circuit area.

In order to make the manufacturing, operation methods, objectives and advantages of the present invention more obvious BRIEF DESCRIPTION OF THE DRAWINGS The following is a detailed description of several preferred embodiments, which are described in detail below with reference to the accompanying drawings. FIG. 1 shows a display system according to an embodiment of the present invention. The display system 100 can include a display module 101 and a signal processing module 102. The display module 101 can include at least one display panel 110 and one driver integrated circuit 120 for driving the display panel 110. The display panel 110 can be a liquid crystal display (LCD) panel, a light-emitting diode (LED) panel, or the like. The signal processing module 102 can include at least a processor 210, a display controller 220, and a memory device 230. The processor 210 can control the operation of the signal processing module 102. According to an embodiment of the present invention, the signal processing module 102 can be a baseband processing device of a portable electronic device (not shown), and can include a plurality of hardware devices for performing baseband signal processing. The portable electronic device can be a notebook computer, a mobile phone, a portable game console, a portable multimedia player, a global positioning system, a receiver, or the like. The baseband signal processing may include, for example, but not limited to, analog to digital to digital to analog to analog conversion, gain adjustment, modulation/demodulation, encoding/decoding, or the like. It should be noted that FIG. 1 shows a simplified block diagram. In order to simplify the description, some components of a general display module and a general signal processing module are not shown in the figure.

According to an embodiment of the present invention, the display controller 220 can receive data or instructions from the driver integrated circuit 120 through a multi-channel interface (MCI) bus, or transmit data or instructions to the driver integrated circuit. 120. The multi-channel interface bus is a novel data link standard to assist the device in using a lower clock rate, for example, not exceeding Transfer and/or receive large amounts of data over 100 MHz. The multi-channel interface includes a clock pin SCL, a chip select pin SCX, and at least two data lines SDA0 and SDA1 for transmitting data and instructions. The data lines SDA0 and SDA1 can support bidirectional instruction and data transmission. According to an embodiment of the present invention, a multi-channel interface can be used to transmit high-resolution images and/or video data, for example, a quarter-video graphics array (Quarter Video Graphics Array) having a display resolution of 320×240. QVGA), widescreen quarter-video graphics array (WQVGA) with 432×240 or 400×240 display resolution, and half-size video graphics array with 480×320 display resolution (Half-size Video Graphics) Array, referred to as HVGA). Moreover, in other embodiments of the invention, the multi-channel interface busbar may be further expanded to include more than two data lines, such as three, four or more data lines, when needed. For example, when using a higher resolution display panel, the multi-channel interface bus can further include three, four or more data lines to increase the transmission bandwidth. Therefore, the multi-channel interface proposed by the present invention is not limited to the architecture of the two data lines as shown in FIG.

Figure 2 is a block diagram showing a display controller in accordance with an embodiment of the present invention. The display controller 220 can include at least a memory access unit 221, a data rearrangement unit 222, a shift register module 223, and a multi-channel interface controller 224. It is worth noting that Figure 2 shows a simplified block diagram in which some of the components required for a general display controller are not shown in the figure for simplicity of illustration. The memory access unit 221 is coupled to the external memory controller 232 and the external memory 231. According to an embodiment of the invention, the external memory controller 232 is accessible for storage in The image of the external memory 231 or the data of the video signal (for example, frame data) is transmitted to the memory access unit 221. The external memory controller 232 and the external memory 231 can be included in the memory device 230 shown in FIG. According to an embodiment of the present invention, the memory access unit 221 may be a direct memory access (DMA) controller that receives data from the external memory 231 and transmits the data to the data rearrangement unit. 222. In some embodiments, the memory access unit 221, the external memory controller 232, and the external memory 231 can be combined into a data source 200 as shown in FIG.

In accordance with an embodiment of the present invention, the data rearrangement unit 222 is configured to rearrange the data bits received from the data source 200 and to distribute the data bits substantially evenly to the plurality of groups. The shift register module 223 can include a plurality of shift registers, such as shift registers 225 and 226. According to an embodiment of the present invention, the shift register may be a first in first out (FIFO) device, each for receiving a group of data bits from the data rearranging unit 222, and The group data bit is output to one of the plurality of data lines SDA0 and SDA1 according to a clock signal CLK, wherein the data lines SDA0 and SDA1 are coupled to the display module 101 as shown in FIG. In one embodiment of the present invention, the data rearrangement unit 222 and the shift register module 223 can be implemented by a hardware device, and the multi-channel interface controller 224 is configured to control the data rearrangement unit 222 and the shift register module. The operation of group 223 allows the data bits to be rearranged according to a predetermined rule and transmitted to data lines SDA0 and SDA1 (described in more detail in the following paragraphs).

Figure 3 is a block diagram showing a display controller in accordance with another embodiment of the present invention. As mentioned above, the multi-channel interface bus can be used when needed. Further developed to include more than two data lines, for example, three, four or more data lines to increase the transmission bandwidth. In this embodiment, a display controller 320 suitable for a multi-channel interface having three data lines will be described. It is to be noted that the structure of the display controller 320 is similar to that of the display controller 220 shown in FIG. Therefore, a detailed description of each component in the display controller 320 can be referred to the description of FIG. 2, and details are not described herein again. The display controller 220 differs from the display controller 320 in that the data rearranging unit 322 is configured to distribute the data bits substantially evenly to three groups, and the shift register module 323 includes three shift registers. . Each shift register is configured to receive a group of data bits from the data rearrangement unit 322, and output the group data bits to one of the data lines SDA0, SDA1, and SDA2 according to the clock signal CLK.

Figure 4 is a block diagram showing a display controller in accordance with another embodiment of the present invention. In this embodiment, a display controller 420 suitable for a multi-channel interface having four data lines will be described. It is to be noted that the structure of the display controller 420 is similar to that of the display controller 220 shown in FIG. Therefore, the detailed description of each component in the display controller 420 can be referred to the description of FIG. 2, and details are not described herein again. The display controller 220 differs from the display controller 420 in that the data rearranging unit 422 is configured to distribute the data bits substantially evenly to the four groups, and the shift register module 423 includes four shift registers. . Each shift register is configured to receive a group of data bits from the data rearranging unit 422, and output the group data bits to one of the data lines SDA0, SDA1, SDA2, and SDA3 according to the clock signal CLK.

According to an embodiment of the invention, the image or video signal may comprise one or The data bit of multiple frames. Each frame may contain a plurality of pixels, and the content of each pixel may be represented by a complex component depending on the color space used. For example, when a red, green, and blue (RGB) color space is used to represent pixel content, the components may include red (R), green (G), and blue (B). As another example, when a luminance and chrominance (YUV) color space is used to represent pixel content, the components may include luminance (Y) and chrominance (U and V). To simplify the description, the following embodiment will take the red, green and blue (RGB) color space as an example. However, it is worth noting that the invention is not limited to the use of red, green and blue (RGB) color spaces.

In accordance with an embodiment of the present invention, each component may represent pixel content in the form of a plurality of data bits, and the data bits of the image or video signal may include data bits of the components. For example, for the color format RGB565, the red (R), green (G), and blue (B) components use 5, 6, and 5 bits to represent pixel content, respectively. As another example, for the color format RGB666, each of the red (R), green (G), and blue (B) components uses 6 bits to represent the pixel content. As another example, for the color format RGB888, each of the red (R), green (G), and blue (B) components uses 8 bits to represent the pixel content.

As described above, the multi-channel interface controller 224 is configured to control a data rearrangement unit (eg, the data rearrangement unit 222, 322 or 422) and a shift register module (eg, a shift register module 223, The operation of 323 or 423) causes the data bits to be rearranged and transmitted to the data line according to established rules. According to the first aspect of the present invention, the established rule may be that the plurality of data bits belonging to the same component in one pixel are simultaneously transmitted to different data lines. Figure 5 is a diagram showing the upcoming embodiment according to the first aspect of the present invention. The color format transmitted to different data lines is the rearranged data bits of RGB565. In Figure 5, the data bits are rearranged for a multi-channel interface containing two, three, and four data lines according to established rules. In this embodiment, the color format is RGB565, so the content of one pixel is represented by 16 bits, and the 16-bit includes bits R4, R3, R2, R1, R0, G5, G4, G3, G2, G1. G0, B4, B3, B2, B1 and B0, wherein R0, G0 and B0 are the least significant bits (LSB) of the red (R), green (G) and blue (B) components, respectively. It is worth noting that since the data line can be used to transmit both the command and the data, before transmitting the data bit, a preferred method is to first transmit an indicator bit A0 to indicate that the next bit is a data bit.

As shown in FIG. 5, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to the same component in one pixel can be simultaneously transmitted to different pixels. Information line. For example, for a multi-channel interface with two data lines, the data bits R4 and R3 of the red (R) component are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For a multi-channel interface with three data lines, the red (R) component data bits R4, R3 and R2 are simultaneously transmitted to different data lines SDA0, SDA1 and SDA2, respectively. For a multi-channel interface with four data lines, the red (R) component data bits R4, R3, R2 and R1 are simultaneously transmitted to different data lines SDA0, SDA1, SDA2 and SDA3, respectively. Based on established rules, consecutive data bits belonging to a component in a pixel (eg, data bits R4 and R3) are simultaneously transmitted to different data lines.

Figure 6 is a diagram showing the rearrangement of the color format to be transmitted to different data lines as RGB 666 according to the embodiment of the first aspect of the present invention. The data bit passed. In this embodiment, the color format is RGB666, therefore, the use of the included bits R5, R4, R3, R2, R1, R0, G5, G4, G3, G2, G1, G0, B5, B4, B3, B2, B1 is used. And 18 bits of B0 represent the content of a pixel. As shown in FIG. 6, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to the same component in one pixel are simultaneously transmitted to different data. line. For example, for a multi-channel interface with two data lines, the green (G) component data bits G5 and G4 are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For a multi-channel interface with three data lines, the green (G) component data bits G5, G4 and G3 are simultaneously transmitted to different data lines SDA0, SDA1 and SDA2, respectively. For a multi-channel interface with four data lines, the green (G) component data bits G3, G2, G1 and G0 are simultaneously transmitted to different data lines SDA0, SDA1, SDA2 and SDA3, respectively. Based on established rules, consecutive data bits belonging to a component of a pixel (eg, data bits G5 and G4) are simultaneously transmitted to different data lines.

Figure 7 is a diagram showing the rearranged data bits of the color format RGB888 to be transmitted to different data lines according to the embodiment of the first aspect of the present invention. In this embodiment, the color format is RGB888, therefore, the use includes bits R7, R6, R5, R4, R3, R2, R1, R0, G7, G6, G5, G4, G3, G2, G1, G0, B7. The 24-bits of B6, B5, B4, B3, B2, B1, and B0 represent the content of one pixel. As shown in FIG. 7, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to the same component in one pixel are simultaneously transmitted to different data. line. For example, for having The multi-channel interface of the two data lines, the data bits B7 and B6 of the blue (B) component are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For a multi-channel interface with three data lines, the data bits B5, B4 and B3 of the blue (B) component are simultaneously transmitted to different data lines SDA0, SDA1 and SDA2, respectively. For a multi-channel interface with four data lines, the data bits B7, B6, B5 and B4 of the blue (B) component are simultaneously transmitted to different data lines SDA0, SDA1, SDA2 and SDA3, respectively. Based on established rules, consecutive data bits belonging to a component in a pixel (eg, data bits B5 and B4) are simultaneously transmitted to different data lines. It should be noted that the data lines as shown in Figures 5, 6 and 7 are not limited to data bits transmitting only a specific color component, and may also be used to transmit data bits of two or more color components. .

According to the second aspect of the present invention, the predetermined rule may be that the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data lines. Figure 8 is a diagram showing the rearranged data bits of the color format RGB565 to be transferred to different data lines according to the embodiment of the second aspect of the present invention. In this embodiment, the color format is RGB565, so 16-bit elements are used to represent the content of one pixel. As shown in FIG. 8, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data. line. For example, for a multi-channel interface with two data lines, the data bits R4 and G2 of the red (R) and green (G) components are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For multi-channel interfaces with three data lines, data bits R4, G5 and B4 of red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines. SDA0, SDA1 and SDA2. For multi-channel interfaces with four data lines, the data bits R4, R0, G2 and B3 of the red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines SDA0, SDA1, respectively. SDA2 and SDA3. Based on the established rules, consecutive data bits (eg, R4, R3, R2, etc.) belonging to a component in a pixel are sequentially transmitted to a data line.

Figure 9 is a diagram showing the rearranged data bits of the color format of RGB 666 to be transmitted to different data lines according to the embodiment of the second aspect of the present invention. In this embodiment, the color format is RGB666, so 18 bits are used to represent the content of one pixel. As shown in FIG. 9, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data. line. For example, for a multi-channel interface with two data lines, the data bits R5 and G2 of the red (R) and green (G) components are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For multi-channel interfaces with three data lines, data bits R5, G5 and B5 of red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines SDA0, SDA1 and SDA2, respectively. For multi-channel interfaces with four data lines, data bits R5, R1, G3 and B4 of red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines SDA0, SDA1, respectively. SDA2 and SDA3. Based on the established rules, consecutive data bits (eg, R5, R4, R3, etc.) belonging to a component in a pixel are sequentially transmitted to a data line.

Figure 10 is a diagram showing the rearrangement of the color format to be transmitted to different data lines as RGB888 according to the embodiment of the second aspect of the present invention. The data bits listed. In this embodiment, the color format is RGB888, so 24 bits are used to represent the content of one pixel. As shown in FIG. 10, the data rearrangement unit (for example, the data rearrangement unit 222, 322 or 422) rearranges the data bits so that the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data. line. For example, for a multi-channel interface with two data lines, the data bits R7 and G3 of the red (R) and green (G) components are simultaneously transmitted to different data lines SDA0 and SDA1, respectively. For multi-channel interfaces with three data lines, data bits R7, G7 and B7 of red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines SDA0, SDA1 and SDA2, respectively. For multi-channel interfaces with four data lines, the data bits R7, R1, G3 and B5 of the red (R), green (G) and blue (B) components are simultaneously transmitted to different data lines SDA0, SDA1, respectively. SDA2 and SDA3. In this way, consecutive data bits (eg, R7, R6, R5, etc.) belonging to a component in a pixel are sequentially transmitted to a data line. It should be noted that in the second aspect of the present invention, for a multi-channel interface having three data lines, data elements belonging to different components in one pixel are transmitted to different data lines. For example, as shown in Fig. 10, the data bits R7~R0 of the red (R) component are sequentially transmitted to the data line SDA0, and the data bits G7~G0 of the green (G) component are sequentially transmitted to the data. Line SDA1, and the data bits B7~B0 of the blue (B) component are sequentially transmitted to the data line SDA2. Similar results can be achieved with RGB565 and RGB666 as shown in Figures 8 and 9. It should be noted that the data lines as shown in Figures 8, 9, and 10 can be used to transmit data bits of up to two specific color components, thereby enabling the circuit of the driver integrated circuit 120 to be optimized. To restore the original data bit order of all color components.

According to an embodiment of the present invention, the data rearrangement unit may include at least one temporary memory for temporarily storing the data bit, and at least one multiplexer module coupled to the temporary memory for multiplexing processing Temporary data bits. Figure 11 is a block diagram showing a data rearrangement unit according to an embodiment of the present invention. The data rearrangement unit 522 can be applied to a multi-channel interface having two data lines and coupled to two shift registers 525 and 526. The data rearrangement unit 522 can include registers 401 and 402 and multiplexer modules 501 and 502. The register 401 is configured to temporarily store the data bits received from the data source 200 as shown in FIG. The size of the register 401 can be designed according to the bus bar bandwidth to which the data source 200 is coupled. For example, the size of the register 401 can be 32 bits, 64 bits, 128 bits, or the like.

It is assumed that in the embodiment of the present invention, the register 401 is a 32-bit scratchpad, and can be further divided into four sub-registers Reg-0, Reg-1, Reg-2 as shown in FIG. With Reg-3. Each sub-storage device is used to temporarily store data of one character (ie, 8-bit). Therefore, for the pixel data of the color format RGB888, in a first time interval, the sub-registers Reg-0, Reg-1, Reg-2 and Reg-3 can be used to temporarily store the pixels belonging to the first pixel. Information on the red, green, and blue components of the octet and the red component of the octet of the second pixel. Then, in a second time interval, the sub-registers Reg-0, Reg-1, Reg-2, and Reg-3 can be used to temporarily store the green and blue components of the 8-bit element belonging to the second pixel. The information and the information on the red and green components of the 8-bit element of the 3rd pixel, and so on.

The multiplexer module 501 can include one or more multiplexers for multiplexing data bits temporarily stored in the temporary memory 401 in response to a set of control signals Ctrl_1 received from the multi-channel interface controller 224. Assigned to the scratchpad 402. The register 402 can be a 24-bit register and can be further divided into 3 sub-registers, such as R, G and B as shown in FIG. Each sub-storage device is used to store data of one character (ie, 8-bit) of a component (eg, one of red, green, and blue components). It should be noted that, according to other embodiments of the present invention, the register 402 can also be replaced by three lines or data busses coupled between the multiplexer modules 501 and 502. Therefore, the present invention is not limited to the structure shown in Fig. 11.

Figure 12 is a block diagram showing a multiplexer module 501 according to an embodiment of the present invention. The multiplexer module 501 can include three multiplexers 511, 512, and 513. Each multiplexer is coupled between the sub-registers Reg-0, Reg-1, Reg-2, and Reg-3 of the register 401 and one of the sub-registers R, G, and B of the register 402. The data bit multiplexed temporarily stored in the temporary memory 401 is allocated to the temporary memory 402 in response to a set of control signals Ctrl_1 received from the multi-channel interface controller 224. After the multiplex processing, the data bits of the three components of each pixel are extracted from the plurality of data bits received from the data source and temporarily stored in the temporary memory 402.

Figure 13 is a block diagram showing a multiplexer module 502 according to an embodiment of the present invention. The multiplexer module 502 can include two multiplexers 521 and 522. Each multiplexer is coupled between one of the sub-registers R, G, and B of the register 402 and the shift registers 525 and 526 (represented by reference numerals SR0 and SR1, respectively, in FIG. 13). In response to a set of control signals Ctrl_2 received from the multi-channel interface controller 224, the data bit multiplexed temporarily stored in the register 402 is multiplexed to the shift register 525 according to the established rules described above. With 526. The multiplexed (i.e., rearranged) data bits are further transferred to the data lines by shift registers 525 and 526. Examples of the rearranged results and corresponding descriptions can be found in Figures 5-10, and will not be repeated here.

Although the block diagram of the data rearrangement unit shown in Figures 11-13 is applicable to a multi-channel interface having two data lines, it must be noted that those skilled in the art can easily derive from the above that it is suitable for having three lines, Design of a data rearrangement unit for multi-channel interfaces of four or more data lines. Therefore, the present invention is not limited to the contents shown in Figures 11-13. In addition, it must be noted that those skilled in the art will understand that the data rearrangement unit can be implemented using other hardware devices and perform substantially the same functions as described in the above embodiments or achieve substantially the same results. Therefore, the present invention is not limited to the contents shown in Figures 11-13.

Figure 14 is a flow chart showing a method of controlling transmission of a plurality of data bits of an image or video signal according to an embodiment of the present invention. First, a data bit is received from a data source (step S1402). Next, the data bits are rearranged such that the data bits are substantially evenly distributed to the plural group according to a predetermined rule (step S1404). According to the first aspect of the present invention, according to the predetermined rule, data bits belonging to the same component in one pixel are simultaneously transmitted to different data lines. In this way, consecutive data bits belonging to a component in a pixel are simultaneously transmitted to different data lines as shown in Figures 5-7. That is, the operation of rearranging the data bits may cause the data lines to be not limited to data bits that exclusively carry a color component. According to the second aspect of the present invention, according to the predetermined rule, data bits belonging to different components in one pixel are simultaneously transmitted to different data lines. In this way, consecutive data bits belonging to a component in a pixel are sequentially transmitted to a data line as shown in FIGS. 8-10. That is, the operation of rearranging the data bits can be As a result, each data line is exclusively dedicated to data bits carrying up to two color components. In other embodiments, according to the established rule, when the multi-channel interface has three data lines, the data bits of one component of one pixel are transmitted to a specific data line, and the data bits of the three data lines are rearranged. The results can be referred to the contents shown in Figure 8-10. Finally, each group of data bits is output to one of the plurality of data lines according to a clock signal (step S1406).

It is worth noting that in traditional designs, in order to process large amounts of data for high-resolution display panels, extremely high clock rates are required. However, in embodiments of the invention, the display system can use a low clock rate of no more than 100 MHz. Therefore, the system clock rate does not have to be increased to a high clock rate as used in conventional designs, and peripheral devices do not have to operate at high clock rates. In addition, unlike other conventional designs that require a large number of data lines to support high-speed data transmission in order to process a large amount of data of a high-resolution display panel, the display system requires only a small number of data lines in accordance with the concept of the present invention. Therefore, circuit design and layout can be simplified, and circuit area can be saved.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Display system

101‧‧‧ display module

102‧‧‧Signal Processing Module

110‧‧‧ display panel

120‧‧‧Drive integrated circuit

200‧‧‧Source

210‧‧‧ processor

220, 320, 420‧‧‧ display controller

221‧‧‧Memory access unit

222, 322, 422, 522‧‧‧ data rearrangement unit

223, 323, 423‧‧‧ shift register module

224‧‧‧Multi-channel interface controller

225, 226, 525, 526, SR0, SR1‧‧‧ shift register

230‧‧‧ memory device

231‧‧‧External memory

232‧‧‧External memory controller

401, 402‧‧‧ register

501, 502‧‧‧ multiplexer module

511, 512, 513, 521, 522‧‧‧ multiplexers

B, R, G, Reg-0, Reg-1, Reg-2, Reg-3‧‧‧ sub-registers

CLK, Ctrl_1, Ctrl_2‧‧‧ signals

SCL, SCX‧‧‧ pins

SDA0, SDA1, SDA2, SDA3‧‧‧ data line

Figure 1 shows a display system in accordance with an embodiment of the present invention.

2 is a diagram showing display control according to an embodiment of the present invention Block diagram.

Figure 3 is a block diagram showing a display controller in accordance with another embodiment of the present invention.

Figure 4 is a block diagram showing a display controller according to still another embodiment of the present invention.

Figure 5 is a diagram showing the rearranged data bits of the color format RGB565 to be transferred to different data lines according to the first aspect of the present invention.

Figure 6 is a diagram showing the rearranged data bits of the color format of RGB 666 to be transmitted to different data lines according to the embodiment of the first aspect of the present invention.

Figure 7 is a diagram showing the rearranged data bits of the color format RGB888 to be transmitted to different data lines according to the embodiment of the first aspect of the present invention.

Figure 8 is a diagram showing the rearranged data bits of the color format RGB565 to be transferred to different data lines according to the embodiment of the second aspect of the present invention.

Figure 9 is a diagram showing the rearranged data bits of the color format of RGB 666 to be transmitted to different data lines according to the embodiment of the second aspect of the present invention.

Figure 10 is a diagram showing the rearranged data bits of the color format RGB888 to be transmitted to different data lines according to the embodiment of the second aspect of the present invention.

Figure 11 is a block diagram showing a data rearrangement unit according to an embodiment of the present invention.

Figure 12 is a block diagram showing a multiplexer module according to an embodiment of the present invention.

Figure 13 is a block diagram showing a multiplexer module according to another embodiment of the present invention.

Figure 14 is a flow chart showing a method of controlling transmission of a plurality of data bits of an image or video signal according to an embodiment of the present invention.

200‧‧‧Source

220‧‧‧ display controller

221‧‧‧Memory access unit

222‧‧‧Data rearrangement unit

223‧‧‧Shift register module

224‧‧‧Multi-channel interface controller

225, 226‧‧‧ shift register

231‧‧‧External memory

232‧‧‧External memory controller

CLK‧‧‧ signal

SDA0, SDA1‧‧‧ data line

Claims (22)

A display controller for controlling transmission of a plurality of data bits from a data source to an image or video signal of a display module, comprising: a data rearrangement unit for rearranging the data source received from the data source The data bits are such that the data bits are substantially evenly distributed to the plurality of group data bits; a shift register module, including a plurality of shift registers, each for rearranging from the data The unit receives one of the group data bits and outputs the group data bit to one of the plurality of data lines, wherein the data lines are coupled to the display module according to a clock signal And a multi-channel interface controller for controlling the operation of the data rearrangement unit and the shift register module. The display controller of claim 1, wherein the data rearrangement unit comprises: at least one temporary memory for temporarily storing the data bits; and at least one multiplexer module coupled to The at least one temporary register is configured to multiplex the temporarily stored data bits. The display controller of claim 1, wherein the content of each pixel in the image or video signal is represented by a plurality of components, and the data bits of the image or video signal comprise the components Multiple data bits. The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that the plurality of data bits belonging to the same component in one pixel are simultaneously transmitted to different data lines. The display controller of claim 3, wherein the display controller The data rearrangement unit rearranges the data bits such that the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data lines. The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that consecutive data bits belonging to a component in one pixel are sequentially transmitted to a data line. . The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that consecutive data bits belonging to a component in one pixel are simultaneously transmitted to different data lines. . The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that the plurality of data bits belonging to different components in one pixel are transmitted to different data lines. The display controller of claim 3, wherein the components of the pixel comprise color, brightness, and/or chromaticity. The display controller of claim 1, wherein the clock rate of one of the clock signals does not exceed 100 MHz. The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that each data line is not limited to a plurality of data bits carrying only a specific component. The display controller of claim 3, wherein the data rearrangement unit rearranges the data bits such that each data line carries only a plurality of data bits of up to two specific components. A transmission control method for controlling transmission of a plurality of data bits of an image or video signal, comprising: receiving the data bits from a data source; rearranging the data bits to make the data according to an established rule The data bits are generally evenly distributed to the plurality of group data bits; and the group data bits of the group data bits are output to one of the plurality of data lines according to a clock signal. The transmission control method of claim 13, wherein the step of rearranging the data bits further comprises: temporarily storing the data bits received from the data source; and according to the predetermined rule The data bits that are temporarily stored are processed to substantially equally distribute the data bits to the groups. The transmission control method of claim 13, wherein the content of each pixel in the image or video signal is represented by a plurality of components, and the data bits of the image or video signal comprise the components Multiple data bits. The transmission control method according to claim 15, wherein according to the predetermined rule, the plurality of data bits belonging to the same component in one pixel are simultaneously transmitted to different data lines. The transmission control method according to claim 15, wherein according to the predetermined rule, the plurality of data bits belonging to different components in one pixel are simultaneously transmitted to different data lines. The transmission control method according to claim 15, wherein according to the predetermined rule, consecutive data bits belonging to a component in a pixel are sequentially transmitted to a data line. The transmission control method according to claim 15, wherein according to the predetermined rule, consecutive data bits belonging to a component in one pixel are simultaneously transmitted to different data lines. A transmission control method as described in claim 15 of the patent application, According to the established rule, the plurality of data bits belonging to different components in one pixel are transmitted to different data lines. The transmission control method of claim 15, wherein the components of the pixel include color, brightness, and/or chromaticity. The transmission control method according to claim 13, wherein one of the clock signals has a clock rate of not more than 100 MHz.