JP2011097279A - Data processing circuit, integrated circuit apparatus, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing circuit capable of eliminating the necessity of previously executing pixel format conversion or color conversion at a transfer source of image data and thus reducing a burden on the transfer source, to provide an integrated circuit apparatus, and to provide electronic equipment. <P>SOLUTION: The data processing circuit 1A receives a first pixel data signal 2a transmitted via a first bus 2, and converts the received signal into a second pixel data signal 3a to be transmitted via a second bus 3. A register 30 stores first setting information 31 for specifying an arrangement order of a plurality of first pixel element data in the first pixel data signal 2a. A first format conversion section 10 extracts the plurality of first pixel element data with a given reference bit from the first pixel data signal 2a as the head on the basis of the first setting information 31, and generates a pixel data signal 12. A color conversion section 20 converts the pixel data signal 12 into a pixel data signal 22 in accordance with a conversion formula from a first color space to a second color space. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data processing circuit, an integrated circuit device, an electronic device, and the like.

  Electronic devices that process image data, such as projectors and printers, are widely used, and as the miniaturization of semiconductor processes progresses, an image processing apparatus included in these electronic devices is one in which a CPU and an image processing circuit are incorporated. It is realized by IC. Such an image processing IC may require processing for transferring image data read from a memory connected to a general-purpose bus to an image processing circuit via a video bus under the control of the CPU. Since the general-purpose bus and the video bus operate using different bus protocols, the image data transferred from the memory via the general-purpose bus is transferred via the video bus in order to realize this image data transfer processing. A data processing circuit for converting the image data into possible image data is required.

JP 2001-45458 A JP-A-10-6577 JP 2008-276356 A

  However, the conventional data processing circuit only performs bus protocol conversion. If image data pixel format conversion processing and RGB to YUV color conversion processing are required, the CPU expands the image data in the memory. After these conversion processes are performed, the converted image data is transferred to the data processing circuit via the general-purpose bus. In this method, since the CPU performs the pixel format conversion process and the color conversion process, if the transfer amount of the image data per unit time increases, there may be a problem that the CPU process cannot keep up.

  The present invention has been made in view of the above problems, and according to some aspects of the present invention, it is not necessary to perform pixel format conversion or color conversion in advance at the image data transfer source, and therefore It is possible to provide a data processing circuit, an integrated circuit device, and an electronic device that can reduce a load of a transfer source.

  (1) The present invention receives a first pixel data signal transmitted via a first bus according to a first protocol, and transmits a second pixel transmitted via a second bus according to a second protocol. A data processing circuit for converting to a data signal, including a register unit, a first format conversion unit, and a color conversion unit, wherein the first pixel data signal is in a given first color space. A plurality of first pixel element data for specifying color information to be defined, wherein the second pixel data signal is for specifying color information defined in a given second color space; A plurality of second pixel element data, and the register unit stores first setting information for specifying an arrangement order of the plurality of first pixel element data in the first pixel data signal. , The first format conversion unit is configured to output the first format conversion unit. A plurality of first pixel element data starting from a given reference bit from the first pixel data signal based on constant information, and a first pixel format including the plurality of first pixel element data And the color conversion unit generates the pixel data signal generated by the first format conversion unit according to a given conversion formula from the first color space to the second color space. Is a data processing circuit that converts the data into a pixel data signal including the plurality of second pixel element data.

  According to the present invention, the first pixel data signal transmitted through the first bus is subjected to pixel format conversion and color conversion, and the second pixel data signal transmitted through the second bus. Therefore, it is not necessary to perform pixel format conversion or color conversion in advance at the transfer source of the first pixel data signal, so that the load on the transfer source can be reduced.

  Further, according to the present invention, the arrangement order of the plurality of first pixel element data in the first pixel data signal of a specific pixel format can be specified by the first setting information. Therefore, even if the arrangement order of the plurality of first pixel element data in the first pixel data signal is variable, by changing the first setting information in advance according to the arrangement order, the plurality of first pixels The element data can be extracted to generate a pixel data signal in the first pixel format. Therefore, according to the present invention, the flexibility of the pixel format conversion process can be improved.

  (2) In the data processing circuit, the register unit stores second setting information for specifying the reference bit of the first pixel data signal, and the first format conversion unit includes the first format conversion unit. The plurality of first pixel element data may be extracted from the first pixel data signal based on one setting information and the second setting information.

  According to the present invention, it is possible to specify a reference bit serving as a reference for the arrangement order of the plurality of first pixel element data by the second setting information. Therefore, even if the position of the reference bit of the first pixel data signal is variable, a plurality of first pixel element data is extracted by changing the second setting information in advance according to the position of the reference bit. Thus, a pixel data signal in the first pixel format can be generated. Therefore, according to the present invention, the flexibility of the pixel format conversion process can be further improved.

  (3) In this data processing circuit, the register unit sets a third setting for specifying whether or not the reference bit of the first pixel data signal is a part of the first pixel element data. Information is stored, and the first format conversion unit determines whether or not to extract the reference bit as a part of the first pixel element data based on the third setting information. Good.

  According to the present invention, based on the third setting information, whether or not the reference bit serving as a reference for the arrangement order of the plurality of first pixel element data is a part of the first pixel element data (that is, effective). Whether it is data or not). Therefore, even when the reference bit of the first pixel data signal can be both valid and invalid, the third setting information is changed in advance according to whether the reference bit is valid or invalid. The plurality of first pixel element data can be extracted to generate a pixel data signal in the first pixel format. Therefore, according to the present invention, the flexibility of the pixel format conversion process can be further improved.

  (4) In this data processing circuit, when the number of bits of each of the plurality of first pixel element data extracted from the first pixel data signal is m, For each piece of pixel element data, the upper n bits (n ≦ m) may be added to the lower n bits and bit expanded to m + n bits to generate a pixel data signal of the first pixel format.

According to the present invention, when the value of the first pixel element data is the maximum value that can be represented by m bits, that is, 2 ^m −1 (all bits are 1), the pixel data signal of the first pixel format is also m + n bits. The maximum value that can be expressed, that is, 2 ^{m + n} −1 (all bits are 1). When the value of the first pixel element data is the minimum value that can be represented by m bits, that is, 0 (all bits are 0), the pixel data signal of the first pixel format is also the minimum value that can be represented by m + n bits, that is, 0 (all Is 0). Therefore, since the m + n bit range (0 to 2 ^{m + n} −1) can be used to the maximum extent, errors associated with the bit expansion of the pixel data signal can be minimized.

  (5) The data processing circuit further includes a second format conversion unit and a pixel data selection unit, and the first pixel data signal has any one of a plurality of types of pixel formats. And the register unit includes fourth setting information for specifying a pixel format of the first pixel data signal, and the plurality of first pixels in the first pixel data signal having a predetermined pixel format. 5th setting information for specifying arrangement | positioning of element data is memorize | stored, and the said 2nd format conversion part is the said 1st pixel data signal of the said predetermined pixel format based on the said 5th setting information The plurality of first pixel element data is extracted from the first pixel element data, a pixel data signal of a second pixel format including the plurality of first pixel element data is generated, and the pixel data The data selection unit selects either the pixel data signal generated by the first format conversion unit or the pixel data signal generated by the second format conversion unit based on the fourth setting information. The color conversion unit is generated by the first format conversion unit selected by the pixel data selection unit according to a given conversion formula from the first color space to the second color space. The pixel data signal or the pixel data signal generated by the second format conversion unit may be converted into a pixel data signal including the plurality of second pixel element data.

  According to the present invention, the arrangement of the plurality of first pixel element data in the first pixel data signal of a predetermined pixel format can be specified by the fifth setting information. Therefore, even if the arrangement of the plurality of first pixel element data in the first pixel data signal of the predetermined pixel format is variable, by changing the fifth setting information in advance according to the arrangement, The first pixel element data can be extracted to generate a pixel data signal in the second pixel format. Furthermore, the pixel format of the first pixel data signal can be specified by the fourth setting information. Therefore, even when the pixel format of the first pixel data signal is variable, the pixel data signal of the first pixel format or the second pixel can be changed by changing the fourth setting information in advance according to the pixel format. Color conversion processing can be performed by selecting a pixel data signal in the format. Therefore, according to the present invention, the pixel format conversion process and the color conversion process can be performed even when the pixel format of the first pixel data signal is variable.

  (6) In this data processing circuit, when the number of bits of each of the plurality of first pixel element data extracted from the first pixel data signal is j, For each piece of pixel element data, the upper k bits (k ≦ j) may be added to the lower k bits and bit extended to j + k bits to generate a pixel data signal of the second pixel format.

According to the present invention, when the value of the first pixel element data is the maximum value that can be represented by j bits, that is, 2 ^j −1 (all bits are 1), the pixel data signal of the second pixel format is also j + k bits. The maximum value that can be expressed, that is, 2 ^{j + k} −1 (all bits are 1). In addition, when the value of the first pixel element data is the minimum value that can be expressed by j bits, that is, 0 (all bits are 0), the pixel data signal of the second pixel format is also the minimum value that can be expressed by j + k bits, that is, 0 (all Is 0). Therefore, since the j + k bit range (0 to 2 ^{j + k} −1) can be used to the maximum extent, errors associated with the bit expansion of the pixel data signal can be minimized.

  (7) The present invention is an integrated circuit device including any of the data processing circuits described above.

  In the integrated circuit device, a pixel format of the first pixel data signal is determined based on an external signal, and at least one of the first to fifth setting information is stored in the register unit included in the data processing circuit. You may make it include the setting part to set.

  (8) The present invention is an electronic apparatus including the integrated circuit device described above.

The functional block diagram of the data processing circuit of 1st Embodiment. The figure which shows an example of the specific structure of the data processing circuit of 1st Embodiment. The figure which shows an example of the format of RGB data. The figure which shows an example of a specific structure of an RGB format conversion circuit. The figure for demonstrating specification of the bit position of R, G, B. FIG. The figure which shows an example of the bit expansion by a bit expansion circuit. The figure which shows an example of the operation timing of the data processing circuit of 1st Embodiment. The functional block diagram of the data processing circuit of 2nd Embodiment. The figure which shows an example of the specific structure of the data processing circuit of 2nd Embodiment. The figure which shows an example of the format of YUV422 data. The figure which shows an example of the specific structure of a YUV format conversion circuit. The figure which shows the truth table of the selection logic of a selection circuit. The figure which shows an example of the bit expansion by a bit expansion circuit. The figure which shows an example of the operation timing of the data processing circuit of 2nd Embodiment. 1 is a block diagram of a projector as an example of an electronic apparatus according to an embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Data Processing Circuit (1) First Embodiment FIG. 1 is a functional block diagram of a data processing circuit according to a first embodiment.

  The data processing circuit 1A according to the first embodiment receives the first pixel data signal 2a transmitted via the first bus 2 according to the first protocol, and via the second bus 3 according to the second protocol. A process of converting to the second pixel data signal 3a to be transmitted is performed.

  The first bus may be a dedicated bus for transmitting the first pixel data signal 2a, or a general-purpose bus capable of transmitting not only the first pixel data signal 2a but also other data signals. There may be. Similarly, the second bus 3 may be a dedicated bus for transmitting the second pixel data signal 3a, and may transmit not only the second pixel data signal 3a but also other data signals. It can be a general purpose bus.

  The first pixel data signal 2a has a plurality of first pixel element data for specifying color information defined in the first color space, and the second pixel data signal 3a has a second color. A plurality of second pixel element data for specifying color information defined in the space is included.

  The first color space and the second color space are, for example, RGB (Red-Green-Blue), RGBA (Red-Green-Blue-Alpha), YUV (generic name such as YCbCr, YPbPr), CMY (Cyan-Magenta). -Yellow). For example, if the first color space is an RGB space, the first pixel data signal 2a is a pixel data signal (hereinafter, “ The plurality of first pixel element data are R, G, and B data. Further, for example, if the first color space is a YUV space, the first pixel data signal 2a is a pixel data signal (hereinafter referred to as a pixel data signal) expressing the color information defined in the YUV space by three data of Y, U, and V. , Referred to as “YUV data signal”), and the plurality of first pixel element data are Y, U, and V data.

  The data processing circuit 1A includes a first format conversion unit 10, a color conversion unit 20, and a register unit 30.

  The register unit 30 stores at least first setting information 31. The first setting information 31 specifies the arrangement order of a plurality of first pixel element data (for example, R, G, and B data) in the first pixel data signal 2a (for example, RGB data signal). Information.

Based on the first setting information 31, the first format conversion unit 10 starts with a given reference bit (bit b _x ) from the first pixel data signal 2 a (for example, RGB data signal) as a plurality. First pixel element data (for example, R, G, B data) is extracted, and the first pixel format includes the plurality of first pixel element data (for example, R, G, B data). The pixel data signal 12 is generated.

The register unit 30 may further store second setting information 32. Second setting information 32 is information for identifying the reference bit b _x of the first pixel data signal 2a.

  Then, the first format conversion unit 10 generates a plurality of first pixel elements from the first pixel data signal 2a (eg, RGB data signal) based on the first setting information 31 and the second setting information 32. You may perform the process which takes out data (for example, each data of R, G, B).

The register unit 30 may further store third setting information 33. Third setting information 33, the reference bit b _x of the first pixel data signal 2a is first pixel element data (for example, R, G, and one of the data of B) whether it is part of This is information for identification.

Then, the first format conversion unit 10 uses the reference bit b _x as a part of the first pixel element data (for example, any data of R, G, B) based on the third setting information 33. You may make it perform the process which determines whether it takes out.

  The first format conversion unit 10 also includes a plurality of pieces of first pixel element data (for example, R, G, and B data) extracted from the first pixel data signal 2a (for example, RGB data signal). When the number of bits is m, the upper n bits (n ≦ m) are added to the lower n bits for each of the first pixel element data (for example, R, G, and B data) to m + n bits. Bit expansion may be performed to generate the pixel data signal 12 in the first pixel format.

  The color conversion unit 20 generates pixel data generated by the first format conversion unit 10 according to a given conversion formula from a first color space (for example, RGB space) to a second color space (for example, YUV space). A process of converting the signal 12 (for example, a signal including R, G, and B data) into a pixel data signal 22 including a plurality of second pixel element data (for example, Y, U, and V data) is performed. .

  The first setting information 31, the second setting information 32, and the third setting information 33 may be stored in one register in the register unit 30, or may be stored separately in a plurality of registers. Also good.

  Hereinafter, a specific configuration example of the data processing circuit of the first embodiment shown in FIG. 1 will be described.

  FIG. 2 is a diagram illustrating an example of a specific configuration of the data processing circuit according to the first embodiment.

  The general-purpose bus 200 (an example of the first bus 2 described in FIG. 1) is connected to the data processing circuit 100A, the CPU 210, the DMA controller 220, the memory 230 such as ROM and RAM, and the like of the first embodiment. The CPU 210 or the DMA controller 220 transfers the pixel data stored in the memory 230 to the data processing circuit 100A via the general-purpose bus 200. In the present embodiment, the pixel data stored in the memory 230 represents color information defined in the RGB space (an example of the first color space described with reference to FIG. 1) as three pieces of data R, G, and B. Pixel data (hereinafter referred to as “RGB data”).

  The data processing circuit 100A expresses RGB data stored in the memory 230 as color information defined in the YUV space (an example of the second color space described with reference to FIG. 1) by three data of Y, U, and V. Conversion to pixel data (hereinafter referred to as “YUV data”) is performed and transferred to the image processing circuit 310 via the video bus 300 (an example of the second bus 3 described in FIG. 1). That is, the data processing circuit 100A simultaneously performs a bus protocol conversion process from the general-purpose bus 200 to the video bus 300 and a conversion process from RGB data to YUV data.

  The RGB data transferred via the general-purpose bus 200 is an example of the first pixel data signal 2a described in FIG. 1, and the YUV data transferred via the video bus 300 is the second described in FIG. This is an example of the pixel data signal 3a. The R, G, and B data included in the RGB data is an example of the first pixel element data described in FIG. 1, and the Y, U, and V data included in the YUV data is illustrated in FIG. 3 is an example of the second pixel element data.

  In the present embodiment, the CPU 210, the DMA controller 220, the memory 230, the data processing circuit 100A, and the image processing circuit 310 operate in synchronization with a common clock signal (CLK) (not shown).

  The data processing circuit 100A includes an RGB format conversion circuit 110 (an example of the first format conversion unit 10 described in FIG. 1), a color conversion circuit 120 (an example of the color conversion unit 20 described in FIG. 1), and a register block 130 ( 1), bus interface (I / F) circuits 140a and 140b, a FIFO memory (First In First Out Memory) 150, a FIFO memory 160, and a timing generation circuit 170. .

  The bus interface circuit 140a performs processing for a write request and a read request to various registers (format conversion setting register 131, color conversion setting register 132, etc.) included in the register block 130 by the CPU 210.

  More specifically, the CPU 210 functions as a bus master, and sends 32-bit address data 201a (HAD1 [31: 0]) and 32-bit address data to the bus interface circuit 140a functioning as a bus slave via the general-purpose bus 200. Write data 202a (HWD1 [31: 0]), 1-bit select signal 203a (HSEL1), 1-bit write signal 204a (HWRITE1), 1-bit ready input signal 205a (HRDYIN1), and the like are transferred.

  The bus interface circuit 140a receives the address data 201a, the write data 202a, the select signal 203a, the write signal 204a, the ready input signal 205a, etc., and the select signal 203a, the write signal 204a, and the ready input signal 205a are all active (high level). If there is, processing for writing the write data 202a to the register assigned to the address specified by the address data 201a is performed.

  In the present embodiment, all the control signals are active if they are at a high level, and inactive if they are at a low level, but the present invention is not limited to this.

  The bus interface circuit 140a is assigned to the address specified by the address data 201a if the select signal 203a and the ready input signal 205a are active (high level) and the write signal 204a is inactive (low level). Data is read from the registered register, and read data 207a (HRD1 [31: 0]) is output to the general-purpose bus 200.

  The bus interface circuit 140b performs processing for the RGB data transfer request by the CPU 210 or the DMA controller 220. In this embodiment, RGB data for one pixel transferred via the general-purpose bus 200 is 15-bit RGB data in RGB555 format (R, G, and B are all 5 bits) or RGB565 format (R, The G and B data are assumed to be any of 16-bit RGB data of 5 bits, 6 bits, and 5 bits, respectively, but the present invention is not limited to this.

  More specifically, the CPU 210 and the DMA controller 220 function as a bus master, and send 32-bit address data 201b (HAD2 [31: 0]) to the bus interface circuit 140b functioning as a bus slave via the general-purpose bus 200. 32 bit write data 202b (HWD2 [31: 0]), 1 bit select signal 203b (HSEL2), 1 bit write signal 204b (HWRITE2), 1 bit ready input signal 205b (HRDYIN2), etc. .

  Here, the write data 202b includes RGB data for two pixels. Specifically, the lower 16 bits (HWD2 [15: 0]) of the write data 202b include the RGB data of the first pixel, and the upper 16 bits (HWD2 [31:16]) include the RGB of the second pixel. Contains data. The bus interface circuit 140b receives the address data 201b, the write data 202b, the select signal 203b, the write signal 204b, the ready input signal 205b, etc., and the select signal 203b, the write signal 204b, and the ready input signal 205b are all active (high level). ), If the address specified by the address data 201b is the address of the FIFO memory 150 (hereinafter referred to as “00000000H”), the process of writing the RGB data for two pixels included in the write data 202b into the FIFO memory 150 I do.

  Further, the bus interface circuit 140b monitors the FIFO memory 150. When the bus interface circuit 140b detects that the FIFO memory 150 is full, the ready output signal 206b (HRDYOUT2) is made inactive (low level) until the FIFO memory 150 becomes empty. To do. While the ready output signal 206b is inactive (low level), a transfer request for the next two pixels of RGB data (write data 202b) from the CPU 210 or the DMA controller 220 is awaited.

  FIGS. 3A to 3D are diagrams showing an example of the format of RGB data for one pixel transferred via the general-purpose bus 200. FIG. As described above, in this embodiment, the transferred RGB data is in either the RGB555 format or the RGB565 format, but the arrangement order of R, G, and B is variable.

  The format shown in FIG. 3A is the RGB565 format, and R, G, and B are arranged in bits 15 to 11, bits 10 to 5, and bits 4 to 0, respectively. That is, data is arranged in the order of R, G, and B, starting with bit 15.

  The format shown in FIG. 3B is the RGB565 format, and B, G, and R are arranged in bits 15 to 11, bits 10 to 5, and bits 4 to 0, respectively. That is, data is arranged in the order of B, G, and R, starting with bit 15.

  The format shown in FIG. 3C is the RGB555 format, and R, G, and B are arranged in bits 14 to 10, bits 9 to 5, and bits 4 to 0, respectively. That is, it can be considered that data is arranged in the order of R, G, and B with bit 15 as the first bit, and there is no valid data in the first bit (bit 15).

  Also, the format shown in FIG. 3D is the RGB555 format, and bits 15 to 8 and bits 7 to 0 are data of bits 7 to 0 and bits 15 to 8 of the format of FIG. 3C, respectively. Is arranged. That is, while the format of FIG. 3C is a little endian format, the format of FIG. 3D is a big endian format. Therefore, in the format of FIG. 3D, B, G, and R are arranged in bits 6 to 2, bits 1 to 0 and 15 to 13, and bits 12 to 8, respectively. That is, it can be considered that data is arranged in the order of B, G, and R with bit 7 as the first bit, and that there is no valid data in the first bit (bit 7).

  Returning to FIG. 2, the RGB format conversion circuit 110 receives the RGB data 151 (RGBX2 [31: 0]) for two pixels stored at the head of the FIFO memory 150 and receives the lower 16-bit RGB data (first pixel). RGB data), upper 16-bit RGB data (RGB data of the second pixel), 10-bit R data 111a (R [9: 0]), G data 111b (G [9: 0]), B data A process of converting the pixel format to 111c (B [9: 0]) (an example of the pixel data signal 12 described in FIG. 1) is performed. As will be described later, the format conversion setting register 131 is preset with information for specifying the bit positions of R, G, and B data in the input RGB data (16 bits) for one pixel. The RGB format conversion circuit 110 performs pixel format conversion processing based on the setting information.

  The color conversion circuit 120 converts the 10-bit R data 111a, G data 111b, and B data 111c generated by the RGB format conversion circuit 110 into 10-bit Y data 121a (Y [9: 0]), according to the following conversion formula: A process of converting to U data 121b (U [9: 0]) and V data 121c (V [9: 0]) is performed.

_{Here, K 00, K 01, K} 02, K 03, K 10, K 11, K 12, K 13, K 20, K 21, K 22, K 23, OFS 0, OFS 1, OFS 2, YMIN, The values of YMAX, UMIN, UMAX, VMIN, and VMAX may be predetermined constant values, but may be configured to be settable in the color conversion setting register 132. By doing this, it is possible to select YCbCr or YPbPr as YUV by changing the setting value of the color conversion setting register 132, and not only RGB to YUV conversion but also any two color spaces. You can also perform color conversion with.

  The Y data 121a, U data 121b, and V data 121c after the conversion processing by the color conversion circuit 120 are collected into 30 bits and stored in the FIFO memory 160.

  The timing generation circuit 170 transmits a vertical synchronization signal 301 (VS) to the image processing circuit 310 in synchronization with the clock signal at the beginning of each frame, and starts transmitting pixel data for one frame. Specifically, the timing generation circuit 170 activates the data enable signal 303 (DE) at a predetermined timing (high level), and stores the YUV data 304 (YUV [29: 0]) stored at the head of the FIFO memory 160. ) Are sequentially transmitted in synchronization with the clock signal until one frame is reached. Note that the timing generation circuit 170 may further transmit the horizontal synchronization signal 302 (HS) to the image processing circuit 310 at the head of each drawing target line.

  The image processing circuit 310 performs image processing on each YUV data 304 and keeps the busy signal 305 (BUSY) inactive (low level) until the image processing is completed. The timing generation circuit 170 controls the FIFO memory 160 not to output the next YUV data 304 by setting the output stop signal 171 to active (high level) while the busy signal 305 is active (high level).

  Further, the timing generation circuit 170 monitors the FIFO memory 160. When the timing generation circuit 170 detects that the FIFO memory 160 is full, the output stop signal 172 is made active (high level) until the FIFO memory 160 becomes empty, so that the FIFO memory 150 Controls not to output the next RGB data 151.

  The vertical synchronization signal 301, the data enable signal 303, the YUV data 304, and the busy signal 305 constitute the video bus 300. Further, the horizontal synchronization signal 302 may be included in the components of the video bus 300.

  FIG. 4 is a diagram illustrating an example of a specific configuration of the RGB format conversion circuit 110.

  In the present embodiment, the RGB format conversion circuit 110 includes a barrel shifter 112, selection circuits 114a, 114b, and 114c, bit extension circuits 116a, 116b, and 116c, and an RGB selection circuit 118.

  The RGB selection circuit 118 receives the 32-bit RGB data 151, selects either the lower 16 bits or the upper 16 bits, and outputs 16-bit RGB data 119 (RGB [15: 0]).

  As described above, the RGB data 151 includes RGB data for two pixels. That is, RGB data of the first pixel is included in the lower 16 bits, and RGB data of the second pixel is included in the upper 16 bits. Therefore, when the FIFO memory 150 outputs new RGB data 151, the RGB selection circuit 118 first selects the lower 16 bits (RGB data of the first pixel) as RGB data 119, and the RGB data for the first pixel is selected. After the pixel format conversion process is completed, the upper 16 bits (RGB data of the second pixel) are selected and set as RGB data 119.

  Then, the RGB format conversion circuit 110 performs the MSB designation information 131a, the R position designation information 131b, the G position designation information 131c, the B position designation information 131d, and RGB565 set in the format conversion setting register 131 for the RGB data 119. A pixel format conversion process is performed based on the selection information 131e. In this embodiment, 4 bits are assigned to the MSB designation information 131a, the R position designation information 131b, the G position designation information 131c, and the B position designation information 131d in the format conversion setting register 131, and the RGB565 selection information 131e 1 bit is assigned.

  The MSB designation information 131a is information indicating which bit of the RGB data 119 is designated as the MSB (Most Significant Bit) and the arrangement order of R, G, and B, and any one of “0000” to “1111” is set. Thus, bit 0 to bit 15 can be designated as the MSB, respectively.

  The R position designation information 131b, the G position designation information 131c, and the B position designation information 131d are information for designating the arrangement order of R, G, and B, and are any one of “1000”, “0100”, and “0010”. Can be designated as the first, second, and third, respectively. For example, if “1000”, “0100”, and “0010” are respectively set as the R position designation information 131b, the G position designation information 131c, and the B position designation information 131d, the order of R → G → B becomes “0010”. , “0100” and “1000” can be set, the order of B → G → R can be specified.

  The RGB565 selection information 131e is information for selecting whether the RGB data 119 is in the RGB555 format or the RGB565 format. If “0” is set, the RGB555 format is selected, and if “1” is set, the RGB565 is selected. A format can be selected.

  5A and 5B show the R, G, and B bit positions specified by the combination of the R position specifying information 131b, the G position specifying information 131c, the B position specifying information 131d, and the RGB565 selection information 131e. It is a figure for demonstrating.

  FIG. 5A shows a case where “1111” (bit 15 is the MSB) is set as the MSB designation information.

  Therefore, for example, if the R position designation information 131b = “1000”, the G position designation information 131c = “0100”, and the B position designation information 131d = “0010”, the bit 15 of the RGB data 119 is set as the MSB to R → G → Bits are assigned in the order of B. Here, if the RGB565 selection information 131e is “1”, the RGB data 119 is in the RGB565 format, and therefore R, G, and B are assigned to bits 15 to 11, bits 10 to 5, and bits 4 to 0, respectively. This corresponds to the case shown in FIG. On the other hand, if the RGB565 selection information 131e is “0”, the RGB data 119 is in the RGB555 format, and therefore there is no valid data in the MSB (bit 15) designated by the MSB designation information 131a. Accordingly, R, G, and B are assigned to bits 14 to 10, bits 9 to 5, and bits 4 to 0 of the RGB data 119, respectively.

  For example, if the R position designation information 131b = “0010”, the G position designation information 131c = “0100”, and the B position designation information 131d = “1000”, the bit 15 of the RGB data 119 is set to the MSB and B → G → Bits are assigned in the order of R. Here, if the RGB565 selection information 131e is “1”, the RGB data 119 is in the RGB565 format, so B, G, and R are assigned to bits 15 to 11, bits 10 to 5, and bits 4 to 0, respectively. This corresponds to the case of FIG. 3B described above. On the other hand, if the RGB565 selection information 131e is “0”, the RGB data 119 is in the RGB555 format, and therefore there is no valid data in the MSB (bit 15) designated by the MSB designation information 131a. Therefore, B, G, and R are assigned to bits 14 to 10, bit 9 to 5, and bit 4 to 0 of the RGB data 119, respectively. This corresponds to the case of FIG. 3C described above.

  On the other hand, FIG. 5B shows a case where “0111” (bit 7 is MSB) is set as the MSB designation information.

  Therefore, for example, if the R position designation information 131b = “1000”, the G position designation information 131c = “0100”, and the B position designation information 131d = “0010”, the bit 7 of the RGB data 119 is set as the MSB to R → G → Bits are assigned in the order of B. Here, if the RGB565 selection information 131e is “1”, the RGB data 119 is in the RGB565 format, so that R, G, and B are set in bits 7 to 3, bits 2 to 0 and 15 to 13, and bits 12 to 8, respectively. Assigned. On the other hand, if the RGB565 selection information 131e is “0”, the RGB data 119 is in the RGB555 format, and therefore there is no valid data in the MSB (bit 7) designated by the MSB designation information 131a. Therefore, R, G, and B are assigned to bits 6 to 2, bits 1 to 0 and 15 to 13, and bits 12 to 8 of the RGB data 119, respectively. In this way, if the set value of the MSB designation information 131a is other than “1111”, the arrangement order of R, G, and B is specified assuming that bit 15 of RGB data 119 is followed by bit 15.

  For example, if R position designation information 131b = “0010”, G position designation information 131c = “0100”, and B position designation information 131d = “1000”, bit 7 of RGB data 119 is set to MSB and B → G → Bits are assigned in the order of R. Here, if the RGB565 selection information 131e is “1”, the RGB data 119 is in the RGB565 format, and therefore B, G, and R are set in bits 7 to 3, bits 2 to 0 and 15 to 13, and bits 12 to 8, respectively. Assigned. On the other hand, if the RGB565 selection information 131e is “0”, the RGB data 119 is in the RGB555 format, and therefore there is no valid data in the MSB (bit 7) designated by the MSB designation information 131a. Therefore, B, G, and R are assigned to bits 6 to 2, bits 1 to 0 and 15 to 13, and bits 12 to 8 of the RGB data 119, respectively. This corresponds to the case of FIG.

  As described above, R data, G data in RGB data 119 (that is, lower 16-bit data or upper 16-bit data of R data 151) is obtained by R position specifying information 131b, G position specifying information 131c, and B position specifying information 131d. The arrangement order of the B data can be specified. That is, the R position designation information 131b, the G position designation information 131c, and the B position designation information 131d function as the first setting information 31 described with reference to FIG.

  Further, the MSB designation information 131a can specify a reference bit that is a reference for the arrangement order of R, G, and B in the RGB data 119 (that is, lower 16-bit data or upper 16-bit data of the R data 151). That is, the MSB designation information 131a functions as the second setting information 32 described with reference to FIG.

  Further, the RGB565 selection information 131e can specify whether the reference bit specified by the MSB designation information 131a is a part of any of R data, G data, or B data. That is, the RGB565 selection information 131e functions as the third setting information 32 described with reference to FIG.

  Returning to FIG. 4, the barrel shifter 112 cyclically shifts the RGB data 119 as necessary so that the bit of the RGB data 119 designated by the MSB designation information 131a becomes the most significant bit (MSB), and the RGB data 113 ( 16 bits) is generated. For example, when “1111” is set as the MSB designation information 131a (in the case of FIG. 5A), since the bit 15 (MSB) of the RGB data 119 is designated as the MSB, the barrel shifter 112 is cyclic. Do not shift. Therefore, the RGB data 113 matches the RGB data 119. On the other hand, for example, when “0111” is set as the MSB designation information 131a (in the case of FIG. 5B), since the bit 7 of the RGB data 119 is designated as the MSB, the barrel shifter 112 uses the RGB data. The left cyclic shift is performed by 8 bits so that bit 7 of 119 becomes the MSB of the RGB data 113. Therefore, bits 15 to 8 and bits 7 to 0 of the RGB data 113 coincide with bits 7 to 0 and bits 15 to 8 of the RGB data 119, respectively.

  The RGB data 113 is input to the selection circuits 114a, 114b, and 114c. The selection circuits 114a, 114b, and 114c follow the same logic as in FIG. 5A described above according to the combination of the B position designation information 131d and the RGB565 selection information 131e according to the R position designation information 131b and the G position designation information 131c. The bits of the RGB data 113 are extracted from the determined bit positions, and 5-bit R data 115a, 5-bit or 6-bit G data 115b, and 5-bit B data 115c are generated.

  If the R position designation information 131b = “1000”, the selection circuit 114a selects bits 15 to 11 (5 bits) of the RGB data 113 when the RGB565 selection information 131e = “1”, and the RGB565 selection information 131e = When “0”, bits 14 to 10 (5 bits) of the RGB data 113 are selected and set as R data 115a. If the R position designation information 131b = “0100”, the selection circuit 114a has the G position designation information 131c = “0010”, the B position designation information 131d = “1000”, and the RGB565 selection information 131e = “1”. Selects bits 10 to 6 (5 bits) of the RGB data 113, and otherwise selects bits 9 to 5 (5 bits) of the RGB data 113 as R data 115a. Further, the selection circuit 114a always selects the bits 4 to 0 (5 bits) of the RGB data 113 as the R data 115a when the R position designation information 131b = “0010”.

  If the G position designation information 131c = “1000”, the selection circuit 114b selects bits 15 to 10 (6 bits) of the RGB data 113 when the RGB565 selection information 131e = “1”, and the RGB565 selection information 131e = When it is “0”, bits 14 to 10 (5 bits) of the RGB data 113 are selected and set as G data 115b. If the G position designation information 131c = “0100”, the selection circuit 114b selects bits 10 to 5 (6 bits) of the RGB data 113 when the RGB565 selection information 131e = “1”, and the RGB565 selection information. When 131e = "0", bits 9 to 5 (5 bits) of the RGB data 113 are selected as G data 115b. If the G position designation information 131c = “0010”, the selection circuit 114b selects bits 5 to 0 (6 bits) of the RGB data 113 when the RGB565 selection information 131e = “1”, and the RGB565 selection information. When 131e = "0", bits 4 to 0 (5 bits) of the RGB data 113 are selected as G data 115b.

  If the B position designation information 131d = “1000”, the selection circuit 114c selects bits 15 to 11 (5 bits) of the RGB data 113 when the RGB565 selection information 131e = “1”, and the RGB565 selection information 131e = When it is “0”, bits 14 to 10 (5 bits) of the RGB data 113 are selected and set as B data 115c. If the B position designation information 131d = “0100”, the selection circuit 114c has the R position designation information 131b = “1000”, the G position designation information 131c = “0010”, and the RGB565 selection information 131e = “1”. Selects bits 10 to 6 (5 bits) of the RGB data 113, and otherwise selects bits 9 to 5 (5 bits) of the RGB data 113 as B data 115c. The selection circuit 114c always selects bits 4 to 0 (5 bits) of the RGB data 113 as the B data 115c if the B position designation information 131d = “0010”.

  The R data 115a, the G data 115b, and the B data 115c are input to the bit expansion circuits 116a, 116b, and 116c, respectively.

  The bit extension circuit 116a performs a process of bit-extending the 5-bit R data 115a to generate 10-bit R data 111a. Specifically, as shown in FIG. 6A, the bit extension circuit 116a copies bits 4-0 of the R data 115a to bits 9-5 of the R data 111a and bits 4-0 of the R data 111a. A process of copying bits 4 to 0 of the R data 115a is performed.

  The bit extension circuit 116b performs a process of generating the 10-bit G data 111b by bit-extending the 5-bit or 6-bit G data 115b according to the RGB565 selection information 131e. Specifically, when the RGB565 selection information 131e = "0", the bit expansion circuit 116b, as shown in FIG. 6A, the bits 9 to 5 of the G data 111b and the bits 4 to 0 of the G data 115b. And copying the bits 4-0 of the G data 115b to the bits 4-0 of the G data 111b. On the other hand, when the RGB565 selection information 131e = "1", the bit expansion circuit 116b copies bits 5-0 of the G data 115b to bits 9-4 of the G data 111b as shown in FIG. 6B. At the same time, a process of copying bits 5 to 2 of G data 115b to bits 3 to 0 of G data 111b is performed.

  Then, the R data 111a, the G data 111b, and the B data 111c are output to the image processing circuit 120 and subjected to image processing as described with reference to FIG.

  If the bit extension is performed as shown in FIGS. 6A and 6B, when the 5-bit R data 115a has the maximum value ("11111"), the 10-bit R data 111a also has the maximum value (" 1111111111 "). Further, when the 5-bit R data 115a has the minimum value (“00000”), the 10-bit R data 111a also has the minimum value (“0000000”). Accordingly, since the 10-bit range (“0000000000000” to “1111111111”) can be used to the maximum extent, errors generated in the R data 111a due to bit expansion can be minimized.

  For the same reason, errors that occur in the G data 111b and B data 111c due to bit expansion can be minimized.

  FIG. 7 is a timing chart showing an example of operation timing of the data processing circuit 100A.

From time t _{1 to} t ₂ , the timing generation circuit 170 transmits the vertical synchronization signal 301 (VS) to the image processing circuit 310 in synchronization with the clock signal (CLK).

At time _{t 3} after a predetermined time, the select signal 203b (HSEL2) is such CPU 210, a write signal 204b (HWRITE2), along with shifts ready input signal 205b with (HRDYIN2) from a low level to a high level, via the general purpose bus 200 The address data 201b (HAD2 [31: 0]) indicating the address (00000000H) of the FIFO memory 150 is transmitted to the data processing circuit 100A.

The time _{t 4} later, etc. CPU 210, together with reversing the polarity of the ready input signal 205b (HRDYIN2) every clock cycle, the write data 202b (HWD2 [31 comprising RGB data of two pixels every two clock cycles : 0]) is transmitted to the data processing circuit 100A.

Bus interface circuit 140b is the select signal 203b (HSEL2) and when ready input signal 205b (HRDYIN2) is at a high level both (time _t 3 ~t _4, time _t 5 ~t _6, time _t 7 ~t _8, time t _{9 to} t ₁₀ ,...) To the address specified by the address data 201b (HAD2 [31: 0]) (all are addresses 00000000H of the FIFO memory 150) and the next clock cycle (time t _{4 to} t _5, time _t 6 ~t _7, the time _t 8 ~t _9, time _t 10 _~t 11, the write data 202b of ···) (HWD2 [31: 0 ]) is written to.

At time _t 4 ~t _6, the write data 202b (HWD2 [31: 0] ) low-order 16 bits of the (HWD2 [15: 0]) and the upper 16 bits (HWD2 [31:16]) to each first pixel of RGB data (RGB0) and includes a second pixel RGB data (RGB1), at time _{t 5,} the top first pixel in the buffer of the RGB data (RGB0) and the second pixel of the RGB data of the FIFO memory 150 (RGB1) is written. As a result, at the times t _{5 to} t ₆ , the lower 16 bits and the upper 16 bits of the RGB data 151 (RGBX2 [31: 0]) become RGB0 and RGB1, respectively.

At times t _{5 to} t ₇ , the RGB format conversion circuit 110 causes the R, G, B data (R 0, G 0, B 0) and (R 1, G 1, B 1) of the first and second pixels from RGB 0 and RGB 1, respectively. ) Are generated in order.

More specifically, first, the RGB selection circuit 118 selects the lower 16-bit data of the RGB data 151 (RGBX2 [31: 0]) at the times t _{5 to} t ₆ to select the RGB data 119 (RGB [15: 0] ) it becomes RGB0, RGB data 151 at time _{t 6 ~t 7 (RGBX2 [31} : 0]) upper 16-bit data is selected of RGB data 119 (RGB [15: 0] ) is RGB1.

Then, the RGB data 119 (RGB [15: 0]) is cyclically shifted as necessary by the barrel shifter 112, and the R, G, and B data are taken out by the selection circuits 114a, 114b, and 114c, respectively, and are respectively bit extension circuits. 116a, 116b and 116c are bit-extended to 10 bits. As a result, R data 111a (R [9: 0] ), G data 111b (G [9: 0] ), B data 111c (B [9: 0] ) , the time _t 5 in ~t ₆ R0, G0 , becomes B0, at time _t 6 ~t ₇ R1, G1, becomes B1.

From time t _{6 to} t ₈ , the color conversion circuit 120 converts the first pixel (R0, G0, B0) and the second pixel (R1, G1, B1) into Y, U, and V in order. As a result, Y data 121a (Y [9: 0] ), U data 121b (U [9: 0] ), V data 121c (V [9: 0] ) is the first pixel at time _t 6 ~t ₇ consisting of Y, U, becomes to the data of V (Y0, U0, V0) , the time _t 7 ~t ₈ in the second pixel Y, U, each data V (Y1, U1, V1) .

At time t ₇ , bits 29 to 20 (YUV [29:20]), bits 19 to 10 (YUV [19:10]), bits 9 to 0 (YUV [9: 0]) of the first buffer of the FIFO memory 160. ], Y0, U0, and V0 are respectively written and transmitted to the image processing circuit 310 together with the data enable signal 303 (DE) in synchronization with the clock signal (CLK).

At time _{t 8,} the bit of the first buffer of the FIFO memory 160 29~20 (YUV [29:20]) , bits 19~10 (YUV [19:10]), the bit 9~0 (YUV [9: 0 ], Y1, U1, and V1 are respectively written and transmitted to the image processing circuit 310 together with the data enable signal 303 (DE) in synchronization with the clock signal (CLK).

  RGB data for the third and fourth pixels (RGB2, RGB3), RGB data for the fifth and sixth pixels (RGB4, RGB5), RGB data for the seventh and eighth pixels (RGB6, RGB7), ... As for..., Similarly to the RGB data (RGB0, RGB1) of the first pixel and the second pixel, conversion processing to YUV data is performed and transmitted to the image processing circuit 310.

If necessary, the timing generation circuit 170 may transmit the horizontal synchronization signal 302 (HS) to the image processing circuit 310 in synchronization with the clock signal (CLK) at time t _{5 to} t ₆ . Good.

  As described above, according to the data processing circuit 100A of the first embodiment, pixel format conversion and color conversion are performed on RGB data in the RGB555 format or RGB565 format transferred via the general-purpose bus 200, and the video Since it is converted into YUV data transferred via the bus 300, it is not necessary for the CPU 210 to perform pixel format conversion or color conversion in advance. Therefore, the load on the CPU 210 and memory resources can be reduced.

  Further, according to the data processing circuit 100A of the first embodiment, R, G, and B data in RGB data in the RGB555 format or the RGB565 format are determined by the R position specifying information 131b, the G position specifying information 131c, and the B position specifying information 131d. Can be specified. Therefore, even if the arrangement order of R, G, and B data in the RGB data transferred via the general-purpose bus 200 is variable, the R position designation information 131b, the G position designation information 131c, and B in advance according to the arrangement order. By changing the position designation information 131d, it is possible to appropriately extract R, G, and B data from RGB data and convert the pixel format to 10-bit R data 111a, G data 111b, and B data 111c.

  Further, according to the data processing circuit 100A of the first embodiment, the MSB designation information 131a is used to set a reference bit that is a reference for the arrangement order of R, G, and B data in RGB data transferred via the general-purpose bus 200. Can be identified. Therefore, even if the position of the reference bit of the RGB data transferred via the general-purpose bus 200 is variable, by appropriately changing the MSB designation information 131a in accordance with the position of the reference bit, R , G, and B data can be extracted and a pixel format conversion process can be performed.

  Further, according to the data processing circuit 100A of the first embodiment, the RGB565 selection information 131e can specify whether the RGB data transferred via the general-purpose bus 200 is in the RGB555 format or the RGB565 format. In the case of the RGB555 format, it can be determined that the reference bit serving as the reference for the arrangement order of the R, G, and B data is invalid, and in the case of the RGB565 format, the reference bit is valid. Therefore, by changing the RGB565 selection information 131e according to the pixel format of the RGB data transferred via the general-purpose bus 200, each R, G, and B data is appropriately extracted from the RGB data, and the pixel format conversion process is performed. It can be carried out.

Therefore, according to the data processing circuit 100A of the first embodiment, highly flexible pixel format conversion processing and color conversion processing can be realized.
(2) Second Embodiment FIG. 8 is a functional block diagram of a data processing circuit according to a second embodiment. 8, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  Similar to the data processing circuit 1A of the first embodiment shown in FIG. 1, the data processing circuit 1B of the second embodiment transmits a first pixel data signal transmitted via the first bus 2 according to the first protocol. 2a is received, converted into a second pixel data signal 3a transmitted via the second bus 3 according to the second protocol, and transmitted.

  In the second embodiment, the first pixel data signal 2a has any one of a plurality of types of pixel formats (for example, YUV444, YUV422, YUV411, RGB555, RGB565, etc.).

  In the data processing circuit 1B of the second embodiment, a second format conversion unit 40 and a pixel data signal selection unit 50 are added to the data processing circuit 1A of the first embodiment. The register unit 30 further stores fourth setting information 34 and fifth setting information 35 in addition to the first setting information 31, the second setting information 32, and the third setting information 33. .

  The fourth setting information 34 is information for specifying the pixel format of the first pixel data signal 2a.

  The fifth setting information 35 is information for specifying the arrangement of a plurality of first pixel element data in the first pixel data signal 2a having a predetermined pixel format. For example, when the first pixel data signal 2a is in the YUV422 format (the ratio of the number of data of Y, U, and V is 2: 1: 1), the fifth setting information 35 is Y0 (Y of the first pixel). , Y1 (Y for the second pixel), U0 (U common to the first pixel and the second pixel), and V0 (V common to the first pixel and the second pixel) are specified. Information.

  Based on the fifth setting information 35, the second format conversion unit 40 generates a plurality of first pixel element data (for example, Y0) from the first pixel data signal 2a in a predetermined pixel format (for example, YUV422 format). , Y1, U0, V0), and generates a pixel data signal 42 of the second pixel format including the plurality of first pixel element data (for example, Y0, Y1, U0, V0 data). Perform the process.

  The second format conversion unit 40 also includes a plurality of first pixel element data (for example, Y0, Y1, U0, V0) extracted from the first pixel data signal 2a (for example, a pixel data signal in the YUV422 format). When the number of bits of each data) is j, the upper k bits (k ≦ j) are the lower k bits for each of the first pixel element data (for example, each data of Y0, Y1, U0, V0). And the bit extension to j + k bits to generate the pixel data signal 42 of the second pixel format.

  Based on the fourth setting information 34, the pixel data selection unit 50 is either the pixel data signal 12 generated by the first format conversion unit 10 or the pixel data signal 42 generated by the second format conversion unit 40. Select. For example, based on the fourth setting information 34, the pixel data selection unit 50 selects the pixel data signal 42 when the first pixel data signal 2a is in a YUV format (YUV444, YUV422, YUV411, etc.). When the first pixel data signal 2a has an RGB format (RGB555, RGB565, etc.), the pixel data signal 12 may be selected.

  The color conversion unit 20 has a pixel data signal 52 (pixel data signal 12 or pixel data signal 42) selected by the pixel data selection unit 50 in accordance with a given conversion formula from the first color space to the second color space. Is converted into a pixel data signal 22 including a plurality of second pixel element data (for example, Y, U, and V data).

  The first setting information 31, the second setting information 32, the third setting information 33, the fourth setting information 34, and the fifth setting information 35 are stored in one register in the register unit 30. Alternatively, it may be stored in a plurality of registers.

  Hereinafter, a specific configuration example of the data processing circuit according to the second embodiment illustrated in FIG. 8 will be described.

  FIG. 9 is a diagram illustrating an example of a specific configuration of the data processing circuit according to the second embodiment. 9, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  In the second embodiment, the pixel data stored in the memory 230 is either RGB data or YUV422 format pixel data (hereinafter referred to as “YUV422 data”).

  When the RGB data transferred from the memory 230 is transferred via the general-purpose bus 200, the data processing circuit 100B according to the second embodiment converts the transferred RGB data into YUV data and transmits the image via the video bus 300. A process of transferring to the processing circuit 310 is performed. On the other hand, when the YUV422 data transferred from the memory 230 via the general-purpose bus 200 is transferred, the data processing circuit 100B converts the transferred YUV422 data into a pixel format, and further performs color conversion (for example, YCbCr YUV data subjected to color conversion from YPbPr to YPbPr is transferred to the image processing circuit 310 via the video bus 300.

  That is, the data processing circuit 100B simultaneously performs conversion processing from RGB data or YUV422 data to YUV data as well as bus protocol conversion processing from the general-purpose bus 200 to the video bus 300.

  The RGB data or YUV422 data transferred via the general-purpose bus 200 is an example of the first pixel data signal 2a described with reference to FIGS. 1 and 8, and the YUV data transferred via the video bus 300 is illustrated in FIG. 8 is an example of the second pixel data signal 3a described in FIG.

  Also in the second embodiment, when RGB data is transferred via the general-purpose bus 200, the RGB data for two pixels is simultaneously transferred by the write data 202b as in the first embodiment, and the RGB data for one pixel is transferred. The format is as shown in FIGS. 3 (A) to 3 (D).

  In the second embodiment, when YUV422 data is transferred via the general-purpose bus 200, YUV422 data for two pixels is transferred simultaneously by the write data 202b, and the YUV422 data for two pixels is shown in FIG. 10 (D).

  In the format shown in FIG. 10A, Y data (Y0) for the first pixel and Y data (Y1) for the second pixel are arranged in bits 15 to 8 and bits 31 to 24, respectively. And U data (U0) and V data (V0) are arranged in bits 23 to 16, respectively.

  In the format shown in FIG. 10B, Y data (Y0) for the first pixel and Y data (Y1) for the second pixel are arranged in bits 15 to 8 and bits 31 to 24, respectively. U data (U0) and V data (V0) are arranged in .about.16 and bits 7 to 0, respectively.

  In the format shown in FIG. 10C, Y data (Y0) for the first pixel and Y data (Y1) for the second pixel are arranged in bits 7 to 0 and bits 23 to 16, respectively. U data (U0) and V data (V0) are arranged in .about.8 and bits 31 to 24, respectively.

  In the format shown in FIG. 10D, Y data (Y0) for the first pixel and Y data (Y1) for the second pixel are arranged in bits 7 to 0 and bits 23 to 16, respectively. U data (U0) and V data (V0) are arranged in .about.24 and bits 15 to 8, respectively.

  In FIGS. 10A to 10D, U data (U0) and V data (V0) are data common to the first pixel and the second pixel.

  In the following, the formats shown in FIGS. 10A to 10D are referred to as “UYVY format”, “VYYY format”, and “YUYV format”, respectively, due to the order of data from LSB (Least Significant Bit). , “YVYU format”.

  Returning to FIG. 9, the data processing circuit 100B of the second embodiment is different from the data processing circuit 100A of the first embodiment in the YUV format conversion circuit 180 (an example of the second format conversion unit 40 described in FIG. 8). And a selection circuit 190 (an example of the pixel data signal selection unit 50 described with reference to FIG. 8).

  The YUV format conversion circuit 180 receives the YUV422 data 152 (YUV422 [31: 0]) stored at the head of the FIFO memory 150, receives 10-bit V data 181a (V [9: 0]), and Y data 181b (Y [9: 0]), U data 181c (U [9: 0]) (an example of the pixel data signal 42 described in FIG. 8) is subjected to pixel format conversion processing. As will be described later, in the format conversion setting register 131, information for specifying which format the YUV422 data 152 is shown in FIGS. 10A to 10D is set in advance. The YUV format conversion circuit 180 performs pixel format conversion processing based on the setting information.

  The selection circuit 190 selects one of the set of R data 111a, G data 111b, and B data 111c or the set of V data 181a, Y data 181b, and U data 181c, and 10-bit R or V data. 191a (RV [9: 0]), G or Y data (hereinafter referred to as “GY data”) 191b (GY [9: 0]), B or U data (hereinafter referred to as “RV data”) , “BU data”) 191c (BU [9: 0]). As will be described later, in the format conversion setting register 131, information for specifying whether the input pixel data is RGB data or YUV422 data is set in advance, and the selection circuit 190 performs selection processing based on the setting information. I do.

  The color conversion circuit 120 converts the 10-bit RV data 191a, GY data 191b, and BU data 191c output from the selection circuit 190 into 10-bit Y data 121a and U data in accordance with the conversion formula described in the first embodiment. 121b and a process of converting to V data 121c are performed.

  Since other configurations in the second embodiment are the same as those in the first embodiment, the description thereof is omitted.

  FIG. 11 is a diagram for explaining an example of a specific configuration of the YUV format conversion circuit 180.

  In the second embodiment, the format conversion setting register 131 includes the MSB designation information 131a, the R position designation information 131b, the G position designation information 131c, the B position designation information 131d, and the RGB565 selection information 131e described in the first embodiment. Thus, YUV422 position selection information 131f and pixel format selection information 131g are set.

  The YUV422 position selection information 131f is information for selecting whether each pixel data included in the YUV422 data 152 is in the UYVY format, VYUY format, YUYV format, or YVYU format. For example, by setting “00”, “01”, “10”, and “11” as the YUV422 position selection information 131f, the UYVY format, VYUYY format, YUYV format, and YVYU format are selected, respectively.

  The pixel format selection information 131g is information for selecting whether the pixel data transferred via the general-purpose bus 200 is RGB data or YUV422 data. For example, by setting “0” or “1” as the pixel format selection information 131g, RGB data or YUV422 data is selected, respectively.

  The YUV format conversion circuit 180 includes a Y0 selection timing generation circuit 182, selection circuits 184a, 184b, 184c, and bit expansion circuits 186a, 186b, 186c. The YUV format conversion circuit 180 performs processing based on the YUV422 position selection information 131f.

  The Y0 selection timing generation circuit 182 instructs the selection circuit 184b to select Y data (Y0) of the first pixel or Y data (Y1) of the second pixel in the YUV422 data 152. Perform processing to generate (Y0SEL).

  The YUV422 data 152 is input to the selection circuits 184a, 184b, 184c.

  The selection circuits 184a and 184c perform processing of extracting 8-bit V data 185a and U data 185c, respectively, from the bit position of the YUV422 data 152 determined according to the YUV422 position selection information 131f.

  Further, the selection circuit 184b performs a process of extracting 8-bit Y data 185b from the bit position of the YUV422 data 152 determined according to the YUV422 position selection information 131f and the Y0 selection signal 183.

  FIG. 12 shows a truth table of selection logic of the selection circuits 184a, 184b, and 184c. As described above, the YUV422 data 152 may be the UYVY format if the YUV422 position selection information 131f is “00”, the VYUY format if “01”, the YUYV format if “10”, or “11”. YVYU format.

  Therefore, as shown in FIG. 12, the selection circuit 184a has the YUV422 position selection information 131f = “00”, “01”, “10”, “11” for each case in which bits 23 to 16, bits 7 to 0, bits 31 to 24, and bits 15 to 8 are selected as V data 185a.

  If the YUV422 position selection information 131f = "00" or "01", the selection circuit 184b selects bits 15 to 8 of the YUV422 data 152 when the Y0 selection signal 183 = "1", and the Y0 selection signal 183 = When “0”, bits 31 to 24 of the YUV422 data 152 are selected and set as Y data 185b. If the YUV422 position selection information 131f = “10” or “11”, the selection circuit 184b selects bits 7 to 0 of the YUV422 data 152 when the Y0 selection signal 183 = “1”, and the Y0 selection signal When 183 = "0", bits 23 to 16 of the YUV422 data 152 are selected and set as Y data 185b.

  For each case of YUV422 position selection information 131f = “00”, “01”, “10”, “11”, the selection circuit 184c performs bits 7 to 0, bits 23 to 16, and bit 15 of the YUV422 data 152, respectively. .About.8, bits 31.about.24 are selected as U data 185c.

  Thus, the arrangement of the Y data, U data, and V data in the YUV422 data can be specified by the YUV422 position selection information 131f. That is, the YUV422 position selection information 131f functions as the fifth setting information 35 described with reference to FIG.

  Returning to FIG. 11, the V data 185a, Y data 185b, and U data 185c are input to the bit expansion circuits 186a, 186b, and 186c, respectively.

  The bit expansion circuits 186a, 186b, and 186c perform a process of expanding the 8-bit V data 185a, Y data 185b, and U data 185c to generate 10-bit V data 181a, Y data 181b, and U data 181c, respectively. .

  Specifically, as shown in FIG. 13, the bit extension circuit 186a copies the bits 7-0 of the V data 185a to the bits 9-2 of the V data 181a, and also sets the V data bits 1-0 of the V data 181a to V A process of copying bits 7 to 6 of the data 185a is performed.

  Similarly, bit extension circuit 186b copies bits 7-0 of Y data 185b to bits 9-2 of Y data 181b, and copies bits 7-6 of Y data 185b to bits 1-0 of Y data 181b. Perform the process.

  Similarly, the bit expansion circuit 186c copies bits 7-0 of the U data 185c to bits 9-2 of the U data 181c, and copies bits 7-6 of the U data 185c to bits 1-0 of the U data 181c. Perform the process.

  If the bit extension is performed as shown in FIG. 13, when the 8-bit V data 185a has the maximum value (“11111111”), the 10-bit V data 181a also has the maximum value (“1111111111”). In addition, when the 8-bit V data 185a has the minimum value (“00000000”), the 10-bit V data 181a also has the minimum value (“0000000”). Accordingly, since the 10-bit range (“0000000000000” to “1111111111”) can be used to the maximum extent, errors occurring in the V data 181a due to bit expansion can be minimized.

  For the same reason, errors occurring in the Y data 181b and the U data 181c due to bit expansion can be minimized.

  The selection circuit 190 selects a set of R data 111a, G data 111b, and B data 111c if the pixel format selection information 131g = "0", and selects Y data 181a if the pixel format selection information 131g = "1". A set of U data 181b and V data 181c is selected as RV data 191a, GY data 191b, and BU data 191c.

  In this manner, the pixel format (either RGB or YUV422) of the pixel data transferred via the general-purpose bus 200 can be specified by the pixel format selection information 131g. That is, the pixel format selection information 131g functions as the fourth setting information 34 described with reference to FIG.

  FIG. 14 is a timing chart showing an example of operation timing of the data processing circuit 100B. FIG. 14 shows an example of the operation timing of the data processing circuit 100B when YUV422 data is input via the general-purpose bus 200. The operation timing of the data processing circuit 100B when RGB data is input via the general-purpose bus 200 is the same as that in FIG.

From time t _{1 to} t ₂ , the timing generation circuit 170 transmits the vertical synchronization signal 301 (VS) to the image processing circuit 310 in synchronization with the clock signal (CLK).

At time _{t 3} after a predetermined time, the select signal 203b (HSEL2) is such CPU 210, a write signal 204b (HWRITE2), along with shifts ready input signal 205b with (HRDYIN2) from a low level to a high level, via the general purpose bus 200 The address data 201b (HAD2 [31: 0]) indicating the address (00000000H) of the FIFO memory 150 is transmitted to the data processing circuit 100B.

The time _{t 4} later, etc. CPU 210, together with reversing the polarity of the ready input signal 205b (HRDYIN2) every clock cycle, the write data 202b (HWD2 [31 including YUV422 data of two pixels every two clock cycles : 0]) is transmitted to the data processing circuit 100B. Here, it is assumed that the YUV422 data transmitted from the CPU 210 or the like is in the UYVY format.

Bus interface circuit 140b is the select signal 203b (HSEL2) and when ready input signal 205b (HRDYIN2) is at a high level both (time _t 3 ~t _4, time _t 5 ~t _6, time _t 7 ~t _8, time t _{9 to} t ₁₀ ,...) To the address specified by the address data 201b (HAD2 [31: 0]) (all are addresses 00000000H of the FIFO memory 150) and the next clock cycle (time t _{4 to} t _5, time _t 6 ~t _7, the time _t 8 ~t _9, time _t 10 _~t 11, the write data 202b of ···) (HWD2 [31: 0 ]) is written to.

At time _t 4 ~t _6, the write data 202b (HWD2 [31: 0] ) are included first pixel and the second pixel of YUV422 data (y1, v0, y0, u0 ) is, at a time _{t 5} The YUV422 data (y1, v0, y0, u0) of the first pixel and the second pixel are written in the first buffer of the FIFO memory 150. As a result, at times t _{5 to} t ₆ , bits 31 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0 of YUV422 data 152 (YUV422 [31: 0]) are respectively y1, v0, y0, u0.

At times t _{5 to} t ₇ , the YUV format conversion circuit 180 causes the V, Y, U data (v0 ′, y0 ′, u0 ′) and (v0 ′, y1 ′, u0) of the first pixel and the second pixel. ') Is generated in order.

More specifically, at times t _{5 to} t ₇ , bits 23 to 16 of YUV422 data 152 (YUV422 [31: 0]) are selected by selection circuit 184a and V data 185a becomes v0, and selection circuit 184c , Bits 7 to 0 of YUV422 data 152 (YUV422 [31: 0]) are selected, and U data 185c becomes u0.

The time _t 5 ~t ₆ In Y0 selection signal 183 (Y0SEL) becomes high level, the selection circuit 184b, YUV422 data 152 (YUV422 [31: 0] ) bit 15-8 is is selected and Y data 185b of It becomes y0. On the other hand, the time _t 6 ~t ₇ In Y0 selection signal 183 (Y0SEL) goes low, the selection circuit 184b, YUV422 data 152 (YU V422 [31: 0 ]) bits 31 to 24 are selected of Y data 185b Becomes y1.

The V data 185a, Y data 185b, and U data 185c are bit-extended to 10 bits by the bit expansion circuits 116a, 116b, and 116c, respectively, and the V data 181a (V [9: 0]) and Y data 181b (Y [ 9: 0]), U data 181c (U [9: 0] ) , respectively at time _{t 5 ~t 6 v0 ', y0} ', ' it becomes, respectively at time _{t 6 ~t 7 v0' u0,} y1 ', U0'.

Further, the selection circuit 190 selects V data 181a (V [9: 0]), Y data 181b (Y [9: 0]), U data 181c (U [9: 0]), and RV data 191a ( RV [9: 0]), GY data 191b (GY [9: 0] ), BU data 191c (BU [9: 0] ) , the time _t 5 ~t in ₆ respectively v0 ', y0', to u0 ' becomes, respectively at time _{t 6 ~t 7 v0 ', y1} ', it becomes u0 '.

From time t _{6 to} t ₈ , the color conversion circuit 120 converts the first pixel (v0 ′, y0 ′, u0 ′) and the second pixel (v0 ′, y1 ′, u0 ′) into Y, U, and V in order. Is done. As a result, Y data 121a (Y [9: 0] ), U data 121b (U [9: 0] ), V data 121c (V [9: 0] ) is the first pixel at time _t 6 ~t ₇ consisting of Y, U, becomes to the data of V (Y0, U0, V0) , the time _t 7 ~t ₈ in the second pixel Y, U, each data V (Y1, U1, V1) .

At time t ₇ , bits 29 to 20 (YUV [29:20]), bits 19 to 10 (YUV [19:10]), bits 9 to 0 (YUV [9: 0]) of the first buffer of the FIFO memory 160. ], Y0, U0, and V0 are respectively written and transmitted to the image processing circuit 310 together with the data enable signal 303 (DE) in synchronization with the clock signal (CLK).

At time _{t 8,} the bit of the first buffer of the FIFO memory 160 29~20 (YUV [29:20]) , bits 19~10 (YUV [19:10]), the bit 9~0 (YUV [9: 0 ], Y1, U1, and V1 are respectively written and transmitted to the image processing circuit 310 together with the data enable signal 303 (DE) in synchronization with the clock signal (CLK).

  YUV422 data (y3, v1, y2, u1) for the third and fourth pixels, YUV422 data (y5, v2, y4, u2) for the fifth and sixth pixels, YUV422 data for the seventh and eighth pixels .. (Y7, v3, y6, u3),... Are also converted into YUV data in the same manner as the YUV422 data (y1, v0, y0, u0) of the first pixel and the second pixel, respectively. It is transmitted to the processing circuit 310.

If necessary, the timing generation circuit 170 may transmit the horizontal synchronization signal 302 (HS) to the image processing circuit 310 in synchronization with the clock signal (CLK) at time t _{5 to} t ₆ . Good.

  As described above, according to the data processing circuit 100B of the second embodiment, pixel format conversion and color conversion are performed on RGB data and YUV data transferred via the general-purpose bus 200, and the video bus 300 is Therefore, the CPU 210 does not need to perform pixel format conversion or color conversion in advance. Therefore, the load on the CPU 210 and memory resources can be reduced.

  Further, according to the data processing circuit 100B of the second embodiment, in addition to the effects exhibited by the data processing circuit 100A of the first embodiment, the following effects can also be achieved.

  First, the YUV422 position selection information 131f can specify which format of the YUV422 data is UYVY, VYUYY, YUYV, or YVYU. Therefore, even if the YUV422 data transferred via the general-purpose bus 200 is in any of the UYVY, VYUYY, YUYV, and YVYU formats, by changing the YUV422 position selection information 131f in advance according to the format, the YUV422 data The V, Y, and U data can be extracted and converted into a 10-bit V data 181a, Y data 181b, and U data 181c.

  Further, the pixel format selection information 131g controls whether the selection circuit 190 selects the combination of the R data 111a, the G data 111b, and the B data 111c and the combination of the V data 181a, the Y data 181b, and the U data 181c. be able to. Therefore, by changing the pixel format selection information 131g in advance according to the pixel format of the pixel data transferred via the general-purpose bus 200, a set of R data 111a, G data 111b, B data 111c and V data 181a, Y A color conversion process can be performed by selecting a set of data 181b and U data 181c.

  Therefore, according to the data processing circuit 100B of the second embodiment, it is possible to realize pixel format conversion processing and color conversion processing that are more flexible than the data processing circuit 100A of the first embodiment.

2. Integrated Circuit Device, Electronic Device FIG. 15 is a block diagram illustrating a configuration of a projector as an example of the electronic device of the present embodiment.

  The projector 400 includes an image processing apparatus 500, an illumination optical system 610, a liquid crystal panel 620, and a projection optical system 630. Illumination light emitted from the illumination optical system 610 passes through the liquid crystal panel 620 and is modulated into image light representing an image. The image light is projected on the screen 700 by the projection optical system 630, whereby an image is displayed on the screen 700.

  The image processing apparatus 500 includes blocks such as a data processing circuit 510, an image processing circuit 520, a liquid crystal panel driving circuit 530, a CPU 540, a ROM 550, a RAM 560, a USB controller 570, a DMA controller 580, and the like. It is realized as an integrated circuit device (IC: Integrated Circuit) integrated on a chip.

  The data processing circuit 510, the image processing circuit 520, the liquid crystal panel driving circuit 530, the CPU 540, the ROM 550, the RAM 560, the USB controller 570, and the DMA controller 580 are connected to the general-purpose bus 590 and synchronized with a common clock signal (not shown). Can communicate with each other.

  The general-purpose bus 590 is a so-called “on-chip bus” used to connect various blocks inside the IC. For example, an AHB (Advanced High-Performance Bus) defined by the AMBA (registered trademark) standard is used. . The general-purpose bus 590 is a general-purpose bus capable of transmitting various bit data, and can perform bidirectional communication according to a protocol defined by the AMBA (registered trademark) standard or the like.

  The CPU 540 executes a control program stored in the ROM 550 to control the entire image processing apparatus 500, for example, the data processing circuit 510, the image processing circuit 520, the liquid crystal panel driving circuit 530, the USB controller 570, and the DMA controller 580. . In addition, the CPU 540 performs processing for transmitting image data stored in the ROM 550 or the RAM 560 to the data processing circuit 510 via the general-purpose bus 590.

  The RAM 560 is used for temporarily storing calculation results and image data by the CPU 540 and the image processing circuit 520.

  The USB controller 570 acquires image data input via a USB cable from a DVD player or a personal computer (not shown), and writes the acquired image data to the RAM 560 via the general-purpose bus 590 or the data processing circuit 510. Process to send.

  The DMA controller 580 performs processing for transmitting image data stored in the ROM 550 and the RAM 560 to the data processing circuit 510 via the general-purpose bus 590. Therefore, for example, when it is necessary to transmit a large amount of image data to the data processing circuit 510, the CPU 540 transmits control data (setting values of various control registers, etc.) to the DMA controller 580, and the necessary image data. Transmission processing can be left to the DMA controller. By doing so, the load on the CPU 540 is reduced.

  On the other hand, the data processing circuit 510 and the image processing circuit 520, and the image processing circuit 520 and the liquid crystal panel driving circuit 530 are connected by video buses 512 and 522, respectively. The video buses 512 and 522 are dedicated buses for transmitting digital image data, and perform one-way communication according to a protocol different from that of the general-purpose bus 590. Image data includes, for example, a 1-bit vertical synchronization signal that represents the beginning of each frame of a moving image or a still image, multiple bits (for example, 10 bits) of pixel data that represents information about each pixel, and the timing at which the pixel data is valid It consists of a 1-bit data enable signal.

  The data processing circuit 510 is implemented by the data processing circuit described with reference to FIGS. 1 to 14, receives pixel data via the general-purpose bus 590, and performs pixel format conversion processing and color conversion processing on the received pixel data. Then, the data processing circuit 510 transmits a vertical synchronization signal at the head of each frame to the image processing circuit 520 via the video bus 512, and then the pixel data for one frame (pixel format conversion processing and color conversion processing are performed. Processed pixel data) is transmitted together with a data enable signal.

  The image processing circuit 520 recognizes that pixel data of a new frame is transmitted by receiving a vertical synchronization signal from the data processing circuit 510 via the video bus 512. The image processing circuit 520 acquires pixel data when the data enable signal is valid, performs image processing for adjusting an image represented by the image data, and transmits the image data after the image processing via the video bus 522. Then, processing to transmit to the liquid crystal panel drive circuit 530 is performed. The specification of the image data transmitted via the video bus 522 is the same as the specification of the image data transmitted via the video bus 512.

  The image processing by the image processing circuit 520 includes, for example, adjustment processing of brightness, contrast, hue, and the like, processing for correcting image distortion such as trapezoid distortion, and so-called OSD (on-screen) for displaying various setting items on the screen. display) processing. The image processing circuit 520 receives control data (setting values of various control registers) via the general-purpose bus 590, and executes various image processing according to the control data.

  The liquid crystal panel drive circuit 530 drives the liquid crystal panel 620 based on the image data transmitted from the image processing circuit 520 via the video bus 522. As a result, an image represented by the image data is formed on the liquid crystal panel 620, and a desired image is projected on the screen 700.

  In the projector 400 of this embodiment, the data processing circuit 510 included in the image processing apparatus 500 is realized by the data processing circuit described with reference to FIGS. 1 to 14, thereby eliminating the need for the pixel format conversion and color conversion by the CPU 540. The load on the CPU 510 and memory resources can be reduced.

  In addition to projectors, electronic devices that can use this embodiment include mobile phones, portable game devices, personal computers, portable information terminals, pagers, electronic desk calculators, devices with touch panels, word processors, and viewfinders. Various electronic devices such as a type or monitor direct-view type video tape recorder and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A data processing circuit, 1B data processing circuit, 2 1st bus, 2a 1st pixel data signal, 3 2nd bus, 3a 2nd pixel data signal, 10 1st format converter, 12 pixel data signal , 20 color conversion unit, 22 pixel data signal, 30 register unit, 31 first setting information, 32 second setting information, 33 third setting information, 34 fourth setting information, 35 fifth setting information, 40 second format conversion unit, 42 pixel data signal, 50 pixel data selection unit, 52 pixel data signal, 100A data processing circuit, 100B data processing circuit, 110 RGB format conversion circuit, 111a R data, 111b G data, 111c B Data, 112 barrel shifter, 113 RGB data, 114a-114c selection circuit, 115a R data, 115b G data, 115c B data, 116a to 116c bit extension circuit, 118 RGB selection circuit, 119 RGB data, 120 color conversion circuit, 121a Y data, 121b U data, 121c V data, 130 register block, 131 format Conversion setting register, 131a MSB designation information, 131b R position designation information, 131c G position designation information, 131d B position designation information, 131e RGB565 selection information, 131f YUV422 position selection information, 131g pixel format selection information, 132 color conversion setting register, 140a bus interface circuit, 140b bus interface circuit, 150 FIFO memory, 151 RGB data, 152 YUV422 data, 160 FIFO Memory, 170 timing generation circuit, 180 YUV format conversion circuit, 181a V data, 181b Y data, 181c U data, 182 Y0 selection timing generation circuit, 183 Y0 selection signal, 184a-184c selection circuit, 185a V data, 185b Y data 185c U data, 186a-186c bit expansion circuit, 190 selection circuit, 191a RV data, 191b GY data, 191c BU data, 200 general-purpose bus, 201a address data, 201b address data, 202a write data, 202b write data, 203a select Signal, 203b select signal, 204a write signal, 204b write signal, 205a ready input signal, 205b ready input signal, 206a ready Output signal, 206b Ready output signal, 207a Read data, 210 CPU, 220 DMA controller, 230 Memory, 300 Video bus, 301 Vertical synchronization signal, 302 Horizontal synchronization signal, 303 Data enable signal, 304 YUV data, 305 Busy signal, 310 Image processing circuit, 400 projector, 500 image processing apparatus, 510 data processing circuit, 512 video bus, 520 image processing circuit, 522 video bus, 530 liquid crystal panel drive circuit, 540 CPU, 550 ROM, 560 RAM, 570 USB controller, 580 DMA controller, 590 General-purpose bus, 610 Illumination optical system, 620 Liquid crystal panel, 630 Projection optical system, 700 screen

Claims (8)

Data processing for receiving a first pixel data signal transmitted via a first bus according to a first protocol and converting it into a second pixel data signal transmitted via a second bus according to a second protocol A circuit,
A register section;
A first format conversion unit;
A color conversion unit,
The first pixel data signal is:
A plurality of first pixel element data for specifying color information defined in a given first color space;
The second pixel data signal is:
A plurality of second pixel element data for specifying color information defined in a given second color space;
The register part is
Storing first setting information for specifying an arrangement order of the plurality of first pixel element data in the first pixel data signal;
The first format conversion unit includes:
Based on the first setting information, the plurality of first pixel element data are extracted from the first pixel data signal with a given reference bit as a head, and the first pixel element data includes the plurality of first pixel element data. Generating a pixel data signal of one pixel format;
The color converter is
The pixel data signal generated by the first format conversion unit according to a given conversion formula from the first color space to the second color space is converted into pixel data including the plurality of second pixel element data. A data processing circuit that converts signals. In claim 1,
The register part is
Storing second setting information for specifying the reference bit of the first pixel data signal;
The first format conversion unit includes:
A data processing circuit that extracts the plurality of first pixel element data from the first pixel data signal based on the first setting information and the second setting information. In claim 2,
The register part is
Storing third setting information for specifying whether or not the reference bit of the first pixel data signal is a part of the first pixel element data;
The first format conversion unit includes:
A data processing circuit that determines whether or not to extract the reference bit as a part of the first pixel element data based on the third setting information. In any one of Claims 1 thru | or 3,
The first format conversion unit includes:
When the number of bits of each of the plurality of first pixel element data extracted from the first pixel data signal is m, the upper n bits (n ≦ m) are lower for each of the first pixel element data A data processing circuit which adds to n bits and bit-extends to m + n bits to generate a pixel data signal of the first pixel format. In any one of Claims 1 thru | or 4,
A second format conversion unit;
A pixel data selection unit,
The first pixel data signal has any one of a plurality of types of pixel formats,
The register part is
Fourth setting information for specifying a pixel format of the first pixel data signal, and an arrangement of the plurality of first pixel element data in the first pixel data signal of a predetermined pixel format Storing the fifth setting information of
The second format conversion unit includes:
Based on the fifth setting information, the plurality of first pixel element data is extracted from the first pixel data signal of the predetermined pixel format, and the second pixel element data includes the plurality of first pixel element data. Generate a pixel data signal in pixel format,
The pixel data selection unit
Based on the fourth setting information, the pixel data signal generated by the first format converter or the pixel data signal generated by the second format converter is selected,
The color converter is
The pixel data signal generated by the first format conversion unit or the second data selected by the pixel data selection unit according to a given conversion formula from the first color space to the second color space. A data processing circuit that converts the pixel data signal generated by the format conversion unit into a pixel data signal including the plurality of second pixel element data. In claim 5,
The second format conversion unit includes:
When the number of bits of each of the plurality of first pixel element data extracted from the first pixel data signal is j, the upper k bits (k ≦ j) are lower for each of the first pixel element data. A data processing circuit which adds to k bits and bit-extends to j + k bits to generate a pixel data signal of the second pixel format.   An integrated circuit device comprising the data processing circuit according to claim 1.   An electronic device comprising the integrated circuit device according to claim 7.

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