JPH11338408A - Scan converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a matching conversion of a synchronizing frequency without using a large-capacity frame memory. SOLUTION: In a resolution conversion part 32, image data per one horizontal scanning line relative to an input are written temporarily in banks 41, 42, and the data are read out, for example, twice to every datum, and a horizontal synchronizing frequency relative to an output is converted, for example, to the double of a horizontal synchronizing frequency relative to an input, and outputted to a display device 31 following this timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an input side of image data relating to an input when image data of an arbitrary input side image display system is input and output to a display device of a predetermined output side image display system. The present invention relates to a scan converter that converts a horizontal synchronizing frequency of an image display system into a synchronization frequency of image data of the output-side image display system.

[0002]

2. Description of the Related Art Display devices of general computing systems are required to have various sizes and various resolutions from the viewpoints of use and installation space. For example, if you want to enjoy multimedia software with a large image, use a resolution of 640 x 480 dots. On the other hand, if you want to display as much information as possible for a job with good visibility on one screen, In order to reduce fatigue, it is desirable to display at the highest possible resolution. Also, with the development of multimedia technology in computing systems in recent years and the start of digital television broadcasting services, in the near future there will be situations where the separation of computing systems from homes and television broadcasting will no longer be separated. It is anticipated that it is increasingly important to convert image signals of different synchronization frequencies to each other to match the display of images of different synchronization frequencies, such as between a computing system and a television broadcast receiver. It is becoming.

As described above, a scan converter is usually used as an interface for mutually converting image signals of a plurality of different kinds of synchronous frequencies.

Generally, as shown in FIG. 8, a scan converter converts a horizontal synchronizing frequency in accordance with image data Sin input from an input source device, and then converts the horizontal synchronization frequency into a display device such as a liquid crystal display display or a flat display such as a plasma display. 1 is output. At this time, for example, as a display method of the input source signal, as shown in FIG. 9, XGA, SVGA, VGA and VTX are used.
There are various types such as T. The horizontal synchronization frequency (H) and the vertical synchronization frequency (V) in these systems are determined by factors such as the technical level at the time these systems were developed.
It is set differently like. Therefore, the main function of the scan converter is to adjust the signals of various frequencies to be synchronized with the display device.

In this scan converter, FIG.
, RGB (red, green, blue) signal, YUV (luminance component, RY color difference component, BY color difference component) signal, or Y
When predetermined image data such as a CrCb (gamma-converted luminance / color difference separation color system) signal is input from an input source device, the first pixel processing unit 11 performs pixel thinning processing as necessary, Image data for one screen (frame) is stored in the frame memory 13 through the memory controller 12. After the image data is read out again by the memory controller 12, the second pixel processing unit 1
4 to inflate the pixel, and then output the YUV signal or YCrCb
The signal is input to the color format converter 15 and converted into an RGB signal. Then, after adjusting the brightness and the contrast by the brightness / contrast adjustment unit 16, the gamma correction unit 17 corrects the linearity of the adjustment change of the color different for each display device,
Dithering unit 1 performs color approximation correction when display colors are small.
Step 8 Then, the on-screen display synthesizing unit 19 synthesizes and controls a predetermined display adjustment display. Thereafter, the output adjusting unit 20 applies a 24-bit RGB signal to each of the odd-numbered port corresponding to the odd-numbered pixel and the even-numbered port corresponding to the even-numbered pixel according to the port format of the display device of the display device 1. Are output alternately. All of these image processing operations are executed by the CPU 21 according to a predetermined software program (driver device).

Here, at least two PLL circuits 22 and 23 are incorporated in the scan converter.
One PLL circuit 22 is used to synchronize the image data read by the first pixel processing unit 11 until the memory controller 12 writes the image data to the frame memory 13. The other PLL circuit 23 is used for synchronizing operations until image data is read from the frame memory 13 and output to the display device 1.
That is, the frame memory 1 is controlled by the memory controller 12.
The writing operation of the image data to 3 is performed in synchronization with the signal from the input source device in accordance with the transmission frequency of one PLL circuit 22. On the other hand, the operation in which the memory controller 12 reads the image data in the frame memory 13 is as follows.
The operation is performed so as to correspond to the operation clock of the display device 1 at the output destination in accordance with the oscillation frequency of the other PLL circuit 23. As described above, the two separate PLL circuits 22 and 23 transmit operation clocks having different frequencies under the control of the CPU 21, and the frame memory 1
The horizontal synchronization frequency of the input / output image signal can be easily changed by executing the reading and writing of the image data with respect to 3 at different clock frequencies.

[0007]

The capacity of the frame memory 13 used in the above-described scan converter is required to be at least as large as the size of the output device (that is, the display device 1 on the output side).
In the case of a screen of 768 dots, 1024 × 768
× 24 = 18,874,368 bits of capacity is required.

[0008] Such a frame memory 13 is generally expensive, and has been a cause of impeding space saving in circuit configuration.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a scan converter which can omit a frame memory and can be constructed at a low cost.

[0010]

Means for Solving the Problems In order to solve the above problems,
According to the first aspect of the present invention, when image data of an arbitrary input-side image display method is input and output to a display device of a predetermined output-side image display method, the input-side image display of the input image data is performed. A scan converter that converts the horizontal synchronization frequency of the input-side image display system to match the synchronization frequency of the image data of the output-side image display system, and a measurement unit that measures the horizontal synchronization frequency of the input-side image display system; and the measurement unit. A timing control unit for converting the horizontal synchronizing frequency to a predetermined integer magnification according to the measurement result in step (a), and a bank for temporarily storing input image data for each horizontal scanning line. The horizontal scanning lines stored in the memory are repeatedly read out a predetermined number of times corresponding to the predetermined integer magnification according to the measurement result of the measurement unit, and the resolution of the image data is converted. A resolution conversion unit, and an output control unit that outputs the image data output from the resolution conversion unit to the display device at the horizontal synchronization frequency converted to the predetermined integer magnification by the timing control unit. is there.

According to a second aspect of the present invention, the timing control section counts a horizontal synchronization signal of the horizontal synchronization frequency with reference to a vertical synchronization signal input from an input source device. A function of determining a horizontal scanning line that does not need to be displayed on the display device side according to a measurement result of the measurement unit, and the output control unit has a function of determining a horizontal scanning line that does not need to be determined determined by the timing control unit. This is provided with a masking function for stopping the output of image data relating to the scanning line.

According to a third aspect of the present invention, the bank of the resolution conversion section includes an odd buffer for temporarily storing all of the odd-numbered pixels in each of the horizontal scanning lines, and an odd buffer for temporarily storing all of the odd-numbered pixels in each of the horizontal scanning lines. And an even buffer that temporarily stores all of the even-numbered pixels, and wherein the output control unit includes: an odd-numbered pixel in one line output from the odd-numbered buffer; This is to output even-numbered pixels in a line in parallel.

According to a fourth aspect of the present invention, for each pixel of the image data output from the resolution conversion unit, the pixel data is interposed between another pixel adjacent to the pixel in the horizontal scanning direction and the vertical scanning direction. And a filter for performing pixel adjustment by weighting with.

[0014]

FIG. 1 is a diagram showing a scan converter 30 according to one embodiment of the present invention. This scan converter is installed in advance in a multi-display or the like for displaying image information from a computing system, a television receiver, or the like, and is installed from an input source device as shown in FIG. The horizontal synchronization frequency of the given image data is changed to the output destination display device 31.
Is converted so as to match with.

Here, in this embodiment, the display device 3
As an example, a liquid crystal display panel (LCD) 31a of 1024 × 768 dots is built in.
A general liquid crystal display driven by the driver 31b and the Y driver 31c is applied. Here, the display device 31 has two ports: an odd-numbered port to which an odd-numbered pixel (odd-numbered pixel) in one horizontal scanning line is input, and an even-numbered port to which an even-numbered pixel (even-numbered pixel) is input. The odd-numbered port and the even-numbered port each receive a 24-bit RGB signal promptly. In this way, 24-bit image data (odd pixel and even pixel) are input in parallel to each of the odd port and the even port, and a total of 48 (= 24 × 2) bits are input. Therefore, even when image data is input at half the display frequency in the display device 31, sufficient synchronization can be achieved.

Then, the scan converter 30
Pixel data is stored in an odd buffer (1/2 line) 41a,
42a and even buffers (1/2 line) 41b, 42
b is alternately written and read out and output in parallel, so that the horizontal synchronizing frequency (HSi) related to each and the input image data can be uniformly doubled and the screen can be converted. By thinning out end lines that are not necessary for display, the frame memory (13) and the two P memories as in the conventional example shown in FIG.
Even if the LL circuits (22, 23) are omitted, synchronization matching can be obtained without any problem.

That is, the scan converter 30 converts a resolution of a 24-bit RGB signal (RGB24) from the outside into a resolution converter 32, and outputs attribute information in pixel units from the resolution converter 32 to adjacent pixels. , A filter 33 for adjusting between, an image adjusting unit 34, a dividing cycle 36 for dividing the synchronization signal from the external PLL 35,
A timing control unit 37 for controlling operation timings of the resolution conversion unit 32 and the image adjustment unit 34 based on a synchronization signal given from an input source, and a horizontal synchronization signal Hsync and a vertical synchronization signal from an oscillator 38 in the input source device Vsyn
Sync measurement unit 39 (measurement unit) for measuring c, and all elements 32, 34, and 3 in scan converter 30
6, 37, and 39 are provided.

As shown in FIG. 2, the resolution conversion section 32 has two banks 41 and 42 which operate alternately for writing and reading.
Are odd buffers (1/2 line) 41a and 42a in which odd-numbered pixels (odd pixels) in one horizontal scanning line are temporarily stored, and even-numbered pixels (even pixels) are temporarily stored. And even buffers (1/2 line) 41b and 42b, respectively. Each buffer 41a, 41b, 42a, 42b
The bit length is set to half the length of one horizontal scanning line. The alternate switching between the two banks 41 and 42 is executed, for example, in response to the fall of the horizontal synchronizing signal Hsync. One of the banks 41/42 is connected to the input terminal 43 through the switch 43a to write image data. During operation, the other bank 42/41 is connected to the connection terminal 4 on the filter 33 side through the switches 45a and 45b.
4a and 44b are connected to operate for reading image data. The switch 43a is connected to one of the banks 4
In the state where the odd buffers 41a and 42a are connected to the horizontal buffers 1a and 1b, respectively, that is, each pixel (pixel) in one horizontal scanning line is input.
And the even buffers 41b and 42b alternately.
Thereby, each odd buffer 41 of each bank 41, 42 is provided.
Only odd pixels are stored in a and 42a, and only even pixels are stored in the even buffers 41b and 42b. The switching operation of these switches 43a, 45a, 45b is executed according to an operation control signal from the timing control unit 37.

Note that an analog RGB signal (A-RGB) is originally output from the input source device, and the analog RGB signal (A-RGB) is converted by an analog / digital converter (ADC) 46. After being converted to a 24-bit digital RGB signal (RGB24), it is input to the resolution conversion unit 32. Here, FIGS. 1 and 2 show an example in which a single ADC is used.
If the processing speed of the DC 46 is slower than the processing inside the scan converter 30, two analog / digital converters are used in parallel to convert a 24-bit digital RGB signal (RGB24) in parallel. Conversion unit 32
May be input. In this case, a pair of analog / digital converters (ADCs) may be connected to the odd buffers 41a and 42a and the even buffers 41b and 42b of the banks 41 and 42 via switches.

The filter 33 is a circuit for performing a weighting operation process with respect to each pixel and other pixels which have been input in advance and performing pixel adjustment such as a pixel smoothing process. An odd-numbered pixel operation unit 51 that performs processing on odd-numbered pixels and an even-numbered pixel operation unit 52 that performs processing on even-numbered pixels are provided. Each of the pixel operation units 51 and 52 has five dot buffers (1 dot) for temporarily storing pixel data of one pixel.
53 to 58, two line buffers (1 line) 59 and 60 having a storage capacity of the number of dots for one line, and pixel data from these buffers 55 to 60 and the latest input from the resolution conversion unit 32 9 with the pixel data
Multipliers 61 to 69 for weighting pieces of data, and adders 71 to 69 for adding outputs from all the multipliers 61 to 69
74, and an output control unit 75 that outputs the data output from the adders 71 to 74 to the image adjustment unit 34.

The first dot buffer 53 and the second dot buffer 53 are connected in series, and the switches 45a, 45
5b is connected to the resolution conversion unit 32. As a result, the first dot buffer 53 stores the pixel data input earlier than the latest input pixel data from the resolution conversion unit 32 by one clock, and the second dot buffer 54 stores the resolution. The pixel data input before the latest input pixel data from the conversion unit 32 by two clocks is stored.

Each of the line buffers 59 and 60 has a storage capacity of the number of dots for one line as described above, but the data input from the resolution conversion unit 32 Since only the odd-numbered pixels and the even-numbered pixel operation unit 52 have only even-numbered pixels, only half of the pixel data per one horizontal scanning line is stored. Therefore, the first line buffer 59 having the storage capacity of the number of dots for one line stores the odd pixels in the two horizontal scanning lines and then sequentially outputs the odd pixels. After even pixels in two horizontal scanning lines are stored in the buffer 60, they are sequentially output. Thereby, the first line buffer 59 and the second line buffer 59
Is output after one of the odd-numbered pixels or the even-numbered pixels is stored in the line buffer 60 for each skipped horizontal scanning line.

Then, the third dot buffer 55 and the fourth dot buffer 56 are connected in series and connected to the first line buffer 59. As a result, the third dot buffer 55 stores the pixel data output earlier by one clock than the pixel data output latest from the first line buffer 59, and the fourth dot buffer 56 stores The pixel data output two clocks ahead of the pixel data output most recently from the first line buffer 59 is stored.

Further, the fifth dot buffer 57 and the sixth dot buffer 58 are connected in series and connected to the second line buffer 60. As a result, the fifth dot buffer 57 stores the pixel data output one clock earlier than the pixel data output most recently from the second line buffer 60, and the sixth dot buffer 58 stores The pixel data output two clocks ahead of the pixel data output most recently from the second line buffer 60 is stored.

The multipliers 61 to 69 are connected to the latest pixel data input from the resolution converter 32 and the buffers 53 to 6.
Count k for each pixel data output from 0
Weighting is performed by integrating 1 to k9. Also,
The adders 71 to 74 determine pixel data adjusted between adjacent pixels by adding the data weighted by the multipliers 61 to 69. That is, the multiplier 61
Due to the weighting at .about.69 and the addition at the adders 71 to 74, the latest pixel data input from the resolution conversion unit 32 is the same as the two pixels previously input in the horizontal direction and these pixels. Adjustment such as pixel smoothing processing by weighting is performed using pixels input two lines earlier. By such processing, a smooth image can be obtained in both the horizontal direction and the vertical direction, and therefore, it is possible to contribute to improvement in image quality.

The output control unit 75 includes a timing control unit 37
Pixel data according to the instruction control from the image adjustment unit 3
In particular, a masking function for stopping the output of pixel data to the image adjustment unit 34 in accordance with an instruction from the timing control unit 37 is provided for the “thinning-out process” for each scanning line described later. .

Each pixel operation unit 5 in the filter 33
All the operations in 1 and 52 are executed based on a timing control signal from the timing control unit 37.

The image adjustment unit 34 includes a color format conversion unit (15), a luminance / contrast adjustment unit (16), a gamma correction unit (17), and a dithering unit (1) in the conventional example shown in FIG.
8) and a circuit corresponding to the on-screen display synthesis section (19).

As shown in FIG. 1, the dividing cycle 36 receives a synchronizing signal from the PLL 35 in the input source device and converts it into, for example, a double frequency synchronizing signal. The signal is taken into the timing controller 37 and used as an operation base clock for various timing controls.

The Sync measuring section 39 obtains a base clock from the oscillator 38 on the circuit board on which the scan converter 30 is mounted, compares the base clock with the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync,
The synchronization frequency attribute of the input source device is determined, and the result is transmitted to the timing control unit 37. The synchronization frequency attribute of the input source device determined here is, for example, VGA or S
This is an attribute of a frequency characteristic value set in advance for each predetermined image display method such as VGA, and makes a determination according to data in a predetermined table stored in a nonvolatile ROM or the like.

The timing control unit 37 uses the divided synchronization signal given from the dividing cycle 36 as an operation clock,
The timing of the resolution conversion unit 32 and the filter 33 is controlled in accordance with the synchronization frequency attribute of the input source device provided from the nc measurement unit 39. For example, in the case where the image display system of the image signal from the input source device is XGA, and the synchronization frequency is matched with the output destination display device 31 from the beginning, the resolution conversion unit 32 And the filter 33, the horizontal synchronization signal Hs from the input source device.
A synchronization signal having the same cycle as that of the input signal is provided so that the input / output synchronization frequency is not changed. On the other hand, when the image display method of the image signal from the input source device is VGA or SVGA, In the case where the synchronous frequency is changed for the display device 31, the synchronous frequency for input and output is changed for the resolution converter 32 and the filter 33.

Here, as shown in FIG. 3, a thinning-out timing control circuit 77 for thinning out horizontal scanning lines that do not need to be output when outputting from the scan converter 30 to the display device 31 is built in the timing control unit 37. ing. The thinning-out timing control circuit 77 determines whether to thin out the output of the image data on a line-by-line basis based on the horizontal synchronization signal Hsync given from the input source device and the information on the determination result in the Sync measuring unit 39. A determining unit 78, a thinning signal output unit 79 that outputs a thinning signal in accordance with an output from the thinning line determining unit 78,
An output control unit 75 of the filter 33 and a synchronizing signal output stopping unit 80 for stopping the output of the horizontal synchronizing signal Hsync to the display device 31 when the thinning signal is output from the thinning signal output unit 79 are provided.

The thinning line determination unit 78 counts the horizontal synchronization signal Hsync based on the input of the vertical synchronization signal Vsync provided from the input source device, and the number of the currently input image is the horizontal scanning line. This is a counter for recognizing whether or not. When the count value in the thinned line determination section 78 becomes “0”, the count value is transmitted to the thinned signal output section 79 as all signals of a plurality of lines.

The thinning signal output unit 79 has a function of determining whether or not the horizontal scanning lines counted by the pattern comparing unit 28 are lines to be thinned according to the determination result of the Sync measuring unit 39. When it is necessary to thin out, a low signal is output as a thinning signal to the synchronizing signal output stopping section 80, and otherwise, a high signal is transmitted to the synchronizing signal output stopping section 803.

Specifically, for example, in the case of a simple operation of thinning out only one of the count values of all the lines in the thinned line judging section 78, the input from the thinned line judging section 78 is performed. When the counted value becomes “0” value and all of the plurality of lines given from this become “0” value, an OR circuit that recognizes this is applied.

On the other hand, in the case of a complicated operation such as thinning out a plurality of lines among the count values for all the lines in the thinning line judgment unit 78, only a simple OR circuit is used as the thinning signal output unit 79. It is difficult to determine an appropriate timing for thinning out only by doing so. In this case, the data length of one line of the input image data and the data length of one line of the image data to be output are limited to several combinations corresponding to the types of the image display methods. By preparing several types of combinations as a data table, a thinned line can be determined efficiently. In this case, a non-volatile storage device is provided inside or outside the decimation signal output unit 79, and information on the decimation line corresponding to the synchronization frequency attribute of the input source device is stored in advance in the non-volatile storage device as a data table. The data table may be referred to to determine whether or not it is necessary to thin out according to the count result.

The synchronizing signal output stopping section 80 is an AND circuit for calculating the logical product of the output signal from the thinning signal output section 79 and the horizontal synchronizing signal Hsync, and the signal from the thinning signal output section 79 is a high signal. When there is, the horizontal synchronization signal Hsync is output to the output control unit 75 and the display device 31. On the other hand, when the signal from the thinning signal output unit 79 is a low signal (thinning signal), the horizontal synchronization signal Hs
A low signal is output regardless of the high / low state of the sync.

The operation of the scan converter having the above configuration will be described. First, in a case where the image display system of the image signal from the input source device is XGA, the output destination display device 3
When the synchronization frequency is matched from the beginning, the timing control unit 37 controls the resolution conversion unit 32 and the filter 33 to synchronize with the horizontal synchronization signal Hsync from the input source device in the same cycle. A signal is given so that the input / output synchronization frequency is not changed. At this time, the input horizontal synchronization signal Hsync (input Hsync) 8
1 and the horizontal synchronizing signal Hsync upon output (output Hs
ync) 82 is as shown in FIG. In FIG. 4, for simplicity of explanation, the total number of horizontal scanning lines for input / output is 7
Although it is a book, the number is actually much larger than this.

On the other hand, when the image display method of the image signal from the input source device is VGA or SVGA and the synchronization frequency is changed for the output destination display device 31, the timing control unit 37 changes the input / output synchronization frequency for the resolution conversion unit 32 and the filter 33. FIG. 5 shows an example in which the total number of horizontal scanning lines related to output is 1.8 times the total number of input horizontal scanning lines. In FIG. 5, the input Hsyn
c, the image data inputted according to c
Image data output according to sync is indicated by reference numeral 84. Reference numeral 85 indicates the output timing of the output image data in the conventional example. Block breaks in these image data indicate horizontal scanning lines in each image data. In FIG. 5, for simplicity of explanation, the total number of horizontal scanning lines for input is set to 5 and the total number of horizontal scanning lines for output is set to 9, but in practice, it is far more than this. Needless to say, the number is large.

Conventionally, as shown in FIG. 5, the last line (fifth line) Li5 related to the input image data 83
And the timing of the end of the last line (ninth line) Lpo9 of the output image data 85. In connection with this, in each line cycle, the output image data 85 does not have a frequency exactly twice that of the input image data 83, and in the example of FIG. 5, the ratio of these line cycles is 5: It is 9.
For this reason, complicated control has to be performed to determine what data is allocated to each pixel in each line ("1" to "9") of the conventional output image data 85.

On the other hand, in this embodiment,
Assuming that the frequency of the input Hsync is HSi and the frequency of the output Hsync is HSo, a relationship of “HSo = 2 × HSi” is established. As a result, the output image data 84 has a frequency exactly twice that of the input image data 83. The ratio of each line cycle is 1: 2. Then, the timing does not coincide with the end timing of the last line (ninth line) Lso9 of the output image data 84,
After the last line (ninth line) Lso9, there is a time when the thinning processing is performed. That is, in the time zone in which the thinning process is performed, the output control unit 75 does not output the pixel data to the image adjusting unit 34 under the control of the timing control unit 37. No display is performed on the horizontal scanning line corresponding to.

Since the ratio between the line periods of the output image data 84 and the input image data 83 is 1: 2, which is simpler than the conventional one, the odd-numbered lines ("1") in the output image data 84 "3", "5", "7") and even-numbered lines ("2", "4", "6") respectively following
If “8”) is simply arranged in the same pixel array, it is possible to easily perform pixel matching without performing complicated pixel rearrangement.

The operation in scan converter 30 at this time will be described in detail. The following operations in the scan converter 30 are all achieved by the CPU 40 controlling each of the elements 32, 33, 34, 35, 37, and 39 according to a predetermined driver program.

First, the Sync measuring section 39 compares the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync given from the input source device with the base clock signal from the oscillator 38, and determines the synchronization frequency attribute of the input source device. Judge,
The result is transmitted to the timing control unit 37. On this occasion,
For example, the image display system of the input source device is the XGA system, and the synchronization frequency HSi of the horizontal synchronization signal Hsync is 5
When the frequency is 8 KHz, the timing control unit 37
As described above, the filter 33 and the image adjustment unit 34 are operated at the same frequency HSi as the input synchronization frequency HSi to output image data to the display device 31. On the other hand, for example, the image display system of the input source device is the VGA system, and the synchronization frequency HSi of the horizontal synchronization signal Hsync is 32 KH.
In the case of z, the timing control unit 37 determines that the frequency HSi (64K
Hz), and the image display system of the input source device is SVGA
When the synchronization frequency HSi of the horizontal synchronization signal Hsync is 48 KHz, the timing control unit 37
Then, as shown in FIG. 6, the filter 33 and the image adjustment unit 34 are operated at a frequency HSi (96 KHz) that is twice the input synchronization frequency HSi, and the image data is output to the display device 31.

In the resolution conversion section 32, as shown in FIG.
Image data from the input source device is temporarily written and read out to the filter 33 and output while being alternately switched between a, 45a, and 45b. At this time, the odd buffers 41a and 42a and the even buffers 41b and 41b are provided for each pixel.
2b, and odd-numbered pixels in one line are replaced with odd-numbered buffers 41 as in "(3) Write Line buf" in FIG.
a, 42a, and “(4) Write Li” in FIG.
ne buf ", the even pixels are stored in the even buffer 41b,
After writing to the 42b, each read is performed (“(5) (6) Read Line buf” in FIG. 7).

In FIG. 7, "A" is used as shown in FIG.
「F’, the input horizontal synchronization signal H
8 shows a state of operation according to sync ((1) in FIG. 7). However, in (3) to (11) in the same drawing, six pixels “0” to “5” are replaced with odd pixels “0”.
Although an example is shown in which processing is performed separately for “2”, “4” and even-numbered pixels “1”, “3”, and “5”, one horizontal scanning line is actually configured with a much larger number of pixels than six. Of course.

At this time, “(5) (6) Read Line bu
In “f”, odd-numbered pixel rows formed one by one ((3) Write Line buf = “0” “* (blank data)”
"2", "*", "4", "*") and even pixel rows ((4)
Write Line buf = "*""1""*""3""*"
For each of “5”), only the portion excluding “*” is extracted and read twice each. That is, the blank data "*" is packed, and as a result, the half cycle line data compressed to half cycle data is read twice each, and (5) Read L
ine buf = “0” “2” “4” “0” “2” “4” and (6) Read Line buf = “1” “3” “5” “1”
It is converted into data “3” and “5”.

Each pixel operation unit 51, 5 of the filter 33
2, the pixel data is temporarily stored in each of the buffers 53 to 60, and then the multiplier 61
After being output to # 69 and weighted by predetermined counts k1 to k9, they are added by addition in adders 71 to 74. As a result, a smooth image is obtained in both the horizontal and vertical directions, and the image quality is improved. The output result of the filter 33 is “(7) (8) Filter o” in FIG.
ut ”.

In parallel with the above operation, in the timing control unit 37, the horizontal synchronizing signal Hs
Each time SYNC is input, it is deciphered by the thinning line determination unit 7
8 and based on this, the thinning signal output unit 7
In step 9, a horizontal scanning line to be subjected to the thinning process is determined, and if necessary, the data is output to the output control unit 75 and the display device 31 through the synchronization signal output stop unit 80 by referring to a data table.

Here, as a result of the determination by the timing control section 37, if the thinning processing is not performed, the thinning signal output section 79 outputs “1 (high signal)” to the synchronization signal output stop section 80. . In the synchronizing signal output stop unit 80, the horizontal synchronizing signal Hsync is output to the output control unit 75 and the display device 31 as it is while “1 (high signal)” is given from the thinning signal output unit 79.

As described above, when the thinning process is not performed,
In the processing for the horizontal scanning lines “A” to “D” and “F” in FIG. 7, each image data is output to the image adjustment unit 34 according to the instruction signal from the timing control unit 37, and the image adjustment unit 34 After the predetermined process is performed in the display device 3 as shown in “(9) (10) Output image data” in FIG.
1 is output. In parallel with this, the scan converter 30 outputs a horizontal synchronizing signal Hsync (“(11) Output Hsync” in FIG. 7) related to the output. Here, the image display method of the input source device is VGA or SVG.
A shows the case of the A method, and the horizontal synchronization signal H
The synchronization frequency of the horizontal synchronization signal Hsync related to the output is doubled because the output processing is performed in parallel on two lines with respect to the synchronization frequency of sync. In the display device 31, the horizontal synchronization signal Hsync output here (“(11) Output H in FIG. 7)
sync)), the display processing of “(9) (10) output image data” in FIG. 7 is performed line by line.

On the other hand, as a result of the judgment in the timing control section 37, when it is necessary to perform the thinning processing, the thinning signal output section 79 (logical sum circuit) outputs the synchronization signal output stop section 80.
Outputs “0 (low signal)”. In the synchronization signal output stop unit 80, when the input signal from the thinning signal output unit 79 is “0 (low signal)”, the horizontal synchronization signal Hsync for the output control unit 75 and the display device 31
Is stopped (reference T in (11) in FIG. 7).
1). Then, the output of the image data from the output control unit 75 to the image adjustment unit 34 is stopped as indicated by the symbol T2 of “(9) (10) output image data” in FIG. Processing and output of image data to the display device 31 are not performed. At the time of thinning processing, the horizontal synchronization signal Hsy from the timing control unit 37 to the display device 31 is output.
nc is not transmitted. Therefore, the display device 31 does not display a horizontal scanning line corresponding to the portion subjected to the thinning process.

As described above, in the resolution conversion section 32, one line of image data is divided into odd-numbered pixels and even-numbered pixels and written into the odd-numbered buffers 41a and 42a and the even-numbered buffers 41b and 42b, respectively, and these are read twice. , The horizontal frequency is doubled, so that the expensive large-capacity frame memory (1
The conversion of the synchronization frequency can be easily performed without using 3). Therefore, the entire scan converter can be provided at a small area and at a low price.

At this time, since the filter 33 performs the pixel adjustment processing by weighting the pixels adjacent in both the horizontal scanning direction and the vertical scanning direction, the image quality can be improved.

In the above embodiment, the pixel data is alternately written into the odd buffers (1/2 line) 41a, 42a and the even buffers (1/2 line) 41b, 42b, and read out and output in parallel. In this way, the frequency of the horizontal synchronization signal Hsync is doubled by the timing control unit 37, and the buffers 41a, 41b,
The image data in the pixels 42a and 42b is read twice each time. However, the present invention is not limited to this. For example, pixel data is alternately written to these using three or more N buffers, and these are respectively written. The data may be read out and output in parallel to the display device 31 at the output destination using N lines. In this case, the capacity of each buffer is 1 / Nlin
e would be fine.

In the above embodiment, the display device 31
As an example, a 1024 × 768 dot liquid crystal display panel (LCD) is applied. However, if a digital input type is used, for example, a plasma display panel (P
DP) can be applied. Also,
The screen size is not limited to 1024 × 768 dots, and a large screen display such as 1280 × 1024 dots may be applied.

[0057]

According to the first aspect of the present invention, in the resolution conversion section, image data for each horizontal scanning line is once written to a bank, and these are written an integer number of times (for example, V
The horizontal synchronization frequency for output is converted into an integer multiple of the horizontal synchronization frequency for input (for example, twice for VGA or SVGA), and the display device is read in accordance with this timing. , It is possible to easily perform matching conversion of the synchronization frequency without using an expensive large-capacity frame memory as in the related art. Therefore, the entire scan converter can be provided at a small area and at a low price.

According to the second aspect of the present invention, the timing control section counts the horizontal synchronization signal of the horizontal synchronization frequency with reference to the vertical synchronization signal input from the input source device. In accordance with the measurement result in the measurement unit, the display device determines a horizontal scan line that does not need to be displayed on the display device side, and in the output control unit, outputs image data related to the horizontal scan line that does not need to be determined determined in the timing control unit. Is stopped, the unnecessary end lines on the screen display can be easily thinned out, and the matching with the screen size of the display device can be easily achieved.

According to the third aspect of the present invention, the odd-numbered pixels and the even-numbered pixels in one line are output in parallel. The processing can be speeded up by processing the second pixel and the even pixel separately, and the data transmission to the display device is transmitted separately by transmitting the odd pixel and the even pixel separately. Processing can be made more efficient.

According to the fourth aspect of the present invention, the filter assigns a weight to each pixel of the image data to other pixels adjacent to the pixel in the horizontal and vertical scanning directions. Since the pixel adjustment is performed, the image quality at the time of displaying on the display device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a scan converter and a display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a resolution converter, a filter, and the like in the scan converter according to the embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration of a timing control unit in the scan converter according to one embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between input image data and output image data when XGA image data is input in one embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between input image data and output image data when VGA or SVGA image data is input according to an embodiment of the present invention;
FIG. 5 is a diagram showing nc and output Hsync.

FIG. 6 is a diagram showing a correspondence between a horizontal synchronization frequency related to input and a horizontal synchronization frequency related to output according to one embodiment of the present invention.

FIG. 7 is a timing chart showing a processing operation of each image data in the scan converter according to one embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional scan converter.

FIG. 9 is a diagram illustrating a correspondence relationship between a horizontal synchronization frequency and a vertical synchronization frequency of each general screen display method.

[Explanation of symbols]

 Reference Signs List 30 scan converter 31 display device 31a LCD 32 resolution conversion unit 33 filter 34 image adjustment unit 35 PLL 36 division period 37 timing control unit 38 oscillator 39 Sync measurement unit 40 CPU 41, 42 bank 41b, 42b even buffer 41a, 42a odd buffer 43 Input terminals 43a, 45a, 45b Switch 51 Odd pixel operation unit 52 Even pixel operation unit 53 First dot buffer 54 Second dot buffer 55 Third dot buffer 56 Fourth dot buffer 57 Fifth dot buffer 58 No. 6 dot buffer 59 first line buffer 59, 60 line buffer 60 second line buffer 61 to 69 multiplier 71 to 74 adder 75 output control unit 77 thinning timing control circuit 78 thinning line Down determining unit 79 decimating the signal output unit 80 the synchronization signal output stop unit 83 inputs image data 84 output image data 85 prior output image data Hsync horizontal synchronizing signal Vsync vertical synchronizing signal

Claims (4)

[Claims] When image data of an arbitrary input-side image display method is input and output to a display device of a predetermined output-side image display method, horizontal synchronization of input-related image data of the input-side image display method is performed. A scan converter that converts a frequency to match a synchronization frequency of image data of the output-side image display method, a measurement unit that measures a horizontal synchronization frequency of the input-side image display method, and a measurement result of the measurement unit. A timing control unit for converting the horizontal synchronization frequency to a predetermined integer magnification according to the following, and a bank for temporarily storing input image data for each horizontal scanning line are built in and stored in the bank. A resolution changer for converting the resolution of image data by repeatedly reading horizontal scanning lines a predetermined number of times corresponding to the predetermined integer magnification according to the measurement result of the measurement unit. A scan converter comprising: a conversion unit; and an output control unit configured to output the image data output from the resolution conversion unit to the display device at the horizontal synchronization frequency converted to the predetermined integer magnification by the timing control unit. 2. The scan converter according to claim 1, wherein the timing control unit counts a horizontal synchronization signal having the horizontal synchronization frequency with reference to a vertical synchronization signal input from an input source device. A count result at the time and a function of determining a horizontal scanning line that does not need to be displayed on the display device side according to the measurement result of the measurement unit.The output control unit is determined by the timing control unit. A scan converter having a masking function for stopping output of image data relating to horizontal scanning lines that do not require display. 3. The scan converter according to claim 1, wherein the bank of the resolution conversion unit temporarily stores all of the odd-numbered pixels in each of the horizontal scanning lines. A buffer, and an even buffer for temporarily storing all of the even-numbered pixels in each of the horizontal scanning lines, wherein the output control unit outputs one of the pixels output from the odd-numbered buffer.
A scan converter characterized in that odd-numbered pixels in a line and even-numbered pixels in one line output from the even buffer are output in parallel. 4. The scan converter according to claim 1, wherein for each pixel of the image data output from the resolution conversion unit, a horizontal scanning direction and a vertical A scan converter, characterized in that it has a filter for performing pixel adjustment by weighting with other pixels adjacent to each other in the scanning direction.