CN111554248A - Liquid crystal display chip - Google Patents
Liquid crystal display chip Download PDFInfo
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- CN111554248A CN111554248A CN202010539545.5A CN202010539545A CN111554248A CN 111554248 A CN111554248 A CN 111554248A CN 202010539545 A CN202010539545 A CN 202010539545A CN 111554248 A CN111554248 A CN 111554248A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/643—Hue control means, e.g. flesh tone control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/68—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/73—Colour balance circuits, e.g. white balance circuits or colour temperature control
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
- G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
- G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
- G09G2370/047—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial using display data channel standard [DDC] communication
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The invention discloses a liquid crystal display chip, which comprises a video zooming circuit, an image processing circuit electrically connected with the video zooming circuit, a TVOUT circuit electrically connected with the image processing circuit, and a data corresponding table circuit electrically connected with the TVOUT circuit, wherein the video zooming circuit is connected with the image processing circuit; the system comprises a first USB interface, a CPU bus, a RAW/JPEG format decoder, an SRAM, a DMA, a CPU, a timer and a DDR2 memory interface; the first USB interface, the RAW/JPEG format decoder, the SRAM, the DMA, the CPU, the timer and the DDR2 memory interface are electrically connected with a CPU bus respectively. The invention can support the display of USB video signals.
Description
Technical Field
The invention belongs to the technical field of display chips, and particularly relates to a liquid crystal display chip.
Background
The existing HDMI/VGA display interfaces have display data channel interfaces (dddcci), but all belong to communication designs that read in one direction and have very small bandwidth (105200 bps). The lcd supporting the touch signal cannot integrate the signal in the same interface and return to the main control terminal through the same transmission line, and a specific interface must be provided additionally, thereby increasing the design and production costs of the product.
Therefore, it is necessary to develop a new liquid crystal display chip.
Disclosure of Invention
The invention aims to provide a liquid crystal display chip capable of supporting USB video signals.
The liquid crystal display chip comprises a video zooming circuit, an image processing circuit electrically connected with the video zooming circuit, a TVOUT circuit electrically connected with the image processing circuit, and a data corresponding table circuit electrically connected with the TVOUT circuit; the system comprises a first USB interface, a CPU bus, a RAW/JPEG format decoder, an SRAM, a DMA, a CPU, a timer and a DDR2 memory interface;
the first USB interface, the RAW/JPEG format decoder, the SRAM, the DMA, the CPU, the timer and the DDR2 memory interface are respectively and electrically connected with a CPU bus;
the first USB interface is used for receiving a digital signal USB input video signal, temporarily storing related data in a DDR2 memory connected with a DDR2 memory interface through a DMA (direct memory access), the RAW/JPEG (RAW-data-joint photographic experts group) format decoder can take out the related data from the DDR2 memory through the DMA according to the time pulse required by each Frame of the video zooming circuit and decode the related data into a correct image format, temporarily stores the related data in a Frame buffer area, stores the related data in the DDR2 memory through the DMA, and inputs the decoded data into the video zooming circuit through the DMA to be processed
Or the first USB interface is used for receiving a digital signal USB input video signal, and temporarily storing the related data in a DDR2 memory connected with a DDR2 memory interface through DMA, the RAW/JPEG format decoder takes out the related data from the DDR2 memory through DMA according to the clock pulse required by each frame of the video scaling circuit, and then decodes the related data into a correct image format and inputs the decoded data to the video scaling circuit for processing.
The system further comprises a TMDS RX PHY interface, an HDMI audio phase-locked loop and an HDMI digital logic circuit, wherein the TMDS RX PHY interface and the HDMI audio phase-locked loop are respectively and electrically connected with the HDMI digital logic circuit; the HDMI digital logic circuit is electrically connected with the input video signal switching interface;
the TMDS RX PHY interface is used for receiving the digital signal HDMI input video signal, and the digital signal is processed by the HDMI digital logic circuit and then transmitted to the input video signal switching interface.
Further, the device also comprises an ADC _ B, ADC _ G, ADC _ R, SOG composite synchronous separator and an analog front-end digital logic circuit, wherein the DC _ B, ADC _ G, ADC _ R, SOG composite synchronous separator is respectively electrically connected with the analog front-end digital logic circuit; the analog front-end digital logic circuit is electrically connected with the input video signal switching interface;
and the ADC _ R, ADC _ G and the ADC _ B are used for receiving the VGA signal or Ypbpr signal, and the VGA signal or Ypbpr signal is processed by the analog front-end digital logic circuit and then is transmitted to the input video signal switching interface.
Further, the video zooming circuit comprises an image noise reduction module, a horizontal zooming module electrically connected with the image noise reduction module, an interleaving release module electrically connected with the horizontal zooming module, and a vertical video zooming module electrically connected with the interleaving release module;
the input video signal switching interface outputs data to the image noise reduction module, the image noise reduction module removes noise points aiming at characteristic points and sends the data to the horizontal zooming module, the horizontal zooming module zooms horizontal video, if the signal is Ypbpr signal, the staggered video display problem is solved through the staggered elimination circuit, then the vertical video zooming module zooms vertical video and sends the video to the image processing circuit.
Further, the image processing circuit comprises a sharpness adjusting module, a chrominance signal pressing module electrically connected with the sharpness adjusting module, an HSV chrominance space axis color adjusting module electrically connected with the chrominance signal pressing module, a black/white expansion module electrically connected with the HSV chrominance space axis color adjusting module, a contrast adjusting module electrically connected with the black/white expansion module, a YUV-to-RGB matrix converting module electrically connected with the contrast adjusting module, a RGB-to-RGB 3x3 matrix module electrically connected with the YUV-to-RGB matrix converting module, a color correction lookup table module electrically connected with the RGB-to-3 x3 matrix module, and a dithering operation module electrically connected with the color correction lookup table module;
the video zooming circuit is divided into two paths of data output paths after processing, one path of data output path is directly transmitted to a red-green-blue 3x3 matrix module, the other path of data output path is transmitted to a red-green-blue 3x3 matrix module after passing through a sharpness adjusting module, a chrominance signal pressing module, an HSV chrominance spatial axis color adjusting module, a black/white expanding module, a contrast adjusting module and a YUV-to-RGB matrix converting module and is converted into a data format ready to be output to a liquid crystal screen, and after color operation is overlapped with a color correction lookup table module, internal color operation bit pixels are reduced to 8-bit pixels suitable for output from 10 bits through a dithering operation module and are input to a TVOUT circuit for liquid crystal screen pixel format conversion, and the internal color operation bit pixels are converted into an LVDS format through a data corresponding table circuit and are output; the sound signal is output to the external sound power amplifier component by the I2S format.
Further, the computer system also comprises a ROM electrically connected with the CPU bus.
Further, the device also comprises a font screen display module electrically connected with the CPU bus.
Further, the device also comprises an ADC interface and a key which are electrically connected with the CPU bus, wherein the ADC interface is electrically connected with the key.
Further, the system also comprises a GPIO interface, a VIC interface, an I2C/UART interface and an SPI interface which are respectively and electrically connected with the CPU bus.
And further, the touch control device also comprises a second USB interface which is respectively electrically connected with the CPU bus and is used for being connected with the touch screen, a touch control signal of the touch screen is transmitted into the chip through the second USB interface or the I2C/UART interface or the SPI interface, and is transmitted back to the signal source main control end from the first USB interface for inverse control after being processed by the CPU in the chip.
The invention has the following advantages: the USB interface is additionally arranged, so that after the mobile phone, the desktop computer, the notebook computer and the television box are connected to the liquid crystal display chip through the USB interface and a driving program, pictures displayed by terminal equipment such as the mobile phone, the desktop computer, the notebook computer and the television box can be copied or desktop display can be expanded. Besides video and sound display, the method also supports the reverse control of the touch signals through the USB interface, and solves the problem that the touch signals cannot return to a signal source main control end (the signal source main control end refers to video source equipment such as a mobile phone, a desktop computer, a notebook computer and the like) through the HDMI/VGA interface. Meanwhile, the invention is also provided with an HDMI and VGA display interface, and can input and display video data through the HDMI and VGA display interface. The invention reduces the design and product production cost and increases the universality of the product.
Drawings
FIG. 1 is a schematic block diagram of the present embodiment;
FIG. 2 is a schematic diagram of an embodiment of a circuit path of an internal USB video display of a chip;
FIG. 3 is a second schematic diagram of the internal USB video display circuit path of the chip according to the present embodiment;
FIG. 4 is a schematic diagram illustrating the reverse control of the touch signal through the USB interface in the present embodiment;
in the figure: 1. a first USB interface, 2, a CPU bus, 3, an ADC interface, 4, a key, 5, an SPI interface, 6, an I2C/UART interface, 7, a second USB interface, 8, a GPIO interface, 9, a VIC interface, 10, a DDR2 memory interface, 11, a RAW/JPEG format decoder, 12, an SRAM, 13, a DMA, 14, a CPU, 15, a ROM, 16, a font screen display module, 17, a timer, 18, an SOG composite sync separator, 19, an ADC _ R, 20, an ADC _ G, 21, an ADC _ B, 22, an audio HDMI, 23, a TMDS RX PHY interface, 24, an HDMI digital logic circuit, 25, an input video signal switching interface, 26, a video scaling circuit, 27, an image processing circuit, 28, a data correspondence table circuit, 29, an out circuit;
the dotted lines in fig. 2 to 3 indicate the flow direction of the signals.
Detailed Description
The invention will be further explained with reference to the drawings.
Referring to fig. 1, in the present embodiment, a liquid crystal display chip includes a video scaling circuit 26, an image processing circuit 27 electrically connected to the video scaling circuit 26, a TVOUT circuit 29 electrically connected to the image processing circuit 27, and a data mapping table circuit 28 electrically connected to the TVOUT circuit 29. The liquid crystal display chip further comprises a first USB interface 1, a CPU bus 2, a RAW/JPEG format decoder 11, an SRAM (static random access memory) 12, a DMA13 (memory access), a CPU (central processing unit) 14, a timer 17 and a DDR2 (random access memory) memory interface. The first USB interface 1, the RAW/JPEG format decoder 11, the SRAM12, the DMA13, the CPU14, the timer 17 and the DDR2 memory interface 10 are respectively electrically connected with the CPU bus 2.
The working principle is as follows:
referring to fig. 3, the first USB interface 1 is configured to receive a digital signal USB input video signal, and temporarily store the related data in a DDR2 memory connected to the DDR2 memory interface 10 through a DMA13, the RAW/JPEG format decoder 11 will fetch the related data from the DDR2 memory through a DMA13 and decode the data into a correct image format according to the clock required by each Frame of the video scaler 26, temporarily store the data in a Frame buffer and store the data in the DDR2 memory through a DMA13, and input the decoded data to the video scaler 26 through a DMA13 for processing.
Referring to fig. 2, or the first USB interface 1 is configured to receive a digital signal USB input video signal, and temporarily store the related data in a DDR2 memory connected to the DDR2 memory interface 10 through a DMA13, the RAW/JPEG format decoder 11 will take out the related data from the DDR2 memory through a DMA13 according to the clock required by each frame of the video scaler 26, decode the data into a correct image format, and input the decoded data to the video scaler 26 for processing; the DDR bandwidth can be greatly saved.
After the mobile phone, the desktop computer and the notebook computer are connected to the liquid crystal display chip through the USB interface and the driving program, pictures displayed on the mobile phone, the desktop computer and the notebook computer can be copied or desktop display can be expanded.
Referring to fig. 1, in this embodiment, the liquid crystal display chip further includes a TMDS (transition minimized differential signaling) RX (receive) PHY (i.e., port physical layer) interface 23, an HDMI audio phase-locked loop 22, and an HDMI digital logic circuit 24, where the TMDS RX PHY interface 23 and the HDMI audio phase-locked loop 22 are respectively electrically connected to the HDMI digital logic circuit 24, and the HDMI digital logic circuit 24 is electrically connected to the input video signal switching interface 25. The TMDS RX PHY interface 23 is configured to receive a digital signal HDMI input video signal, and the digital signal is processed by an HDMI digital logic circuit and then transmitted to the input video signal switching interface.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip further includes ADC _ B21 (ADC represents an analog-to-digital converter, and B represents blue), ADC _ G20 (ADC represents an analog-to-digital converter, and G represents green), ADC _ R19 (ADC represents an analog-to-digital converter, and R represents red), an SOG composite sync separator 18, and an analog front-end digital logic circuit 30, where DC _ B, ADC _ G20, ADC _ R19, and the SOG composite sync separator 18 are electrically connected to the analog front-end digital logic circuit 30, respectively; the analog front-end digital logic circuit 30 is electrically connected to the input video signal switching interface 25. The ADC _ R19, ADC _ G20 and ADC _ B21 are configured to receive VGA signals or ypbppr signals, and send the VGA signals or Ypbpr signals to the input video signal switching interface after being processed by the analog front-end digital logic circuit 30.
Referring to fig. 1, in the present embodiment, the input video signal switching interface 25 automatically determines by the system or selects by the user that the video signal is from VGA, HDMI or USB, and switches the input video signal to the video scaling circuit 26 and the image processing circuit 27 by the present circuit.
Referring to fig. 1, in the present embodiment, the video scaling circuit 26 includes an image noise reduction module, a horizontal scaling module electrically connected to the image noise reduction module, an interlace removing module electrically connected to the horizontal scaling module, and a vertical video scaling module electrically connected to the interlace removing module. The input video signal switching interface 25 outputs data to the image noise reduction module, the image noise reduction module removes noise points for characteristic points and sends the noise points to the horizontal scaling module, the horizontal scaling module performs horizontal video scaling, and a maximum pixel (pixel)1920 point is amplified, if the signal is a Ypbpr signal, the interlaced video display problem is solved through the interlace elimination circuit, then the vertical video scaling module performs vertical video scaling processing and sends the processed signal to the image processing circuit 27, and the maximum pixel 1080 point is amplified. .
Referring to fig. 1, in this embodiment, the image processing circuit 27 includes a sharpness adjustment module, a chrominance signal suppression module electrically connected to the sharpness adjustment module, an HSV chrominance spatial axis color adjustment module electrically connected to the chrominance signal suppression module, a black/white expansion module electrically connected to the HSV chrominance spatial axis color adjustment module, a contrast adjustment module electrically connected to the black/white expansion module, a YUV-to-RGB matrix conversion module electrically connected to the contrast adjustment module, a RGB-to-RGB 3x3 matrix module electrically connected to the YUV-to-RGB matrix conversion module, a color correction lookup table module electrically connected to the RGB-to-RGB 3x3 matrix module, and a dithering operation module electrically connected to the color correction lookup table module. The video zooming circuit 26 is divided into two paths of data output paths after processing, one path of data output path is directly transmitted to a red-green-blue 3x3 matrix module, the other path of data output path is transmitted to a red-green-blue 3x3 matrix module after passing through a sharpness adjusting module, a chrominance signal pressing module, an HSV chrominance spatial axis color adjusting module, a black/white expanding module, a contrast adjusting module and a YUV-to-RGB matrix converting module and then is converted into a data format ready to be output to a liquid crystal screen, and after overlapping color operation with a color correction lookup table module, internal color operation bit pixels are reduced to 8-bit pixels suitable for output from 10 bits through a dithering operation module and are input to a TVOUT circuit for liquid crystal screen pixel format conversion, and the internal color operation bit pixels are converted into an LVDS format through a data corresponding table circuit 28 and output; the sound signal is output to the external sound power amplifier component by the I2S format.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip further includes a ROM15 electrically connected to the CPU bus 2.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip further includes a font screen display module 16 electrically connected to the CPU bus 2. The font screen display module is an interactive interface storage buffer area with a user, the user obtains an LCD parameter adjustment target by the user through a key, an I2C/UART interface, a second USB interface and a GPIO interface, and the adjustment result is fed back to the operation result of the user through characters, scroll bars and the like while the adjustment target is executed.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip further includes an ADC interface (analog-to-digital converter interface) 3 electrically connected to the CPU bus 2 and a key 4, where the ADC interface 3 is electrically connected to the key 4. The ADC interface 3 and the key 4 correspond the data converted by the ADC to the key list.
Referring to fig. 1, in the embodiment, the liquid crystal display chip further includes a GPIO interface 8, a VIC interface 9, an I2C/UART interface 6, and an SPI interface 5, which are electrically connected to the CPU bus 2, respectively; multiple interfaces are provided for accessing devices of different interfaces.
As shown in fig. 1 and 4, in this embodiment, the liquid crystal display chip further includes a second USB interface 7 electrically connected to the CPU bus 2, and is configured to be connected to the touch screen, where a touch signal of the touch screen is transmitted to the chip through the second USB interface 7 or the I2C/UART interface 6 or the SPI interface 5, and is processed by the CPU14 in the chip, and then is transmitted back to the signal source main control terminal (the signal source main control terminal refers to a mobile phone, a desktop computer, a notebook, or other video source device) from the first USB interface for performing inverse control.
In fig. 1, BAIN represents a blue analog input; PB1 denotes the blue progressive signal; GAIN represents green analog input; y1 denotes a luminance signal; RAIN represents the red analog input, PR1 represents the red progressive signal; SOG indicates that Sync (synchronization) signals are added to G of RGB in the VGA signals; SOY1 indicates that a Sync signal is added to a luminance signal; HDMI IN represents HDMI signal input; SAR AIN represents the input of an analog signal to a successive approximation analog-to-digital converter.
Claims (10)
1. A liquid crystal display chip comprises a video zooming circuit (26), an image processing circuit (27) electrically connected with the video zooming circuit (26), a TVOUT circuit (29) electrically connected with the image processing circuit (27), and a data corresponding table circuit (28) electrically connected with the TVOUT circuit (29); the method is characterized in that: the device comprises a first USB interface (1), a CPU bus (2), a RAW/JPEG format decoder (11), an SRAM (12), a DMA (13), a CPU (14), a timer (17) and a DDR2 memory interface (10);
the first USB interface (1), the RAW/JPEG format decoder (11), the SRAM (12), the DMA (13), the CPU (14), the timer (17) and the DDR2 memory interface (10) are respectively and electrically connected with a CPU bus (2);
the first USB interface (1) is used for receiving a digital signal USB input video signal, temporarily storing related data in a DDR2 memory connected with a DDR2 memory interface (10) through a DMA (13), decoding the related data into a correct image format after taking out the related data from the DDR2 memory through the DMA (13) according to a clock pulse required by each Frame of a video scaling circuit (26), temporarily storing the data in a Frame buffer area, storing the data in the DDR2 memory through the DMA (13), and inputting the decoded data to the video scaling circuit (26) through the DMA (13) for processing;
or the first USB interface (1) is used for receiving a digital signal USB input video signal, and temporarily storing related data in a DDR2 memory connected with a DDR2 memory interface (10) through a DMA (13), and a RAW/JPEG format decoder (11) takes out the related data from the DDR2 memory through the DMA (13) according to a clock pulse required by each frame of a video scaling circuit (26), decodes the related data into a correct image format and inputs the decoded data to the video scaling circuit (26) for processing.
2. The liquid crystal display chip of claim 1, wherein: the device is characterized by further comprising a TMDS RX PHY interface (23), an HDMI audio phase-locked loop (22) and an HDMI digital logic circuit (24), wherein the TMDS RX PHY interface (23) and the HDMI audio phase-locked loop (22) are respectively and electrically connected with the HDMI digital logic circuit (24), and the HDMI digital logic circuit (24) is electrically connected with an input video signal switching interface (25);
the TMDS RX PHY interface (23) is used for receiving a digital signal HDMI input video signal, and the digital signal HDMI input video signal is processed by an HDMI digital logic circuit (24) and then is transmitted to an input video signal switching interface (25).
3. The liquid crystal display chip according to claim 1 or 2, characterized in that: the system also comprises an ADC _ B (21), an ADC _ G (20), an ADC _ R (19), an SOG composite synchronous separator (18) and an analog front-end digital logic circuit (30), wherein the DC _ B, ADC _ G (20), the ADC _ R (19) and the SOG composite synchronous separator (18) are respectively and electrically connected with the analog front-end digital logic circuit (30); the analog front-end digital logic circuit (30) is electrically connected with the input video signal switching interface (25);
and the ADC _ R (19), the ADC _ G (20) and the ADC _ B (21) are used for receiving VGA (video graphics array) signals or Ypbpr signals, and the VGA signals or Ypbpr signals are arranged by an analog front-end digital logic circuit (30) and then are conveyed to an input video signal switching interface (25).
4. The liquid crystal display chip of claim 3, wherein: the video zooming circuit (26) comprises an image noise reduction module, a horizontal zooming module electrically connected with the image noise reduction module, an interleaving release module electrically connected with the horizontal zooming module, and a vertical video zooming module electrically connected with the interleaving release module;
the input video signal switching interface (25) outputs data to the image noise reduction module, the image noise reduction module removes noise points aiming at characteristic points and sends the data to the horizontal zooming module, the horizontal zooming module zooms horizontal video, if the signal is Ypbpr signal, the staggered video display problem is solved through the staggered elimination circuit, then the vertical video zooming module zooms vertical video and sends the processed vertical video to the image processing circuit (27).
5. The liquid crystal display chip of claim 1, 2 or 4, wherein: the image processing circuit (27) comprises a sharpness adjusting module, a chrominance signal pressing module electrically connected with the sharpness adjusting module, an HSV chrominance space axis color adjusting module electrically connected with the chrominance signal pressing module, a black/white expansion module electrically connected with the HSV chrominance space axis color adjusting module, a contrast adjusting module electrically connected with the black/white expansion module, a YUV-to-RGB matrix converting module electrically connected with the contrast adjusting module, a red-green-blue 3x3 matrix module electrically connected with the YUV-to-RGB matrix converting module, a color correction lookup table module electrically connected with the red-green-blue 3x3 matrix module and a dithering operation module electrically connected with the color correction lookup table module;
the video zooming circuit (26) is processed and then divided into two paths of data output paths, one path of data output path is directly transmitted to a red, green and blue 3x3 matrix module, the other path of data output path is transmitted to a red, green and blue 3x3 matrix module to be converted into a data format ready to be output to a liquid crystal screen after passing through a sharpness adjusting module, a chrominance signal pressing module, an HSV chrominance spatial axis color adjusting module, a black/white expanding module, a contrast adjusting module and a YUV-to-RGB matrix converting module, and internal color operation bit pixels are reduced to 8-bit pixels suitable for output from 10 bits through a dithering operation module after overlapping color operation with a color correction lookup table module, and are input to a TVOUT circuit to be subjected to liquid crystal screen pixel format conversion, and are converted into an LVDS format through a data corresponding table circuit (28) and output, so that video output; the sound signal is output to the external sound power amplifier component by the I2S format.
6. The liquid crystal display chip of claim 5, wherein: and a ROM (15) electrically connected to the CPU bus (2).
7. The liquid crystal display chip of claim 1, 2, 4 or 6, wherein: and the font screen display module (16) is electrically connected with the CPU bus (2).
8. The liquid crystal display chip of claim 7, wherein: the CPU interface circuit also comprises an ADC interface (3) and a key (4), wherein the ADC interface (3) is electrically connected with the CPU bus (2), and the ADC interface (3) is electrically connected with the key (4).
9. The liquid crystal display chip of claim 1, 2, 4, 6, or 8, wherein: the CPU bus also comprises a GPIO interface (8), a VIC interface (9), an I2C/UART interface (6) and an SPI interface (5) which are respectively and electrically connected with the CPU bus (2).
10. The liquid crystal display chip of claim 9, wherein: the touch control circuit further comprises a second USB interface (7) which is electrically connected with the CPU bus (2) respectively and used for being connected with the touch screen, touch control signals of the touch screen are transmitted into the chip through the second USB interface (7) or the I2C/UART interface (6) or the SPI interface (5), and are transmitted back to the signal source main control end from the first USB interface for inverse control after being processed through the CPU (14) in the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010539545.5A CN111554248A (en) | 2020-06-15 | 2020-06-15 | Liquid crystal display chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010539545.5A CN111554248A (en) | 2020-06-15 | 2020-06-15 | Liquid crystal display chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113270920A (en) * | 2021-05-26 | 2021-08-17 | 深圳市昱森微电子有限公司 | Power supply charging management chip |
| CN113419979A (en) * | 2021-05-26 | 2021-09-21 | 深圳市昱森微电子有限公司 | USB multimedia concentrator control chip |
-
2020
- 2020-06-15 CN CN202010539545.5A patent/CN111554248A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113270920A (en) * | 2021-05-26 | 2021-08-17 | 深圳市昱森微电子有限公司 | Power supply charging management chip |
| CN113419979A (en) * | 2021-05-26 | 2021-09-21 | 深圳市昱森微电子有限公司 | USB multimedia concentrator control chip |
| CN113270920B (en) * | 2021-05-26 | 2022-04-29 | 深圳市昱森微电子有限公司 | Power supply charging management chip |
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