JPH0754912B2 - Digital modulator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator for generating a digital modulation signal capable of reducing an error at a high transmission rate even in a band-limited transmission line.

Configuration of Conventional Example and Problems Thereof The recording density of a digital signal recording / reproducing apparatus is increasing year by year, and the improvement of the digital modulation method also contributes to it. Generally, the following characteristics are desired for a digital modulation system.

(I) The minimum inversion interval (hereinafter referred to as Tmin) is large.

(Ii) The maximum inversion interval (hereinafter referred to as Tmax) is small.

(Iii) There are few low frequency components.

(Iv) The detection window frame is large.

By the above (i), the high frequency spectrum of the digital modulation signal can be reduced, and thereby the upper limit of the transmission band can be lowered. Further, the above (ii) enables self-clocking, which reduces the timing difference between the clock and the signal and contributes to the improvement of the recording density. Further, due to the above (iii), low-frequency noise can be removed, and in an optical information recording / reproducing apparatus or the like that needs to track an information track, a digital modulation signal is mixed as noise in a tracking control signal. You can prevent it. Also, above (iv)
Can increase the jitter margin against intersymbol interference and the like, which also contributes to the improvement of recording density.

Conventionally, in order to improve these characteristics, an N (N is an integer of 2 or more) bit information word is converted into an M (M is an integer larger than N) bit code word, and a connection part of the code word is further operated. This suppresses low frequency components and Tmax
A modulation method for reducing the has already been proposed.

A conventional digital modulator will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a conventional digital modulator, 1 is a conversion means, 2 is a connection processing means,
3 is an accumulating means, 4 is a serializing means, and 5 is a synchronizing signal generating means.

The operation of the digital modulator configured as described above will be described below. The conversion means 1 inputs an N-bit information word (I), converts it into an M-bit code word, and inputs it to the serialization means 4. The serializing means 4 converts the code word and the synchronizing signal output from the synchronizing signal generating means 5 at a constant cycle into a time series signal and outputs it as a digital modulation signal (S). The accumulating means 3 counts forward or backward for each bit of the digital modulation signal. The digital modulation signal counts forward in one state bit and counts backward in the other state. Therefore, the connection processing means 2 uses the count value of the accumulating means 3 and the serializing means 4
The code word or sync signal input to the first code word is output so as to reduce the absolute value of the cumulative value, that is, the portion output as a time-series signal, that is, 1 bit connected to the preceding code word. Alternatively, the value of several bits is adjusted. However, when the state inversion interval becomes smaller than a predetermined Tmin or becomes larger than a predetermined Tmax due to the connection of code words, the state inversion interval is set to a predetermined range in preference to the above cumulative value control. Adjust the codeword connections. By doing so, the low frequency component of the digital modulation signal can be suppressed, the state inversion interval can be limited to a predetermined range, and the band of the transmission path can be narrowed. As a specific example of such a modulator, an EFM modulator used in a recording device for a compact disc (Philips, registered trademark of Sony Corporation) is known. E
The FM modulator converts 8-bit information words into 14-bit code words and connects the code words with 3-bit connection bits. However, since the 8-bit information word is converted into a 17-bit code word when the connection bits are included, the detection window frame is narrowed by about 6% as compared with MFM modulation, for example. Also, when demodulating a signal digitally modulated by this modulator, the number of bits in the code word is large, so a fairly complicated logic circuit or a large capacity is required.
There was also a problem that it required a ROM table. Further, in order to solve these problems, there has been a problem that the suppression of the low frequency component becomes insufficient if the number of bits of the information word and the code word are both reduced.

OBJECT OF THE INVENTION The object of the present invention is to solve the above-mentioned problems of the conventional digital modulator and to sufficiently suppress low frequency components after digital modulation, and further to have a large minimum inversion interval, The object is to provide a digital modulator that is easy to demodulate.

Configuration of the Invention The digital modulator of the present invention is N (N is an integer of 2 or more)
A conversion means for delaying and outputting an M (integer larger than N) bit code word obtained by converting an information word to be modulated, and converting the code word into a time-series signal as a digital modulation signal. It has serializing means for outputting and accumulating means for accumulating the difference between the number of bits in one state and the number of bits in the other state of the digital modulated signal to obtain an accumulated value, and the converting means is a bit of a code word. When "1" is associated with the state inversion of the digital modulation signal and bit "0" of the codeword is associated with the state inversion of the digital modulation signal, most of the information words are in one-to-one correspondence with one type of codeword. Corresponding to the remaining at least one type of specific information word, a plurality of code words including an odd number and an even number of bits “1” included in the code word Specific information that can be converted to any of Conversion is suspended when is input, and at the time when the next information word that can be converted into a plurality of code words is input, the absolute value of this cumulative value becomes smaller based on the cumulative value output by the accumulating means. In addition, it is configured to select the code word corresponding to the above-mentioned specific information word that is held, and by this, the low frequency component of the digital modulation signal can be suppressed with a simple structure, and the minimum inversion It is also possible to use code words that lengthen the interval.

Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a digital modulator according to an embodiment of the present invention. In FIG. 2, 11 is N / M
Converter, 12 DSV evaluation means, 13 selection means, 14 storage means, 15 connection processing means, 16 serialization means, 17a and 17b
Are the first and second accumulating means, respectively, and are N / M converters 11,
The DSV evaluation means 12, the selection means 13, the storage means 14 and the connection processing means 15 constitute the conversion means 10, and the first accumulating means 17a and the second accumulating means 17b constitute the accumulating means 17, respectively.

The operation of the digital modulator having the above structure according to this embodiment will be described below. The N / M converter 11 converts an information word (I) of N (N is an integer of 2 or more) bits into M (M
Is an integer larger than N) and is converted into a code word of bit, and the bit "0" and the bit "1" of the code word are not inverted and there is state inversion of the digital modulation signal output from this digital modulator, respectively. , The code word is configured such that there is always a predetermined number or more of bits “0” between the bits “1” and “1”.
Codewords have a one-to-one correspondence with most of the information words except a specific information word, and with respect to the information words having the above characteristics, the codewords in which the number of bit "1" is odd and even Two codewords of a word correspond. When converting the specific information word, the M / N converter 11 tentatively replaces one of the plurality of code words corresponding to this code word or another code not included in the code word. Tentatively converted to this as a codeword. Such an N / M converter 11 can be easily realized by a combinational circuit or a ROM table. The synchronizing signal generating means 5 periodically includes a synchronizing signal in the code word string output from the N / M converter 11. The connection processing means 15, when the code word string including the synchronization signal is a time-series signal, the connection between the code word and the code word, or between the bit “1” and the bit “1” at the connection portion of the code word and the synchronization signal. The connection is processed so that the number of bits "0" does not become smaller than a predetermined number. The code word thus connected is stored in the storage means 14
Is temporarily stored in. Since the storage means 14 outputs the stored codewords in order from the oldest, the conversion means 10 delays and outputs the codewords. The serializing means 16 NRZI-modulates the code word output from the converting means 10 as a serial signal and outputs it as a digital modulated signal (S). On the other hand, the first and second accumulating means 17a, 17b are for accumulating the difference between the number of bits in one state and the number of bits in the other state (hereinafter referred to as DSV) of the digitally modulated signal, and are serialized. Prior to the digital modulation signal output from the means 16,
The DSV up to the codeword being stored in the storage means 14 is obtained in advance. When the provisional codeword is stored in the storage means 14, the DSV on the assumption that the corresponding information word is converted into one codeword is accumulated by the first accumulating means 17a, and the other is accumulated. The second accumulation means 17b accumulates the DSVs on the assumption that they have been converted into the codewords. When the above provisional codeword is about to be read from the storage means 14, or the next provisional codeword or code is newly stored in the storage means 14.
DSV evaluating means 12 compares the absolute value of the DSV of the first accumulating means 17a with the absolute value of the DSV of the second accumulating means 17b and the selecting means 13 based on the comparison result. Replaces the temporary codeword already stored in the storage means 14 with the codeword corresponding to the DSV having the smaller absolute value. At this time, the first or second accumulating means 17a, 17b
The smaller absolute value of DSV by is copied to the other accumulating means. By doing so, the DSV is controlled so that the absolute value is always small, and thus the low frequency component of the digital modulation signal is suppressed. The synchronizing signal generating means 5 is not limited to the position of this embodiment, and particularly when the value of the DSV of only the synchronizing signal is zero, the synchronizing signal generating means 5 may be placed later. Further, although the storage means 14 is configured to store the code word, it is also possible to store the information word before conversion, and in this case, the storage capacity of the storage means 14 can be reduced. Further, the accumulating means 17 outputs the DSV when it is assumed that the specific information word whose conversion is suspended is converted into one code word and the DSV when it is assumed that the specific information word is converted into the other code word, respectively. However, the DSVs up to and including the tentative codeword and the DSVs after the tentative codeword may be configured to be accumulated by different accumulating means.

Next, a specific conversion method of the N / M conversion means 11 will be described.

Table 1 is an example of the conversion table when N = 2 and M = 4. The information word is composed of 2 bits of [a ₁ , a ₀ ] in order from the upper bit, and the code word is [b ₃ , b ₂ , b ₁ ,
b ₀ ].

Here, there is always a bit "0" between the bit "1" and the bit "1" of the code word, and the least significant bit of the code word is always "0". However, there is always a bit "0" between the bit "1" and the bit "1". Therefore, if this is NRZI modulated, the minimum inversion interval (Tm
in) is equal to the 1-bit length (T) of the information word, and Tmin = T. There are 5 types of code words in total, and 4 information words.
Since it is a type, as shown in Table 1, for example, for information word [00], [*] in the table is associated with two types of code words of “0” and “1” The absolute value can be controlled to be small. Furthermore, if the code words are output in order from the upper bits when they are time-series signals, when both the bit b ₁ of the preceding code word and the bit b ₃ of the following code word are “0”, “0” The bit b _{0 in the} meantime may be either “0” or “1” as long as does not continue too much. In this case, the absolute value of DSV can be controlled to be small by the bit b ₀ . So a bit
When the DSV can be controlled by b ₀ , the N / M converter 11 uses the bit b ₀ as a provisional value as a connection adjustment bit, and the first, second
Based on the results of the accumulating means 17a, 17b and the DSV evaluating means 12, the connection processing means 15 later determines the connection adjustment bit b ₀ to an appropriate value as in the case of the selecting means 13 so that the DSV becomes small. do it. However, if bit "0" is too long between bit "1" and bit "1", Tmax can be limited to a predetermined value by setting the connection adjustment bit to "1" in preference to the above. .

Further, Table 2 is a conversion table of the N / M converter when N = 4 and M = 8. Here, the information word is composed of 4 bits [a ₃ , a ₂ , a ₁ , a ₀ ] in order from the upper bit, and the code word is [b ₇ , b ₆ , b ₅ , b ₄ , b _{3 in} order from the upper bit. , b ₂ , b ₁ , b ₀ ]. In this table, two or more bits "0" are always inserted between the bits "1" and "1" of the code word. When this code word is output as the time-series signal, the bits b ₁ of the preceding code word and the bit b ₇ of the following code word are both “1”.
In this case, if these are both set to “0” and the bit b ₀ between them is set to “1”, there are always two or more bits between the bit “1” and the bit “1” in time series. There is a bit "0" of Tmin = 1.5T. When converting an information word into a code word according to this table, three types of information words [0000], [0001] and [110]
The code word corresponding to [0] where [*] is written in the table may be "0" or "1", which are specific information words capable of controlling DSV. As described above, the bit b ₀ becomes “1” when both the bit b ₁ of the preceding codeword and the bit b ₇ of the subsequent codeword are “1”. On the contrary, when "" is detected, the preceding information word b ₁ and the following information word b ₇ are both returned to "1", so that the original information word can be surely demodulated. However, if either bit b ₃ of the preceding codeword or bit b ₅ of the following codeword is “1”, bit b ₁ of the preceding codeword and bit b ₇ of the following codeword are can not occur that as a "1" bit b ₀ therebetween in order to Tmin is not too small because unlikely that both become "1". Therefore, in that case, if b ₁ , b ₂ , b ₆ and b ₇ between b ₃ of the preceding codeword and b ₅ of the following codeword are all “0”, the bits between them Tm even if b ₀ is “1”
It can be distinguished from the case of adjusting in. Therefore, this bit b ₀ can be used for controlling the DSV as in the case of Table 1. Furthermore, Table 2 is devised so that the conversion and the reverse conversion between the information word and the code word are easy. That is, between all the information words except some exceptions (information word 0111) and the corresponding code words, the top two information words are included.
Bits (a ₃ , a ₂ ) and the upper 3 bits of the codeword (b ₇ , b ₆ , b ₅ )
And the lower 2 bits (a ₁ , a ₀ ) of the information word and the lower 3 bits (b ₃ , b ₂ , b ₁ ) of the code word have a one-to-one mapping relationship. Specifically, in this table (a ₃ , a ₂ or a ₁ ,
There is a correspondence relationship of 00 ← → 000 01 ← → 001 10 ← → 010 11 ← → 100 between a ₀ ) and (b ₇ , b ₆ , b ₅ or b ₃ , b ₂ , b ₁ ). Therefore, the logic circuit for converting between the information word and the code word at the time of modulation / demodulation can be simplified, and the conversion can be performed in a short time without necessarily requiring the ROM table. FIG. 3 is a circuit diagram showing a specific configuration of a 4/8 converter for converting a 4-bit information word into an 8-bit code word according to Table 2. In the figure, the bit b ₀ is tentatively always set to “0”, and is later converted into a final value by the connection processing means 12. Further, FIG. 4 shows a circuit for inversely converting a code word into an information word in accordance with Table 2. As described above, Table 2 is constructed so that conversion and inverse conversion at the time of modulation / demodulation can be performed extremely easily. Furthermore, a plurality of codewords corresponding to all specific information words have a predetermined bit (here, bit b ₄ ) corresponding to "0" and "1". This can be easily done when replacing such a codeword with a final codeword. In Table 2, bits a ₀ and a ₁ of the information word are bits b of the code word.
₁ , b ₂ , b ₃ into the information word bits a ₂ , a ₃ into the code word bits b ₅ , b
_{Although 6} and b ₇ are made to correspond to each other, this combination is not necessarily limited to this, and any other combination may be used.

Furthermore, Table 3 shows N / M when N = 4 and M = 8, similar to Table 2.
It is a conversion table of a converter. Also in this table, either "0" or "1" is selected for the bit marked with [*] of the code word.

This table is organized as follows. That is, the Hamming distance from the predetermined 4-bit value is 1 or less for the information word in which the bits b ₅ , b ₆ , and b ₇ of the code word correspond to the same code word. By doing so, the inverse conversion at the time of demodulation can be simplified. Specifically, the inverse conversion is performed as follows. First, a provisional information word is generated as shown in Table 4 for four kinds of possible values of the bits b ₅ , b ₆ , and b ₇ of the code word, and when b _{1 of} the code word is “1” By reversing a ₀ , a ₁ when b ₂ is “1”, and a ₂ when b ₃ is “1”, respectively, it is possible to easily reverse-convert into an information word as shown in Table 3. However, when b ₁ , b ₄ and b ₇ are all “1”, as an exception, (a ₃ , a ₂ , a ₁ , a ₀ ) is converted back to (0,0,1,1).

As described above, according to the present invention, it is possible to obtain a digital modulated signal with a low frequency component less than a normal information word sequence. However, when the same information word is repeated,
When DSV control cannot be performed, low frequency components may not be suppressed continuously.

FIG. 5 is a block diagram of a digital modulator according to another embodiment of the present invention which solves the above-mentioned drawbacks. In FIG. 5, 20 is a scramble means. The operation of the digital modulator of this embodiment constructed as above will be described below. First, the scramble means 20 disturbs the input information word (I) according to a certain promise. The scramble means 20 can be easily realized by, for example, taking an exclusive OR for each bit and a random number sequence that circulates in synchronization with the synchronization signal. Below is the second
Similar to the illustrated embodiment, the information word disturbed by the scramble means 20 is digitally modulated. In the digital modulation signal thus obtained, the original information word can be easily obtained by performing the inverse conversion at the time of modulation using a random number sequence that circulates in synchronization with the synchronization signal. In addition,
In the above-mentioned embodiment, the scramble means 20 takes the exclusive OR for each bit with the random number sequence and the information word which circulate in synchronization with the synchronizing signal, but the scramble means 20 is not limited to such a configuration. Instead, any other means such as addition between a random number and an information word may be used in principle.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention provides an M (integer larger than N) bit codeword obtained by converting an N (N is an integer of 2 or more) bit information word to be modulated. Delaying means for delaying and outputting, serializing means for converting the code word into a time series signal and outputting it as a digital modulation signal, and a bit in one state of the digital modulation signal being "0" and a bit in the other state. When the bit is "1", the conversion means has an accumulating means for accumulating the difference between the number of the bit "0" and the number of the bit "1", and the converting means has the bit "1" of the code word. When the state of the digital modulated signal is inverted and the bit "0" of the code word is associated with the state of the digital modulated signal is not inverted, one type of code word is made to correspond to each information word in most one-to-one correspondence. , A codeword for the remaining at least one specific information word Corresponds to multiple code words including odd and even number of bit "1" included in, and suspends conversion when a specific information word that can be converted to any of the multiple code words is input Then, at the time when the next information word that can be converted into a plurality of code words is input, at the time when this cumulative value is obtained such that the absolute value of this cumulative value becomes small based on the cumulative value output by the above accumulating means. The code word corresponding to the specific information word preceding is selected, and the bit "1" is not output consecutively including the connection part when the code words are arranged in series. The excellent effect that the minimum inversion interval of the digital modulated signal is large and the low frequency component can be suppressed is obtained.

Further, the converting means converts an information word of 4 bits into an 8-bit code word when the bit "1" and the bit "0" of the code word are associated with the presence or absence of state inversion of the digital modulation signal, respectively. To do.

ii. When a codeword includes a plurality of bits "1", it always includes two or more bits "0".

iii. At least one type of information word corresponds to two types of codewords whose bit at a specific position is "0" and "1", and one of them is selected and converted.

iv. The most significant bit or the least significant bit of the code word is normally set to "0" as a connection adjustment bit, and when the code word string is a time series signal, both sides of the connection adjustment bit are bit "1".
If both of these bits are "0", the connection adjustment bit is "1", and the two bits "0" are adjacent to both sides of the connection adjustment bit, and the third position before and after the connection adjustment bit. If at least one of the two bits to be set is "1", the value of the connection adjustment bit is determined based on the cumulative value.

With this configuration, the minimum inversion interval can be further increased, and bit “1” and bit “0” of the code word can be further increased.
When the digital modulation signal is associated with the state inversion and without the state inversion, the codewords corresponding to the information words whose two bits in the predetermined position have the same value are all in the predetermined position except for a decimal exception. When 3 bits have a constant value, or when bit "1" and bit "0" of the code word are made to correspond to the digital modulation signal with state inversion and without state inversion, respectively, the three bits at a predetermined position have the same value. With the exception of a few exceptions, all the information words corresponding to the code words having the value of ## EQU1 ## have a Hamming distance of 1 or less with respect to a predetermined value of 4 bits determined by the value of 3 bits. The effect that the configuration can be simplified is obtained.

Further, the synchronizing signal generating means for including the synchronizing signal in the digital modulation signal at a constant cycle, and the scrambling means for performing a predetermined calculation between the N-bit random number circulating in synchronization with the synchronizing signal and the input information word. And by converting the information word disturbed by the scramble means into a code word by the conversion means, the low frequency component of the digital conversion signal can be reliably ensured even when the same information word continues. The effect that it can be suppressed is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional digital modulator, FIG. 2 is a block diagram of a digital modulator in one embodiment of the present invention, FIG. 3 is a circuit diagram of a part of the digital modulator in the above embodiment, and FIG. FIG. 5 is a circuit diagram of a part of a digital demodulator for demodulating a digital modulation signal by the digital modulator in the above embodiment, and FIG. 5 is a block diagram of a digital modulator in another embodiment of the present invention. 10 ... conversion means, 11 ... N / M converter, 12 ... DSV evaluation means, 13 ... selection means, 14 ... storage means, 15 ... connection processing means, 16 ... serialization means, 17 ... ... accumulation means, 17a ... first accumulation means, 17b ... second accumulation means, 20 ... scramble means.

Claims (5)

[Claims] 1. A conversion means for delaying and outputting an M (M is an integer larger than N) bit code word obtained by converting an input N (N is an integer of 2 or more) bit information word. , Serializing means for converting the code word into a time-series signal and outputting it as a digital modulation signal, and accumulating the difference between the number of bits in one state of the digital modulation signal and the number of bits in the other state to obtain a cumulative value. And accumulating means for obtaining the bit "1" of the code word with the state inversion of the digital modulation signal,
When the bit “0” of the code word is made to correspond to the digital modulation signal without state inversion, the conversion means determines that the number of bits “1” included in the code word is at least one specific information word. Corresponding a plurality of code words including odd ones and even ones, and corresponding one-to-one code words to the remaining information words respectively, there is a specific information word that can be converted to any of the plurality of code words. Conversion is suspended when input, and the specific information word is suspended so that the absolute value of the cumulative value by the accumulating means becomes small at the time when the next information word that can be converted into a plurality of code words is input. A digital modulator characterized by selecting a code word corresponding to. 2. When the bit "1" and the bit "0" of the code word correspond to the digital modulation signal with state inversion and without state inversion, respectively, the conversion means substantially satisfies all of the following items. The digital modulator according to claim (1), which is equivalent to: i. Convert 4-bit information word to 8-bit code word. ii. When a code word includes a plurality of bits "1", it always includes two or more bits "0". iii. At least one type of information word corresponds to two types of codewords whose bit at a specific position is "0" and "1", and one of them is selected and converted. iv. The most significant bit or the least significant bit of the code word is normally set to "0" as a connection adjustment bit, and when the code word string is a time-series signal, both sides of the connection adjustment bit become "1". Bits on both sides are set to "0", the connection adjustment bit is set to "1", two bits "0" are adjacent on both sides of the connection adjustment bit, and two bits are located third before and after the connection adjustment bit. If at least one of these bits is "1", the value of the connection adjustment bit is determined based on the cumulative value. 3. When the bit "1" and the bit "0" of the code word are made to correspond to the presence and absence of the state inversion of the digital modulation signal, respectively, two bits at a predetermined position correspond to the information word having the same value. The digital modulator according to claim (2), wherein all the code words to be generated have the same value in 3 bits at a predetermined position with a few exceptions. 4. When the bit "1" and the bit "0" of the code word are made to correspond to the presence and absence of state inversion of the digital modulation signal, respectively, 3 bits at a predetermined position correspond to the code word having the same value. All the information words to be used have a Hamming distance of 1 or less with respect to a predetermined value of 4 bits determined by the value of 3 bits, with a few exceptions. The described digital modulator. 5. A predetermined operation between a sync signal generating means for including a sync signal in a digital modulation signal at a constant cycle, and an N-bit random number circulating in synchronization with the sync signal and an input information word. The digital modulator according to claim 1, further comprising a scrambling means for performing the above, wherein the information word disturbed by the scrambling means is converted into a code word by the converting means.