JPH05325425A - Code detecting device - Google Patents

Abstract

PURPOSE:To provide the code detecting device by which the same detection characteristic as a PR (1, 0, -1) system is obtained by using an NRZI system without using a pre-code circuit. CONSTITUTION:In a magnetic recording/reproducing part 2, a reproducing signal which passes through a system of a transmission function 1-D is obtained. Subsequently, in an addition processing part 3, an addition processing to a signal whose transmission function is shown by 1+D and which is delayed by one bit is executed in the same way as the PR (1, 0, -1) system, and it becomes a detecting point. In a demodulating part 4, a signal digitized in the detecting point is divided into an even number sequence and an odd number sequence, and integration is executed in the respective sequences. When integral signals of both these sequences are subjected to MOD2 addition, the transmission function of the demodulating part 4 becomes (1+D)/(1-D<2>). In this case, as for the transmission function by the MOD2 addition, since 1-D and 1+D are equal, the transmission function of the demodulating part 4 becomes 1/(1+D), a transmission function 1 is obtained as a whole, and an input signal can be demodulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code detecting device used for demodulating digital data, and more particularly to NR.
ZI (Non-Return to Zero Inv)
The present invention relates to a code detection device that demodulates a signal that is modulated and recorded.

[0002]

2. Description of the Related Art Conventionally, digital data is generally NR
PR is used as a method for detecting a signal recorded by ZI modulation.
There are partial response methods such as the (1, -1) method and the PR (1,1) method, and their contents are, for example, an introduction to magnetic recording technology (Katsuya Yokoyama, Sogo Denshi Shuppan, 1988 first edition).
Is disclosed in.

The PR (1, -1) method will be described with reference to FIG. The input data a is modulated and recorded by the NRZI conversion circuit whose transfer function as shown in FIG. 13 can be represented by 1 / (1-D). At this time, the signal is 1
Is inverted at 0 and non-inverted at 0 (record signal b). Here, D is a 1-bit delay circuit.

In the case of magnetic recording, the reproduction signal has a transfer function of 1
It has a differential characteristic of -D, and the transfer function becomes 1 as a whole (reproduction signal c). The sign is detected as a ternary value, and when the reproduction signal c exceeds the threshold value on the plus side and exceeds the threshold value on the minus side, the comparator output d which becomes 1 is input by latching with the reproduction clock e. Demodulate the data.

The PR (1,1) method will be described with reference to FIG. The input data a is NRZI-modulated and recorded and reproduced as in the PR (1, -1) system. At this point, the transfer function is 1 as in the PR (1, -1) system.
However, the following processing is performed in order to shift the peak of the spectrum at the detection point to the low range. The reproduced signal c passes through an integrating circuit whose transfer function is represented by 1 / (1-D), and a direct current component is reproduced (integrated signal d). By passing the integrated signal d through a delay circuit for 1 bit, the transfer function becomes D / (1-D)
A 1-bit delayed signal e is obtained. Integrated signal d and 1
The addition signal f is obtained by adding the bit delay signal e, and the overall transfer function at this point is (1 + D) /
(1-D).

Here, the comparator output g is obtained by performing the comparator so that it becomes 1 only when the addition signal f is between the threshold value A and the threshold value B. It can be said that this is equivalent to MOD2 addition assuming that the High level and the Low level of the integrated signal d and the 1-bit delay signal e, which are analog signals, are 1 and 0, respectively. When MOD2 addition is performed, 1-D and 1 + D can be treated in the same manner, so that the overall transfer function (1 + D) / (1-D) is equal to the transfer function 1. Therefore, the comparator output g
The input data a can be demodulated by latching with.

FIG. 11 is a diagram for explaining a recording / reproducing method for PR (1, 0, -1). Referring to FIG. 11, the input data a has a transfer function 1 / (1-
The recording signal b is precoded by the precoding circuit represented by D ² ). The recording signal b becomes the reproducing signal c by the transfer function 1-D in the magnetic recording / reproducing system. The reproduction signal c is subjected to the processing whose transfer function is represented by 1 + D,
The signal d delayed by the 1-bit delay circuit is added to obtain an added signal e, which is the detection point. The transfer function of the reproduction system at this time, (1-D) · ( 1 + D) i.e., 1-D ^2, and the transfer function of the whole recording and reproducing becomes 1. The sign is detected as a ternary value, and the comparator output f which becomes 1 when the addition signal e exceeds the plus side threshold value and the minus side threshold value is reproduced clock g.
Input data is demodulated by latching with.

[0008]

FIG. 12 shows the PR described above.
(1, -1) system, PR (1,1) system and PR
It is a figure which shows the relationship between the standardized frequency and amplitude level of each (1, 0, -1) system. Referring to FIG. 12, PR
In the (1, -1) method, there is no direct current component at the detection point, but the peak of the spectrum is in a higher range than in the PR (1,0, -1) method. S / N on the high frequency side due to head core loss in the case of magnetic recording, deterioration of frequency characteristics of magnetic tape, etc.
Considering the decrease in the ratio, PR (1,0, -1) is more advantageous. Further, in the PR (1,1) system, the peak of the spectrum shifts to the low frequency side as compared with the PR (1, -1) system, but since there is a DC component at the detection point, this causes distortion in the signal. Occurrence of detection error is likely to occur.

The PR (1, 0, -1) method is a detection method that compensates for the drawbacks of both of these detection methods.
Compared with the (1, -1) method, the peak of the spectrum is shifted to the low frequency range, and there is no DC component as in the PR (1,1) method. However, the PR (1,0, -1) detection method requires a precoding circuit for modulation. Therefore, there is a problem that the PR (1,0, -1) method cannot be applied to the detection of a signal recorded by NRZI modulation such as DAT.

The present invention has been made to solve the above problems, and is a code detecting device capable of detecting a signal recorded by NRZI modulation with a detection characteristic equivalent to PR (1,0, -1). The purpose is to provide.

[0011]

According to the present invention, there is provided a magnetic recording / reproducing apparatus for NRZI modulating an input digital signal, recording the same on a recording medium, reproducing the recorded signal and demodulating the original digital signal. The code detection device used is
Detecting means for detecting the reproduced signal reproduced through the 1 + D transmission system, clock signal forming means for forming a clock signal based on the reproduced signal, and even sequence and odd sequence in response to the detected signal in response to the clock signal. Division means for dividing into even series and odd series, and demodulation means for demodulating the original digital signal by MOD2 adding signals from the integrated even series and odd series. ..

[0012]

The principle of the detecting method of the code detecting apparatus according to the present invention will be described with reference to FIG. The input signal has a transfer function of 1 /
The NRZI conversion unit 1 represented by (1-D)
I converted and recorded. As a characteristic of the magnetic recording / reproducing unit 2, the reproduction output is a signal that passes through the system of the transfer function 1-D.
At this point, the overall transfer function is 1, but PR
In order to take advantage of the above advantage at the detection point of the (1,0, -1) system, a signal delayed by 1 bit, whose transfer function is represented by 1 + D in the addition processing unit 3, as in the PR (1,0, -1) system. And the reproduction signal is detected using the signal obtained as a result.

However, in this state, the transfer function is 1
It becomes + D, and the input data cannot be demodulated. Therefore, the demodulation unit 4 divides the signal digitized at the detection point into an even series and an odd series according to the clock signal, and performs integration in each series. The transfer function of this integral is
It becomes 1 / (1-D ² ).

When the even series is 1, the odd series corresponds to D, so that the transfer function of the even series integration system 4a is 1 /.
(1-D ² ), the transfer function of the odd series integration system 4 b is D /
(1-D ² ). The integrated signals of both series are MOD2
When added, the transfer function of the demodulator 4 is (1 + D) / (1-
D ² ). Here, the transfer function in MOD2 addition is 1
Since −D and 1 + D are equivalent, the transfer function (1+
D) / (1-D ² ) is the transfer function (1-D) / (1-
D ² ), and becomes 1 / (1 + D). Therefore, the transfer function 1 + D up to the preceding stage of the demodulation unit 4 and the transfer function 1 / (1 + D) of the demodulation unit 4 can obtain the transfer function 1 as a whole, and the input signal can be demodulated.

That is, in the code detecting apparatus according to the present invention, a signal recorded by NRZI modulation is delayed at the time of detection by a reproduction signal and one bit thereof as in the PR (1,0, -1) system. Signals are added, and this is used as a detection point to perform detection by taking advantage of the PR (1, 0, -1) method. The detected data is divided into an even series and an odd series, the signals are integrated, and the integrated even series signal and the odd series signal are MOD2 added to demodulate the data.

[0016]

【Example】

(1) First Embodiment An embodiment of the present invention will be described below with reference to the drawings. Figure 2
FIG. 3 is a circuit diagram showing a specific configuration of a code detecting device to which the present invention is applied, and FIGS. 3 and 4 are timing charts of signals at respective positions in FIG.

The input data a may be a modulation code such as 8-10 modulation or data after scrambled by scrambled NRZI modulation. This data is NRZ
It is I-modulated and becomes a recording signal b, which is recorded on the magnetic tape 21. The reproduction output from the reproduction head 5 is amplified by the reproduction amplifier 6, waveform-equalized by the reproduction equalizer 7, and sent to the addition processing unit 3.

The reproduced signal c sent to the addition processing unit 3 is added to the signal d delayed by the delay circuit 8 for one bit in the analog addition unit 9 to perform 1 + D, and an addition signal e is obtained. This is the detection point of this code detection device. This signal has no DC component as compared with the PR (1,1) system, and the peak of the spectrum is shifted to the low frequency side as compared with the PR (1, -1) system, so that PR (1,0,-
1) It has the same frequency characteristic as the detection point of the method.

The output of the comparator 10 when the addition signal e exceeds the threshold value A on the plus side is f, and the output of the comparator 11 when it exceeds the threshold value B on the minus side (g in this example). When the threshold is exceeded, it is "L").

Further, a PLL (Phase Looked)
A clock recovery unit 20 including a loop circuit 12 and a frequency divider circuit 13 is provided. The clock recovery unit 20 divides the recovered clock from the PLL circuit 12 into a frequency dividing circuit 13
One of the clocks divided by 2 is output as an even clock h and the other is output as an odd clock r. Either the even clock h or the odd clock k may be used. A signal obtained by latching the comparator output f with the latch circuit 14a at an even clock h is set as an even set i, and a signal obtained by latching the comparator output g by the latch circuit 14b at an even clock h is set as an even reset j. RS-FF (Re
set-Set-Flip-Flop) circuit 15a sets "H" when the even set i becomes "L",
When the even-numbered reset j becomes “L”, the even-numbered series is integrated by setting it to “L”, and the even-numbered integrated signal k is obtained. The odd set m, the odd reset n, and the odd integrated signal o are similarly obtained. Input data a can be reproduced by MOD2 addition of the even-number integrated signal k and the odd-number integrated signal o by the MOD2 adding circuit 16.

In the case of 8-10 modulation or the like, this reproduced data pq can be collated with a demodulation table to obtain a demodulated signal. A demodulated signal can be obtained by performing MOD2 addition (descramble) with the same random signal.

(2) Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the code detecting apparatus according to the present invention is applied to a digitally modulated signal which can suppress the DC component and the continuation of the same bit and has a small error propagation. FIG. 5 is a block diagram showing a main part of a recording system and a reproducing system of a digital signal according to the second embodiment, and FIGS. 6 to 8 are timing charts of signals at respective points shown in FIG.

First, the structure of the recording system according to the second embodiment will be described. Referring to FIG. 5, in the recording system, input data a is divided into blocks every predetermined n bits, a redundant bit adding circuit 23 for adding a redundant bit of 1 bit to the head of the divided block, and a response to a sync pulse. A redundant bit addition timing generation circuit 24 that sends the timing signal to the redundant bit addition circuit 23 and a synchronization signal generation circuit 32 that generates a synchronization signal in response to a synchronization pulse are provided. The signal to which the redundant bit is added is NRZI converted through the latch circuit 31 and the MOD2 arithmetic circuit. This signal is called block data.

This block data includes a buffer memory 26 and a DS that can store one block of block data.
It is sent to the V (Digital Sum Variation) measurement control circuit 27. The DSV measurement control circuit 27 stores the modulated DSV at the end of the preceding block data, and calculates the DSV when the front pattern and the back pattern of the current block data are output. Here, the front pattern and the back pattern mean a signal obtained by NRZI-converting (n + 1) -bit data generated by adding a redundant bit to the beginning of the divided n-bit data and its inverted signal. Then, it is determined whether the block data stored in the buffer memory 26 is inverted (a back pattern is selected) or not (a front pattern is selected) so that the absolute value of DSV becomes small, and the switch 28
The back pattern or the front pattern is selectively output by switching the.

The second embodiment of the present invention will be described below with reference to FIGS. 5 to 8 using concrete data.

The input data a is scrambled data. The input data a is divided into n-bit (n = 5 in this example) blocks, and a redundant bit (redundant bit = 1 in this example) is added to the beginning thereof to obtain a front pattern c and a back pattern d of NRZI modulation. .. The recording signal e is recorded by selecting either the front pattern or the back pattern for each block in consideration of the DC component.

Next, in the reproducing system, the reproduced signal f and the signal g obtained by delaying the reproduced signal f by 1 bit are added to each other to obtain the added signal h. The comparator output when the added signal h exceeds the positive threshold A is set to i, and the comparator output when the negative signal exceeds the negative threshold B is set to j (in this example, when the threshold is exceeded). Is "L"). Further, one clock obtained by dividing the reproduction clock by two is an even clock k, and the other clock is an odd clock o.
Either the even clock k or the odd clock o may be used. A signal latching the comparator output i at the even clock k is set as an even set w, and a signal latching the comparator output j at the even clock k is set as an even reset m. A signal that becomes “H” when the even set w becomes “L” and becomes “L” when the even reset m becomes “L” is defined as an even integration signal n. The odd set p, the odd reset q, and the odd integrated signal r are similarly obtained. Even integrated signal n
And the odd integrated signal r are added by MOD2 to obtain the added signals s and t. The addition signals s and t have an error caused by switching between the front pattern and the back pattern at the time of recording, and only one bit has occurred at the head of the block, and the data b after the redundant bit addition at the time of recording is not completely reproduced. However, the input data a can be reproduced by deleting this redundant bit. Furthermore, this reproduced data u may be decrambled to obtain a demodulated signal.

[0028]

As described above, according to the present invention, the NRZ
The signal recorded by the I modulation is converted into the conventional PR (1,-
1) method and PR (1,1) method, not PR (1,
Since it can be detected through the transfer system of the same transfer function 1 + D as that of the 0, -1) method, the peak of the spectrum at the detection point can be detected by shifting to the lower frequency side than the PR (1, -1) method. Since it is not necessary to regenerate the DC component at the detection point as in the (1,1) method, a code detecting apparatus that can obtain the same effect as the PR (1,0, -1) method without using a precoding circuit. Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an operation of a code detection device according to the present invention.

FIG. 2 is a block diagram showing a main part of a code detection device according to the present invention.

FIG. 3 is a diagram showing a timing chart of signals at respective points shown in FIG.

FIG. 4 is a diagram showing a timing chart of signals at respective points shown in FIG.

FIG. 5 is a block diagram showing a main part of a code detection apparatus according to a second embodiment of the present invention.

6 is a diagram showing a timing chart of signals at respective points in FIG.

7 is a diagram showing a timing chart of signals at respective points in FIG.

8 is a diagram showing a timing chart of signals at respective points in FIG.

FIG. 9 is a diagram showing a timing chart of a PR (1, -1) system.

FIG. 10 is a diagram showing a timing chart of a PR (1,1) system.

FIG. 11 is a timing chart showing a PR (1, 0, -1) system.

FIG. 12 PR (1, -1), PR (1,1) and P
It is a figure which shows the relationship between the normalized frequency and amplitude level in each system of R (1, 0, -1).

FIG. 13 is a diagram showing an NRZI conversion circuit and data at each point.

FIG. 14 is a diagram showing precode circuits and data at respective points.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 NRZI conversion section 2 Magnetic recording / reproducing section 3 Addition processing section 4 Demodulation section 4a Even series integration system 4b Odd series integration system

Claims (1)

[Claims] 1. A code detecting device used in a magnetic recording / reproducing device for NRZI-modulating an input digital signal to record it on a recording medium, reproducing the recorded signal and demodulating it to an original digital signal. Detecting means for detecting the reproduced signal through a 1 + D transmission system, clock signal forming means for forming a clock signal based on the reproduced signal, and an even series in response to the detected signal in response to the clock signal And an odd series, a dividing means for integrating the even series and the odd series, and MOD2 addition of the integrated signals from the even series and the odd series to demodulate the original digital signal. And a demodulation unit for performing code detection.