JPH05130447A - Field discrimination circuit - Google Patents

Abstract

PURPOSE:To provide the field discrimination circuit of a television receiver unnecessitating an input signal other than a synchronizing signal. CONSTITUTION:The field discrimination circuit discriminating an odd or an even number field of a TV signal in a television receiver employing a matrix type display element on which a TV picture is displayed is featured to be provided with count means (2-5) counting number of horizontal synchronizing signals from a first horizontal synchronizing signal after a vertical synchronizing signal till a first horizontal synchronizing signal after a vertical synchronizing signal of a succeeding field, means (6, 7) implementing field discrimination based on a count of the count means till the first horizontal synchronizing signal after the vertical synchronizing signal of the succeeding field and outputting an H or an L signal corresponding to an odd number or an even number field at the same period as the vertical synchronizing signal and a means correcting a field discrimination output at count error.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating circuit for a TV device using a matrix type display element.

[0003]

2. Description of the Related Art In recent years, as a TV image display device replacing a cathode ray tube, development has been progressing mainly on liquid crystal, and a device of about 5 inches is now commercialized. Regarding the liquid crystal display screen, it is considered that the direct-view type will be further enlarged in the future, and the projection type represented by the projector will be miniaturized in the future, and in both of these, high definition and high resolution can be achieved.
As a means for increasing the resolution, although the same interlaced scanning method as the TV method and the non-interlaced scanning method have been proposed, a method of improving the resolution by devising scanning lines has been proposed. In order to perform those scanning methods, it is necessary to distinguish between the odd field and the even field of the TV signal. FIG. 4 shows a standard NTSC signal from, for example, a Toshiba synchronous reproduction IC (TA8
695F) shows a horizontal synchronizing signal HD and a vertical synchronizing signal VD. When the odd field or the even field is discriminated from the sync signal, it can be seen from FIG. 4 that the vertical sync signal VD falls and the vertical sync signal VD falls.
A field is generally discriminated by utilizing the fact that the phase differences θ1 and θ2 from the first trailing edge of the horizontal synchronizing signal HD after the trailing edge are different between the odd field and the even field.

As a means for realizing the field discrimination, the first horizontal synchronizing signal HD after the falling edge of the vertical synchronizing signal VD to the falling edge of the vertical synchronizing signal VD with a clock pulse having a frequency sufficiently higher than that of the horizontal synchronizing signal HD. A means for counting the phase differences θ1 and θ2 until the trailing edge of and comparing them between fields can be considered.

In addition, the horizontal synchronizing signal HD in each field
A method of counting the number and discriminating the field by its absolute value is also conceivable.

[0006]

In the above conventional field discrimination, the standard N is used as the video signal source to be displayed.
Other than TSC signal, VTR signal or CD-ROM
In order to perform field discrimination including the signal (non-interlaced signal) sources that have no correlation for each field regarding the phase difference of the map information etc. from the input signal other than the synchronization signal (for example, more than the horizontal synchronization signal HD There is a problem that requires a high frequency clock pulse signal).

The present invention has been made in order to eliminate such a conventional defect, and an object of the present invention is to provide a field discriminating circuit of a TV apparatus which does not require an input signal other than a synchronizing signal.

[Structure of Invention]

[0009]

In order to achieve the above object, the present invention is a field discriminating circuit for discriminating an odd or even field of a TV signal in a TV device using a matrix type display element for displaying a TV image. At TV
The count operation is performed in synchronization with the horizontal sync signal of the horizontal sync signal and the vertical sync signal reproduced synchronously from the composite signal, and from the first horizontal sync signal after the vertical sync signal to the first horizontal sync signal after the vertical sync signal of the next field. Field determination is performed based on the counting means for counting the number of horizontal synchronizing signals up to the synchronizing signal and the count value of the counting means up to the first horizontal synchronizing signal after the vertical synchronizing signal of the next field, and the same period as the vertical synchronizing signal is obtained. It is characterized in that it is provided with means for outputting an "H" or "L" signal corresponding to an odd or even field and a means for correcting the field discrimination output when a count error occurs.

[0010]

In the present invention, the vertical synchronizing signal VD is generated by the n-ary counter which performs the counting operation in synchronization with the horizontal synchronizing signal HD.
The counting operation starts from the first horizontal signal HD after the falling edge, the state of the counter before the first horizontal synchronizing signal HD after the falling edge of the vertical synchronizing signal VD of the next field is latched, and the odd field and the even field are latched from that state. And outputs "H" or "L" corresponding to the odd and even fields.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a field discriminating circuit according to an embodiment of the present invention, FIG. 2 is a time chart of the embodiment in a normal state, and FIG. 3 is a time chart when a sync signal of the embodiment is defective. Is. According to the present invention, in any of the signal sources, the number of horizontal synchronizing signals HD for one frame conforms to a standard TV signal during normal operation (for example, in Japan, the number of horizontal synchronizing signals HD conforms to the NTSC system, The number of HDs is 525, and assuming that the first horizontal synchronizing signal HD after the fall of the vertical synchronizing signal VD is the first HD, the number of HDs to the first HD after the falling of the vertical synchronizing signal VD of the next field is even in the even field. 262 lines, 263 lines in an odd number field), and the counting operation is started from the first horizontal signal HD after the fall of the vertical synchronization signal VD by the n-ary counter which performs the counting operation in synchronization with the horizontal synchronization signal HD. , Latch the state of the counter before the first horizontal synchronizing signal HD after the fall of the vertical synchronizing signal VD of the next field, and from that state To determine the number field and an even field, odd, and outputs a "H" or "L" corresponding to the even field. In FIG. 1, the field discriminating circuit includes D flip-flops 1 to 5, JK flip-flops 6 to 7, a NAND circuit 8, AND circuits 9 to 12, N.
It is composed of an OR circuit 13 and OR circuits 14 to 15.

First, details in a normal state will be described with reference to FIG. In the n field, the D flip-flop 1 and the NAND circuit 8 generate a differential pulse having a time width from the falling of the vertical synchronizing signal VD to the first falling of the horizontal synchronizing signal HD. The differential pulse is AN
The counter state at the time of the first falling edge of the horizontal synchronizing signal HD of the D flip-flops 2 to 5 forming the quinary counter through the D circuits 9 to 12 is set to zero. Then, the counting operation is started at the next falling edge of the horizontal synchronizing signal HD,
Counting is performed at the timing shown in FIG.

Next, in the (n + 1) th field, the JK flip-flop 6 latches the Q outputs of the D flip-flops 2 and 3 at the falling edge of the vertical synchronizing signal VD, and J input = “H” and K input = “L”. As shown in the timing chart of FIG. 2, the JK flip-flop 6 outputs Q = “H” and inverted output = “L”. At the same time, the NOR circuit 13 checks for an error in the counter output, and if there is an error, OR
The outputs of the AND circuit 12 are corrected by the circuits 14 and 15. In this case, since there is no error, the NOR circuit 13
L ″ is input to the OR circuits 14 and 15. The JK flip-flop 7 outputs J at the output timing of the D flip-flop 1.
With the input = “H” and the K input = “L”, the field discrimination result is output from the Q output at the timing shown in the figure. n + 1
The same operation as described above is performed in the field. However, n +
In one field, the number of horizontal synchronizing signals HD is one more than in the previous field, so that the JK flip-flop 6 has Q = “H”.
And the field discrimination result is as shown in the timing diagram.
H ″. Here, in the present embodiment, n and n +.
Two fields correspond to even fields and n + 1 field corresponds to odd fields. As a field discrimination result signal, even field is "L" and odd field is "
It is possible to obtain the determination result of "H".

Next, the operation when there is a defect in the synchronizing signal (when a spiked pulse is generated on the synchronizing signal HD due to noise or the like and the count is incorrect) will be described with reference to FIG. Assuming that the above-mentioned problem occurs in the n field (two spike-shaped pulses are generated as shown in FIG. 3), the counting operation shown in the figure is performed and n +
At the falling edge of the vertical synchronizing signal VD in one field, the values latched by the JK flip-flop 6 as count outputs are J input = “L” and K input = “L”.
Since the K flip-flop 6 operates to maintain the previous state, the output Q = “L” and the inverted output = “H”. However, the output of the NOR circuit 13 which checks the error of the counter output becomes "H", and the outputs of the OR circuits 14 and 15 become "H" regardless of the output of the JK flip-flop 6. Then, the J input of the JK flip-flop 7 = ”
Since H ”and K input =“ H ”, the JK flip-flop 7 is toggled and the Q output is“ H ”, whereby a count error can be avoided and a normal field discrimination result output can be obtained. ..

In the above embodiment, the n-ary counter is a quinary counter, but it can be easily understood that the larger n is, the better the problem is. Further, in the present embodiment, the avoidance of the error is explained by using two spike-shaped pulses, but in the case where the number of horizontal synchronizing signals HD becomes the same between fields, the error cannot be avoided and the same determination result is continuously obtained. Will be output. However, it is unlikely that this will happen, and it is unlikely that it will span multiple fields. Therefore, there is no practical problem.

[0016]

As described above, according to the present invention, it is possible to provide a field discriminating circuit for a TV device which does not require an input signal other than a synchronizing signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a field discrimination circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation in a normal state according to an embodiment of the present invention.

FIG. 3 is a time chart showing an operation when a problem occurs in a sync signal according to an embodiment of the present invention.

FIG. 4 is a diagram showing a phase relationship of synchronization signals obtained from a standard NTSC signal by a Toshiba synchronous reproduction IC.

[Explanation of symbols]

 1-5 ... D flip-flop 6, 7 ... JK flip-flop 8 ... NAND circuit 9-12 ... AND circuit 13 ... NOR circuit 14, 15 ... OR circuit

Claims (1)

[Claims] 1. A field discriminating circuit for discriminating an odd field or an even field of a TV signal in a TV device using a matrix type display device for displaying a TV image, wherein a vertical sync signal and a vertical sync signal reproduced synchronously from a TV composite signal. Counts in synchronization with the horizontal sync signal of the sync signals, and counts the number of horizontal sync signals from the first horizontal sync signal after the vertical sync signal to the first horizontal sync signal after the vertical sync signal of the next field. Field determination is performed from the count means and the count value of the count means up to the first horizontal sync signal after the vertical sync signal of the next field, and "H" or A means for outputting an "L" signal and a means for correcting the field discrimination output when a count error occurs are provided. Field determination circuit, characterized in that.