JPH08204992A - Field discrimination circuit - Google Patents

Abstract

PURPOSE: To correctly discriminate between an odd number and an even number irrespective of the phase difference between inputted horizontal synchronizing signals and vertical synchronizing signals by providing an edge detection circuit, a 1-bit counter and a latch circuit. CONSTITUTION: An edge detection signal which falls by the first horizontal synchronizing signal after the fall of the vertical synchronizing signals and rises by the next horizontal synchronizing signal is obtained by the edge detection circuit 1. By the 1-bit counter 2 cleared by the edge detection signal, whether the number of the horizontal synchronizing signal is odd numbered or even numbered is counted and the output of an H level or an L level is obtained. A counted result in the next edge detection signal is latched in the latch circuit 3 and a latch signal is outputted as a field discrimination signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating circuit used in an image processing apparatus in television technology.

[0002]

2. Description of the Related Art When a video signal for interlaced scanning is subjected to image processing, it is necessary to determine whether the currently input signal is an odd field or an even field.
The conventional field discriminating circuit shown in FIG. 4 obtains the field discriminating signal by latching the horizontal synchronizing signal at the falling edge of the vertical synchronizing signal as shown in FIG.
However, this method has a problem that the field discrimination signal cannot be correctly extracted when a phase difference between the horizontal synchronizing signal and the vertical synchronizing signal occurs as shown in FIG.

[0003]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and makes it possible to correctly discriminate odd and even fields regardless of the phase difference between the input horizontal synchronizing signal and vertical synchronizing signal. It is intended to provide a circuit.

[0004]

In order to solve the above-mentioned problems, the present invention uses an input horizontal synchronizing signal as a clock signal to detect an edge of an input vertical synchronizing signal, and an edge detecting circuit for detecting the edge. And a latch circuit that latches the output of the counter with the edge detection signal. Further, the edge detection circuit inputs an inverter that inverts an input horizontal synchronizing signal and a vertical synchronizing signal to a data input terminal (D), and outputs the inverter output signal to a clock terminal (Ck).
And a second flip-flop circuit for inputting the Q output signal from the first flip-flop circuit to the data input terminal (D) and inputting the inverter output signal to the clock terminal (Ck). A flip-flop circuit,
It is configured by an OR circuit that inputs or outputs the Q output signal from the first flip-flop circuit and the -Q output signal from the second flip-flop circuit. The 1-bit counter is a third flip-flop that inputs an inverted signal of the horizontal synchronizing signal to a clock terminal and inputs the edge detection signal to a clear terminal (-CLR). The -Q output signal is input to the data input terminal (D), and an odd or even discrimination signal is output from the Q output terminal. Further, the latch circuit inputs an inverted signal of the horizontal synchronizing signal to a clock terminal,
A fourth flip-flop for inputting the edge detection signal to the enable terminal (-E), a Q output signal of the third flip-flop for inputting to the data input terminal (D), and a field discrimination signal from the Q output terminal. Is being output.

[0005]

According to the field discriminating circuit of the present invention, the edge detecting circuit causes the vertical synchronizing signal to fall, then falls at the first horizontal synchronizing signal, and then falls at the next horizontal synchronizing signal. A 1-bit counter that obtains a rising edge detection signal and is cleared by the edge detection signal counts whether the number of horizontal synchronization signals is an odd number or an even number and outputs it as an H level or an L level, and then outputs the next edge. The count result of the detection signal is latched by the latch circuit, and the latch signal is output as the field discrimination signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A field discriminating circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a field discrimination circuit according to the present invention. In the figure, reference numeral 1 is an edge detection circuit, which includes an inverter 11, a first flip-flop 12, and a second flip-flop 1.
3 and an OR circuit 14 to generate an edge detection signal which falls after the vertical synchronizing signal falls, falls at the first horizontal synchronizing signal, and rises at the next horizontal synchronizing signal. Reference numeral 2 denotes a 1-bit counter, which is composed of a third flip-flop, which is cleared by the edge detection signal to start counting the horizontal synchronizing signal. An odd-numbered H level output and an even-numbered L level output are output from the Q output terminal. It is outputting. A latch circuit 3 is composed of a fourth flip-flop, and uses the edge detection signal as an enable signal to latch the output signal of the 1-bit counter with a horizontal synchronizing signal.

The operation of the above arrangement will be described below. FIG. 2 is a timing chart for explaining the operation of each unit. The horizontal synchronization signal Hd input to the edge detection circuit 1 is
The first flip-flop 12 is inverted by the inverter 11.
Input to the clock terminal (Ck) of the
d is input to the data input terminal (D), the Q1s signal is input from the Q output terminal of the first flip-flop 12 to the data input terminal (D) of the second flip-flop 13, and The -Q2s signal is obtained from the -Q output terminal, and the Q1s signal and the -Q2s signal are OR circuit 14
OR gate to generate an edge detection signal Ve.

Clear terminal (-CL of 1-bit counter 2
The edge detection signal Ve is input to R), the inverted horizontal synchronization signal from the inverter 11 is input to the clock terminal (Ck), and the 1-bit count signal S1bit, that is, the horizontal synchronization signal is input from the Q output terminal. When the count is an odd number, the H level is output, and when the count is an even number, the L level is output and input to the data input terminal (D) of the latch circuit 3. The edge detection signal Ve is input to the enable terminal (-E) of the latch circuit 3, and the inverted horizontal synchronization signal from the inverter 11 is input to the clock terminal (Ck). At L level,
When the horizontal sync signal falls, the 1-bit counter 2
The 1-bit count signal S1bit from the Q output terminal is latched and output from the Q output terminal as the field discrimination signal Sf. That is, since the number of horizontal sync signals in the odd field is odd, the output of the 1-bit counter becomes an odd number (H level) when the position of the edge detection signal is reached, and the horizontal sync signal in the even field is The output of the 1-bit counter is an even number (L level) when the position of the edge detection signal is reached, and this level is latched by the latch circuit.

[0009]

As described above, according to the field discriminating circuit of the present invention, the edge detecting circuit causes the vertical synchronizing signal to fall, then falls at the first horizontal synchronizing signal, and then falls at the next horizontal synchronizing signal. A 1-bit counter that obtains a rising edge detection signal and is cleared by the edge detection signal counts whether the number of horizontal synchronization signals is an odd number or an even number and outputs it as an H level or an L level, and then outputs the next edge. The count result of the detection signal is latched by the latch circuit, and the latch signal is output as the field discrimination signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a field discrimination circuit according to the present invention.

FIG. 2 is a timing diagram illustrating the operation of each part of the field discrimination circuit according to the present invention.

FIG. 3 is a timing diagram illustrating an operation of a conventional field discrimination circuit.

FIG. 4 is a block diagram showing a conventional field discrimination circuit.

[Explanation of symbols]

 1 Edge Detection Circuit 2 1 Bit Counter (Third Flip-Flop) 3 Latch Circuit (Fourth Flip-Flop) 11 Inverter 12 First Flip-Flop 13 Second Flip-Flop 14 OR Circuit

Claims (4)

[Claims] 1. An edge detection circuit for detecting an edge of an input vertical synchronization signal using an input horizontal synchronization signal as a clock signal, a 1-bit counter cleared by the edge detection signal, and an output of the counter. A field discriminating circuit comprising a latch circuit for latching with an edge detection signal. 2. The edge detection circuit inputs an inverter for inverting an input horizontal synchronizing signal, a vertical synchronizing signal to a data input terminal (D), and an inverter output signal to a clock terminal (Ck). One flip-flop circuit and a second flip-flop circuit for inputting the Q output signal from the first flip-flop circuit to the data input terminal (D) and inputting the inverter output signal to the clock terminal (Ck) 2. An OR circuit for OR-gates by inputting a Q output signal from the first flip-flop circuit and a -Q output signal from the second flip-flop circuit. Field discrimination circuit. 3. The 1-bit counter is a third flip-flop for inputting an inverted signal of a horizontal synchronizing signal to a clock terminal and inputting the edge detection signal to a clear terminal (-CLR). 2. The field discriminating circuit according to claim 1, wherein the -Q output signal of the flip-flop is inputted to the data input terminal (D), and an odd or even discrimination signal is outputted from the Q output terminal. 4. The latch circuit comprises a fourth flip-flop for inputting an inverted signal of a horizontal synchronizing signal to a clock terminal and inputting the edge detection signal to an enable terminal (-E), and the third flip-flop. 4. A Q output signal of a group is input to a data input terminal (D), and a field discrimination signal is output from the Q output terminal.
The described field discrimination circuit.