JP2001292339A - Synchronizing signal processing circuit, image processing apparatus using it and synchronizing signal discrimination method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronizing signal processing circuit that can ensure field discrimination without error and imposing any restriction onto a processing signal and to provide an image processing apparatus using the same and a synchronizing signal discrimination method. SOLUTION: The synchronizing signal processing circuit is provided with a field discrimination circuit 13 that extends a pulse width of a horizontal synchronizing signal H-SYNC supplied from a synchronizing separator circuit 12 to a prescribed width at e.g. 1/2 H or below to generate a horizontal synchronizing signal H-SYNCW whose pulse width is extended. The circuit is also provided with an interface circuit 15 that detects whether the horizontal synchronizing signal H-SYNCW whose pulse width is extended is at a high level or at a low level at a prescribed position of the 1/2 H or below of the horizontal synchronizing signal supplied from the field discrimination circuit 13 on the basis of a front edge of a vertical synchronizing signal V-SYNC and discriminates whether a field of a video signal is an odd number field or an even number field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal processing circuit for determining whether a current field is an odd field or an even field in an interlaced signal format, an image processing apparatus using the same, and The present invention relates to a method for determining a synchronization signal.

[0002]

2. Description of the Related Art For example, an interlaced plasma display panel (PlasmaDisplay P) is used.
In an image processing apparatus using a signal processing circuit (scan converter) for driving a display device such as an anel (PDP) or converting the number of lines, the current field at the signal input stage is odd (Odd) or even (Even). ) Must be determined.

[0003] The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC of NTSC, PAL and DTV interlace signals have a relationship as shown in FIG. That is, in a certain field at the edge of the vertical synchronization signal V-SYNC, the edges of the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC are aligned, and are shifted by 0.5H in the next field.

[0004]

Since the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC of the interlace signal have a relationship as shown in FIG. 3, the horizontal synchronizing signal and the next synchronizing signal There is a method of detecting the position of the edge of the vertical synchronization signal between the horizontal synchronization signals to determine the field.

However, if the phases of the horizontal synchronizing signal and the vertical synchronizing signal are shifted at a stage before being input to the scan converter due to a signal difference or a temperature characteristic of an IC at the preceding stage, the field judgment is erroneously made. Sometimes.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronous signal processing circuit capable of reliably performing a field determination without being restricted by a processing signal and a synchronous signal processing circuit. An object of the present invention is to provide an image processing apparatus and a synchronization signal determining method using the same.

[0007]

To achieve the above object, a synchronization signal processing circuit according to the present invention comprises: a first circuit for expanding a pulse width of a horizontal synchronization signal corresponding to an interlaced signal to a predetermined width; A level of the horizontal synchronizing signal whose pulse width has been widened by the first circuit is detected at a position where a predetermined time has elapsed from a leading edge of the vertical synchronizing signal corresponding to the interlaced signal, and an odd number is determined in accordance with the detected level. And a second circuit for determining whether the field is an even field or an even field.

The image processing apparatus according to the present invention further comprises a first circuit for expanding the pulse width of the horizontal synchronizing signal corresponding to the interlaced signal to a predetermined width, and a vertical synchronizing signal corresponding to the interlaced signal. At a position where a predetermined time has elapsed from the leading edge, the level of the horizontal synchronizing signal whose pulse width has been expanded by the first circuit is detected, and it is determined whether the field is an odd field or an even field according to the detected level. A synchronous signal processing circuit including a second circuit; and a signal processing circuit that receives an image signal of a predetermined method, performs predetermined signal processing based on the determination result of the second circuit, and outputs the processed signal.

In the present invention, the pulse width of the horizontal synchronizing signal expanded in the first circuit is a predetermined width equal to or less than half the horizontal synchronizing frequency.

In the present invention, when a plurality of horizontal synchronizing signals having different frequencies are supplied to the first circuit, the first circuit can process at least the pulse width of the horizontal synchronizing signal. 1 of horizontal frequency corresponding to high resolution
/ 2 or less.

Further, the present invention has a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplying the signals to the first circuit and the second circuit.

Further, in the present invention, the first circuit sets a pulse width capable of absorbing a phase shift amount of a horizontal synchronization signal caused by characteristics of the synchronization separation circuit.

In the present invention, the first circuit can absorb a phase shift amount of a horizontal sync signal having a largest phase shift amount due to the characteristics of the sync separation circuit among horizontal sync signals to be processed. Set to pulse width.

Further, the present invention is a method of determining a synchronization signal to determine whether an interlace is an odd field or an even field based on a synchronization signal corresponding to the interlace signal. A first step of increasing the pulse width of the horizontal synchronizing signal corresponding to the signal to a predetermined width, and a pulse generated by the first circuit at a position where a predetermined time has elapsed from the leading edge of the vertical synchronizing signal corresponding to the interlaced signal. A second step of detecting the level of the widened horizontal synchronizing signal and determining whether the field is an odd field or an even field according to the detected level.

According to the present invention, for example, the horizontal synchronization signal separated by the synchronization separation circuit is supplied to the first circuit. In the first circuit, the pulse width of the horizontal synchronizing signal is widened to a predetermined width and supplied to the second circuit. And the second
Circuit detects the level of the horizontal synchronizing signal whose pulse width has been widened by the first circuit at a position where a predetermined time has elapsed from the leading edge of the vertical synchronizing signal corresponding to the interlaced signal, and Accordingly, it is determined whether the field is an odd field or an even field.

[0016]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus employing a synchronization signal processing circuit according to the present invention.

As shown in FIG. 1, the image processing apparatus 10 includes an analog / digital (A / D) converter 11, a synchronization separation circuit 12, a field discrimination circuit 13 as a first circuit, and a second circuit as a second circuit. Scan converter 14,
It has an interface circuit 15 as a second circuit and an interlace-driven display 16 made of, for example, a PDP.

The A / D converter 11 converts the input analog video signal AIM into a digital signal and supplies the digital signal to the scan converter 14.

The sync separation circuit 12 receives a composite or component signal, and receives a horizontal sync signal H-SYNC,
The sync signal and the vertical sync signal V-SYNC are separated and supplied to the field discriminating circuit 13 and the scan converter 14. In the present embodiment, the external synchronization sync is also supplied to the sync separation circuit 12 and supplied to the field discrimination circuit 13 and the scan converter 14.

The field discriminating circuit 13 includes a differentiating circuit and a buffer (not shown), and widens the pulse width of the horizontal synchronizing signal H-SYNC supplied from the synchronizing and separating circuit 12 by the differentiating circuit to a predetermined width of, for example, 1 / 2H or less. , The horizontal synchronizing signal H-SYNCW having the increased pulse width is supplied to the interface circuit 15. The field discriminating circuit 1
3, the pulse width of the horizontal synchronizing signal H-SYNCW to be widened may be a predetermined width of 1 / 2H or less, but at least 1 / (1) of the frequency corresponding to the highest resolution that can be processed.
It is desirable to be 2H or less. Further, it is desirable that the horizontal synchronization signal to be processed has a pulse width capable of absorbing the phase shift amount of the horizontal sync signal having the largest phase shift amount.

The scan converter 14 outputs the three primary color signals R converted into digital signals by the A / D converter 11.
(Red), G (green), B (blue), horizontal synchronization signal H-SYN
C, vertical synchronization signal V-SYNC, and clock signal C
In response to the LK, the input three primary color signals, that is, R, G, and B digital signals are written into the image memory at a predetermined clock, and then the written data is read out in synchronization with a clock having a frequency different from, for example, a writing clock. For example, a progressive video signal corresponding to the number of vertical and horizontal pixels of the PDP is generated and supplied to the interface circuit 15.

The scan converter 14 converts various input signals into images and outputs the converted signals in a fixed pixel progressive system. That is, the input signal of the progressive system is not only output in the progressive system, but also the input signal of the interlace system is converted into a progressive video signal and output. In addition, the scan converter 14
When outputting the progressive video signal, for example, a horizontal synchronizing signal H-SYN corresponding to the progressive video signal is output.
C, vertical synchronization signal V-SYNC, and clock signal C
LK is supplied to the interface circuit 15.

The interface circuit 15 is, for example, a PL
D (Programmable Logic Device) and a horizontal synchronization signal whose pulse width is widened at a predetermined position equal to or less than 1 / 2H of the horizontal synchronization signal supplied by the field discriminating circuit 13 from the leading edge of the vertical synchronization signal V-SYNC. Signal HS
It is detected whether the YNCW is at a high level or a low level, and it is determined whether the YNCW is an odd field (Odd Field) or an even field (Even Field). Then, the interface circuit 15
Based on the determination result, the progressive video signal supplied by the scan converter 14 is converted into an interlaced signal and supplied to the display 16.

Next, the field determination according to this embodiment will be described in more detail with reference to FIG.

FIG. 2 shows the relationship between the horizontal synchronizing signal and the vertical synchronizing signal, and is an explanatory diagram of the field discrimination according to the present invention.

The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC of the NTSC, PAL, and DTV interlace signals have a relationship as shown in FIG. 2A. That is, in a field at the edge of the vertical synchronization signal V-SYNC, the horizontal synchronization signal H-SYNC
The edges of the NC and the vertical synchronization signal V-SYNC are aligned and shifted by 0.5H in the next field. As shown in FIG. 2B, the horizontal synchronizing signal H-SYNC is obtained by using a differentiating circuit and a buffer of the field discriminating circuit 13 as shown in FIG.
Increase width to less than 0.5H.

The interface circuit 15 detects whether the horizontal synchronization signal H-SYNCW is at a high level or a low level at a point PDT shown below from the leading edge of the vertical synchronization signal V-SYNC. NTSC, PAL, SECAM (horizontal frequency 15kHz):
0.8 μs ± 0.2 μm 1035i, 1080i / 48, 1080i / 50, 1080i / 60: 9.
0 μs ± 0.5 μm (horizontal frequency 27 kHz to 34 kHz
z)

The components of YUV and R, G,
B, whether the signal is sync-on-green or a signal with an external sync is detected at the above position. In the interface circuit 15, for example, the horizontal synchronizing signal HS
The case where the YNCW is at the high level is determined as an odd field, and the case where the YNCW is at the low level is determined as an even field.
Of course, it is also possible to adopt a configuration in which the case where the horizontal synchronization signal H-SYNCW is at a high level is determined as an even field, and the case where the horizontal synchronization signal H-SYNCW is at a low level is determined as an odd field.

As shown in FIG. 2C, the rising edge (leading edge) of the vertical synchronizing signal V-SYNC and the rising edge of the horizontal synchronizing signal H-SYNC depend on the inherent characteristics and temperature characteristics of the sync separation circuit 12. The rising (leading edge) may be shifted. However, in the present embodiment, the horizontal synchronization signal H
Since the pulse width of −SYNC is widened, even if a phase shift occurs as shown in FIG. 2C, the field can be determined at the above position as shown in FIG. 2D.

Next, the operation of the above configuration will be described.

For example, an analog video signal AIM including R, G, and B signals is supplied to an A / D converter 11 and a synchronization separation circuit 12. In the A / D converter 11,
The R, G, B signals are converted to digital signals and supplied to the scan converter 14. Further, in the sync separation circuit 12, the horizontal sync signal H-SYNC and the vertical sync signal V-SYNC are converted from the input analog video signal AIM.
C is separated in synchronization and supplied to the field determination circuit 13 and the scan converter 14.

In the scan converter 14, for example, R, G, and B digital signals are written into the image memory at a predetermined clock, and then the written data is read out in synchronization with, for example, a clock having a frequency different from the write clock. , A progressive video signal corresponding to the number of vertical and horizontal pixels of the PDP is generated and supplied to the interface circuit 15. In addition, the scan converter 11
Then, when a progressive video signal is output, the corresponding horizontal synchronization signal H-SYNC, vertical synchronization signal V-SYNC, and clock signal CLK are supplied to the interface circuit 15.

In the field discriminating circuit 13, the pulse width of the horizontal synchronizing signal H-SYNC supplied from the synchronizing separation circuit 12 is expanded by a differentiating circuit (not shown) to a predetermined width of, for example, 1 / 2H or less. The horizontal synchronizing signal H-SYNCW having the increased pulse width is supplied to the interface circuit 15.

In the interface circuit 15, the field discriminating circuit 1 starts from the leading edge of the vertical synchronizing signal V-SYNC.
3. The horizontal synchronizing signal H-SY whose pulse width has been widened at a predetermined position equal to or less than 1 / 2H of the horizontal synchronizing signal supplied by
It is detected whether the NCW is at a high level or a low level, and it is determined whether the NCW is an odd field or an even field. And the interface circuit 1
In step 5, based on the determination result, the scan converter 14
Is converted into an interlaced signal and the display 16
Supplied to

As described above, according to the present embodiment, the pulse width of the horizontal synchronization signal H-SYNC supplied from the synchronization separation circuit 12 by the differentiating circuit is set to, for example, 1 / 2H.
A field discriminating circuit 13 for generating a horizontal synchronizing signal H-SYNCW having a pulse width expanded to a predetermined width as described below.
The horizontal synchronizing signal H-SYNCW whose pulse width has been increased to a high level at a predetermined position equal to or less than 1 / 2H of the horizontal synchronizing signal supplied by the field discriminating circuit 13 from the leading edge of the vertical synchronizing signal V-SYNC. Detects whether it is an odd field or an even field, and, based on the determination result, converts the progressive video signal supplied by the scan converter 14 into an interlaced signal. Since the interface circuit 15 for converting and supplying the converted data to the display 16 is provided, it is possible to prevent the upper and lower fields from being inverted due to the erroneous determination of the odd field and the even field, thereby lowering the resolution in the vertical direction.

Further, since the pulse width of the horizontal synchronizing signal is widened, and a point for detecting the high level and the low level is provided with a margin, the phase change due to the temperature characteristic of the sync separation circuit 12 at the preceding stage, the external sync input, and the like. Horizontal sync signal H-SYNC and vertical sync signal V due to differences in internal sync input
Even if a phase shift occurs between -SYNC and -SYNC, erroneous determination is not performed, and a decrease in resolution can be prevented. Further, processing can be performed not only for NTSC signals but also for PAL and DTV signals. In addition, it can respond to a YUV signal input or an external sync input. Further, since only the high level and the low level of the horizontal synchronization signal H-SYNCW are detected at a certain point from the leading edge of the vertical synchronization signal, there is an advantage that the configuration can be made relatively easily.

In the field discriminating circuit 13,
In order to generate the horizontal synchronizing signal H-SYNCW having an increased width, it is possible to generate the horizontal synchronizing signal H-SYNCW using, for example, a cutting pulse removal circuit or a macro vision removal circuit.

Further, it is also possible to adopt this method in a sync separation circuit corresponding to all signal formats such as NTSC and DTV and to make it part of the function.

Also, for example, it is possible to adopt this method in the scan converter 14 so that the field determination can be accurately performed regardless of the phase shift of the horizontal synchronization signal H-SYNC or the vertical synchronization signal V-SYNC. Further, it is possible to output the discrimination result of the odd field and the even field from a certain pin, and at the same time, change the rising timing and length of the field inversion pulse by using a register. Also, as shown by a broken line in FIG. 1, for example, the field determination result can be supplied to the scan converter 14 and reflected in signal processing in the scan converter 14.

[0040]

As described above, according to the present invention,
It is possible to prevent the upper and lower fields from being inverted due to the erroneous determination of the odd field and the even field, thereby lowering the resolution in the vertical direction.

Further, according to the present invention, the pulse width of the horizontal synchronizing signal is widened, and a point for detecting the high level and the low level is provided with a margin, so that the phase change due to the temperature characteristic of the preceding stage, for example, the synchronizing separation circuit. Also, even if a phase shift occurs between the horizontal synchronization signal and the vertical synchronization signal due to the difference between the external sync input and the internal sync input, erroneous determination is prevented and a reduction in resolution can be prevented.

Further, since only the level of the horizontal synchronizing signal is detected at a certain point from the leading edge of the vertical synchronizing signal, there is an advantage that the configuration can be made relatively easily.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus employing a synchronization signal processing circuit according to the present invention.

FIG. 2 shows a relationship between a horizontal synchronization signal and a vertical synchronization signal,
FIG. 4 is an explanatory diagram of field determination according to the present invention.

FIG. 3 is a horizontal synchronizing signal H-SYN of an interlace signal;
FIG. 6 is a diagram illustrating a relationship between C and a vertical synchronization signal V-SYNC.

[Explanation of symbols]

10 ... Image processing device, 11 ... A / D converter, 12 ...
Sync separation circuit, 13 field discriminating circuit, 14 scan converter, 15 interface circuit, 16 display.

Claims (17)

[Claims] 1. A first circuit for expanding a pulse width of a horizontal synchronization signal corresponding to an interlace signal to a predetermined width, and a position at which a predetermined time has elapsed from a leading edge of a vertical synchronization signal corresponding to the interlace signal. And a second circuit for detecting the level of the horizontal synchronizing signal whose pulse width is widened by the first circuit, and determining whether the field is an odd field or an even field according to the detected level. Signal processing circuit. 2. The synchronization signal processing circuit according to claim 1, wherein the pulse width of the horizontal synchronization signal expanded in the first circuit is a predetermined width equal to or less than half the horizontal synchronization frequency. 3. When a plurality of horizontal synchronization signals having different frequencies are supplied to the first circuit, the first circuit includes:
2. The synchronization signal processing circuit according to claim 1, wherein the pulse width of the horizontal synchronization signal is set to be at least half the horizontal frequency corresponding to the highest resolution that can be processed. 4. The synchronization signal processing circuit according to claim 1, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 5. The synchronization signal processing circuit according to claim 2, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 6. The synchronization signal processing circuit according to claim 3, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 7. The synchronization signal processing circuit according to claim 5, wherein said first circuit sets a pulse width capable of absorbing a phase shift amount of a horizontal synchronization signal caused by characteristics of said synchronization separation circuit. 8. The first circuit sets a pulse width capable of absorbing a phase shift amount of a horizontal sync signal having a largest phase shift amount due to characteristics of the sync separation circuit among horizontal sync signals to be processed. The synchronization signal processing circuit according to claim 6. 9. A first circuit for expanding a pulse width of a horizontal synchronization signal corresponding to an interlace signal to a predetermined width, and a position at which a predetermined time has elapsed from a leading edge of a vertical synchronization signal corresponding to the interlace signal. And a second circuit for detecting the level of the horizontal synchronizing signal whose pulse width is widened by the first circuit and determining whether the field is an odd field or an even field according to the detected level. An image processing apparatus, comprising: a signal processing circuit; and a signal processing circuit that receives an image signal of a predetermined method, performs predetermined signal processing based on a determination result of the second circuit, and outputs the processed signal. 10. The image processing apparatus according to claim 9, wherein the pulse width of the horizontal synchronizing signal expanded in the first circuit is a predetermined width equal to or less than half the horizontal synchronizing frequency. 11. When a plurality of horizontal synchronizing signals having different frequencies are supplied to the first circuit, the first circuit adjusts the pulse width of the horizontal synchronizing signal to at least the highest resolution that can be processed. The image processing apparatus according to claim 9, wherein the width is set to be equal to or less than half the horizontal frequency. 12. The image processing apparatus according to claim 9, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 13. The image processing apparatus according to claim 10, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 14. The image processing apparatus according to claim 11, further comprising a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the interlaced signal and supplies the signals to the first circuit and the second circuit. 15. The image processing apparatus according to claim 13, wherein the first circuit sets a pulse width capable of absorbing a phase shift amount of a horizontal synchronization signal caused by characteristics of the synchronization separation circuit. 16. The first circuit sets a pulse width capable of absorbing a phase shift amount of a horizontal sync signal having a largest phase shift amount due to characteristics of the sync separation circuit among horizontal sync signals to be processed. The image processing apparatus according to claim 14, wherein: 17. A method for determining whether an interlaced field is an odd field or an even field based on a synchronizing signal corresponding to an interlaced signal, comprising: a horizontal signal corresponding to the interlaced signal; A first step of expanding the pulse width of the synchronization signal to a predetermined width; and a step of expanding the pulse width by the first circuit at a position where a predetermined time has elapsed from the leading edge of the vertical synchronization signal corresponding to the interlaced signal. A second step of detecting the level of the detected horizontal synchronization signal and determining whether the field is an odd field or an even field according to the detected level.