JP4715330B2 - Video signal processing device, display device, and video signal processing method - Google Patents

Description

  The present invention relates to a video signal processing device, a video signal processing method, and a display device that performs the video signal processing, and more particularly to a technique for detecting a signal format of an input or received video signal.

  2. Description of the Related Art Conventionally, some display devices such as a television receiver are compatible with video signals having a plurality of signal formats. In such a display device, a signal format of a video signal input from the outside or a video signal received by a built-in tuner is determined, and a signal processing state corresponding to the determined signal format is set. . As the detection of the signal format, for example, focusing on the stability of the vertical synchronization signal (Vsync) of the video signal, detection based on the vertical synchronization signal is performed, and processing is performed for each state.

Specifically, if the total number of horizontal lines (number of horizontal sync signals) in one vertical sync period is VTTL,
1) When there is no vertical sync signal for VTTL + α period or longer: No signal state (ex. Α = VTTL × 0.2)
2) When 1V TotalLine = VTTL continues more than β times continuously: Standard signal status (ex.β = 2)
3) Other than above: Non-standard signal states and states were classified.
Here, VTTL is the total number of lines in the 1V section of the standard signal.
480I: 262.5H, 480P: 525H, 1080I: 562.5H, 720P: 750H
It becomes the value.
Each actual state transition has hysteresis to prevent false detections, and according to each state 1) no signal state → screen mute (blanking), free run processing 2) standard signal State → High image quality processing 3) Processing such as non-standard signal state → free-run processing was performed. Here, free-run processing is a mode in which processing is performed at a stable timing that is not affected by an unstable input synchronization signal. Specifically, the input signal is temporarily written in the memory and then written into the memory. A process of reading the signal stably is performed.

  First, a conventional video signal format determination process example will be described with reference to the state transition diagram of FIG. First, when a determination operation is started by turning on the power of the display device or the like (step S1), initialization is performed with v_status = 00, and a transition is made to “no signal state: No-Signal” in step S2. While the vertical synchronization signal (Vsync) is not detected, the “no signal state” is maintained. However, when detected, v_status = 01 is set, and the process proceeds to “Non-Standard Signal” in step S3.

  Next, in “Non-Standard Signal” in step S3, if there is no vertical synchronization signal (Vsync) for a certain period (VTTL + α) or more, v_status = 00, and “no signal state” in step S2. : No-Signal ”. If 1V = VTTL continues continuously β times, v_status = 11 is set and the process proceeds to “Standard Signal” in step S4. In other cases, “Non-Standard Signal” in step S3 is held.

  Then, in the “standard state: Standard Signal” in step S4, if there is no vertical synchronization signal for a certain period (VTTL + α) or longer, v_status = 00 is set and “no signal state: No-Signal” in step S2. Transition. If 1V ≠ VTTL, v_status = 01, and the process proceeds to “Non-Standard Signal” in step S3. In other cases, "Standard Signal" in step S4 is held.

  When it is determined by these signal determinations that the signal is in the standard state, the image quality enhancement processing for the signal of the determined format is performed and displayed. When it is determined that the signal is in a non-standard state, display processing is performed so as to display the input video signal in a stable manner as much as possible by temporarily writing the input video signal into the memory without performing high image quality processing.

Patent Document 1 discloses a technique for discriminating between standard signals and non-standard signals of video signals.
JP 2003-134355 A

By the way, various actual signals exist as follows.
In the case of RF input, there are normal broadcast channels, weak electric field channels, adjacent no-signal channels, no-signal channels, and RF input signals from video game equipment.
In the case of a video input signal, there are a normal playback signal, a variable speed playback signal from a video tape playback device, a video input signal from a video game device, and no signal.
In the case of an input signal using a dedicated video input terminal, there may be 480P, 480I, 720P, 1080I, 540P (P is a progressive signal, I is an interlace signal), and no signal.

  Of these, in the normal broadcast channel, normal video playback, etc., high-quality image processing is performed as a standard signal state. However, a video signal output from a normal game device (hereinafter referred to as a game signal) Channels and adjacent non-signal channels must all be treated as non-standard signal states, and for weak electric field channels and adjacent non-signal channels, non-standard signal states and non-signal states are mixed depending on the signal state. There was a possibility of false detection, and optimal processing could not be performed.

  FIG. 6 is a diagram showing an example of statuses detected by such detection processing. In the figure, a double circle “◎” indicates a state that is stably detected, a circle “◯” indicates a state that may be detected, and a case where no other state is detected.

  As shown in FIG. 6, in the case of an RF signal received by a tuner, in the case of a normal broadcast channel reception signal, it is stably detected as a standard signal, and when a weak electric field channel is received, the standard signal is detected. In some cases, it is detected that the signal is a non-standard signal. When receiving an adjacent non-signal channel, there are cases where a non-signal is detected and a non-standard signal is detected. When receiving a no-signal channel, no signal is detected. When an RF signal output from the video game device is input, it is detected as a non-standard signal.

  In the case of a video signal input to the video input terminal, when a signal normally reproduced by a video tape reproducing device (VCR) is supplied, it is detected as a standard signal. When a signal reproduced by a video tape playback device (VCR) is supplied, it is detected as a non-standard signal. When a video signal output from the video game device is input, it is detected as a non-standard signal. When there is no signal at the video input, it is detected as no signal.

  Further, even when a 480P, 720P, or 1080I video signal is input at a video input terminal or the like, it is detected as a standard signal. In the case of a 540P video signal that may be output by the game device, it is detected as a non-standard signal.

In such conventional detection, there has been a possibility of erroneous detection as described above, and there has been a case where optimum processing cannot be performed.
However,

  The present invention has been made in view of the above points, and an object of the present invention is to enable good video signal discrimination corresponding to various types of video signal inputs.

The present invention detects a horizontal synchronization signal and a vertical synchronization signal from a video signal obtained by input or reception, and the number of horizontal lines within one vertical synchronization period determined by the vertical synchronization signal is defined by the video signal format. Whether the number of horizontal lines is a standard video signal or a non-standard video signal, the number of horizontal lines within one vertical synchronization period is detected in units of 1/2 horizontal line, and the number of detected horizontal lines Is determined to be an interlace signal when it is odd, it is determined as a progressive signal when it is an even number, the video signal format is determined based on the frequency of the horizontal synchronization signal and the vertical synchronization signal, and the determined video signal format is Video obtained by input or reception based on the distinction between standard signals and non-standard video signals, and interlace signals and progressive signals. Set No. processing state corresponding, as its setting, to execute the video signal processing interlaced signal when it is determined that interlace signal nonstandard video signal, a progressive signal when it is determined that the progressive signal of the non-standard video signal The video signal processing is executed .

  By doing so, it is possible to correctly distinguish between a standard signal and a non-standard video signal and to distinguish between an interlaced signal and a progressive signal, and it is possible to deal with various input signal states.

  According to the present invention, optimal signal detection with few malfunctions can be performed on various signal states of video signals, and optimum processing with few malfunctions can be performed. Specifically, for example, when the input signal is abnormal, it is possible to respond quickly when the synchronization signal is disturbed. In addition, since the accuracy of discriminating irregular signal states and game signals such as when RF signals are weak, when receiving adjacent no-signal channels, and during video shift playback, signal processing suitable for game signals can be performed. become. Furthermore, since the accuracy of discriminating between irregular signal states such as when receiving an RF signal in a weak electric field, when receiving an adjacent non-signal channel, and during video shift playback and the game signal is improved, horizontal and vertical frequencies can be adjusted in an irregular signal state. When it fluctuates, it is possible to suppress the fluctuation within the display allowable range on the display unit by switching the output to the free-run frequency. Furthermore, in the future, it is possible to cope with a case where a 540P signal is input from an HD compatible video game device.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  In this example, the present invention is applied to a video display device using a liquid crystal display panel as display means. FIG. 1 shows the overall configuration of the display device. An antenna 11 is connected to a tuner 12, and the tuner 12 demodulates and selects a channel, extracts a composite video signal (CVBS), and synchronizes it with a decoder unit 13 to obtain a component signal (YCbCr). The component signal is converted by the scan converter 14 into timing and resolution corresponding to the display panel. As the conversion here, pixel number conversion, conversion from an interlace signal to a progressive signal, or the like is performed. The output of the scan converter 14 is subjected to high image quality processing by an RGB processing unit (Y color difference RGB processing unit) 15, and finally the panel driving unit 16 performs display driving on the liquid crystal display panel 17. As the high image quality processing in the RGB processing unit 15, for example, sharpness processing is performed.

  The decoder unit 13 sends the synchronization signal component separated from the video signal to the control unit 19, and the control unit 19 determines the details of the received (input) video signal such as the signal format. Based on the determination result, details of the signal processing state in the scan converter 14 and the like are set. 1 shows a configuration for processing a signal received by the tuner 12, a video signal (video signal) obtained from an external video input terminal (not shown) is supplied to the decoder unit 13 for processing. May be.

  FIG. 2 is a diagram illustrating a detailed configuration example of the decoder unit 13. An input signal obtained at the input terminal 21 is supplied to the synchronization separation circuit 22 to separate the horizontal synchronization signal H ′ and the vertical synchronization signal V ′. The separated horizontal synchronizing signal H ′ and vertical synchronizing signal V ′ are supplied to the control unit 19 constituted by a microcomputer, and the input signal format is discriminated from the frequency of the horizontal synchronizing signal H ′ and the vertical synchronizing signal V ′. Do. There is a possibility that the horizontal synchronization signal H ′ and the vertical synchronization signal V ′ at this stage are not synchronization signals with accurate timing. Further, a frequency division ratio setting (divide_ratio) of a PLL (Phase Locked Loop) circuit 23 synchronized with a horizontal synchronizing signal and a vertical period setting (v_ttl setting) of the V countdown unit 24 are performed.

  The PLL circuit 23 generates a stable horizontal synchronization signal H synchronized with the h_lock status indicating the stable state of the horizontal synchronization signal, the pixel clock (CLK), and CLK. The h_lock status is a signal for detecting the number of horizontal synchronization periods within one vertical synchronization period in units of 1/2 horizontal synchronization period. Using this h_lock status, the control unit 19 determines that the input video signal is the interlace signal I when the number of horizontal synchronization periods within one vertical synchronization period is odd, and the progressive signal P when the number is even. Processing to determine that there is. The V countdown unit 24 generates v_status indicating the state of the vertical synchronization signal, and a horizontal synchronization signal H, a vertical synchronization signal V, and a pixel clock CLK that have been stabilized by the countdown.

  The processing after the analog / digital converter 25 is performed by the horizontal synchronizing signal H, the vertical synchronizing signal V, and the pixel clock CLK. The analog / digital converter 25 converts the composite video signal into a digital signal, supplies the converted digitized composite video signal to the Y / C separation circuit 26, and separates it into a luminance signal and a chroma signal. The chroma decoder 27 sets the component signal (YCbCr).

Here, the video signal format detected from the frequency of the horizontal synchronizing signal H and the vertical synchronizing signal V supplied to the control unit 19 and the frequency division ratio setting of the PLL circuit 23 set by the control unit 19 corresponding to the format. An example of (divide_ratio) and vertical period setting (v_ttl setting) is as follows.
Example 1) H = 15.734kHz, V = 59.94Hz → 480I → divide_ratio = 858, v_ttl = 262.5H
Example 2) H = 31.468kHz, V = 59.94Hz → 480P → divide_ratio = 858, v_ttl = 525H
Example 3) H = 33.75kHz, V = 59.94Hz → 1080I → divide_ratio = 2200, v_ttl = 562.5H
Example 4) H = 45kHz, V = 59.94Hz → 720P → divide_ratio = 1650, v_ttl = 750H

  Next, an example of processing for determining the details of the video signal format by the control unit 19 of this example will be described with reference to the state transition diagram of FIG. First, when the determination operation is started by turning on the power of the display device (step S11), initialization is performed with v_status = 00, and a transition is made to “no signal state: No-Signal” in step S12. While the vertical synchronization signal (Vsync) is not detected, the “no signal state” is maintained. However, when detected, v_status = 01 is set, and the process proceeds to “Non-Standard Signal” in step S13.

  Next, in “Non-Standard Signal” in step S13, if no vertical synchronization signal (Vsync) exists for a certain period (VTTL + α) or longer, v_status = 00, and “no signal state” in step S12. : No-Signal ”. If 1V = VTTL continues continuously β times, v_status = 11 is set, and the process proceeds to the “standard state: Standard Signal” in step S14. In other cases, “Non-Standard Signal” in step S13 is held.

  In the “standard state: Standard Signal” in step S4, if there is no vertical synchronization signal for a certain period (VTTL + α) or more, v_status = 00 is set and “no signal state: No-Signal” in step S12. Transition. If 1V ≠ VTTL, v_status = 01, and the process proceeds to “Non-Standard Signal” in step S13. In other cases, “Standard Signal: Standard Signal” in step S14 is held. Up to this point, the processing is the same as that shown in FIG.

  In this example, in step S13, which is a process for a non-standard signal, a process using the h_lock status indicating the stable state of the horizontal synchronization signal is performed. Specifically, “Non-Standard Signal” is divided into two states: an interlace signal (v_state = 01) (step S14) and a progressive signal (v_state = 10) (step S15). To determine. The state transition of step S14 and step S15 is as follows. When the number of lines in one vertical period is counted in units of 1/2 horizontal period, the value is odd (odd number), prog = 0, and even (even number) It is done with a flag that becomes = 1.

  Based on the determination result, each circuit shown in FIG. 1 (scan converter 14, RGB) is controlled by the control unit 19 in the case of a non-standard interlace signal and in the case of a progressive signal. In the processing unit 15 or the like, the signal processing state is set to a corresponding state.

  FIG. 4 is a diagram showing an example of status detected by such detection processing. In the figure, a double circle “◎” indicates a state that is stably detected, a circle “◯” indicates a state that may be detected, and a case where no other state is detected.

  As shown in FIG. 4, in the case of an RF signal received by a tuner, in the case of a normal broadcast channel reception signal, it is stably detected as a standard signal, and when receiving a weak electric field channel, the standard signal is detected. There are cases where it is detected that the signal is a non-standard signal of an interlace signal. When receiving an adjacent non-signal channel, there are a case where it is detected that there is no signal and a case where it is detected that it is a non-standard signal of an interlace signal. When receiving a no-signal channel, no signal is detected. When an RF signal output from a video game device is input, it is detected as a nonstandard signal of a progressive signal.

  In the case of a video signal input to the video input terminal, when a signal normally reproduced by a video tape reproducing device (VCR) is supplied, it is detected as a standard signal. When a signal reproduced by a video tape playback device (VCR) is supplied, there are a case where it is detected as a non-standard signal of an interlace signal and a case of detection as a non-standard signal of a progressive signal. is there. When a video signal output from a video game device is input, it is detected as a nonstandard signal of a progressive signal. When there is no signal at the video input, it is detected as no signal.

  Further, even when a 480P, 720P, or 1080I video signal is input at a video input terminal or the like, it is detected as a standard signal. In the case of a 540P video signal that may be output by a game device, it is detected as a non-standard signal of a progressive signal.

  In this way, the non-standard signal is distinguished and detected by the interlace signal and the progressive signal, so that each non-standard signal can be displayed accurately and satisfactorily. In particular, video signals (game signals) supplied from video game devices can be handled as non-standard signals for progressive signals, so high-quality processing can be performed as progressive signals. Conventionally, high-quality processing is possible for non-standard signals. Compared with the case where the image is displayed without performing the display, a high-quality display is possible.

  With the signal processing configuration of this example described above, optimal signal detection with few malfunctions can be performed for various video signal signal states, and optimum processing with few malfunctions can be performed. Specifically, for example, when the input signal is abnormal, it is possible to respond quickly when the synchronization signal is disturbed. In addition, since the accuracy of discriminating irregular signal states and game signals such as when RF signals are weak, when receiving adjacent no-signal channels, and during video shift playback, signal processing suitable for game signals can be performed. become. Furthermore, since the accuracy of discriminating between irregular signal states such as when receiving an RF signal in a weak electric field, when receiving an adjacent non-signal channel, and during video shift playback and the game signal is improved, horizontal and vertical frequencies can be adjusted in an irregular signal state. When it fluctuates, it is possible to suppress the fluctuation within the display allowable range on the display unit by switching the output to the free-run frequency. Furthermore, in the future, it is possible to cope with a case where a 540P signal is input from an HD compatible video game device.

  In the embodiment described so far, the example is applied to a video display device using a liquid crystal display panel as display means. However, the present invention can also be applied to a display device using other display means.

It is a block diagram which shows the example of whole structure of the display apparatus by one embodiment of this invention. It is a block diagram which shows the structural example of the decoder by one embodiment of this invention. It is explanatory drawing which shows the example of a state transition by one embodiment of this invention. It is explanatory drawing which shows the example of the status detected in one embodiment of this invention. It is explanatory drawing which shows the example of the conventional state transition. It is explanatory drawing which shows the example of the status detected in a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Antenna, 12 ... Tuner, 13 ... Decoder, 14 ... Scan converter, 15 ... RGB processing part, 16 ... Panel drive part, 17 ... Liquid crystal display panel, 18 ... Memory, 19 ... Control part, 22 ... Sync separation part, 23 ... PLL circuit, 24 ... countdown circuit, 25 ... analog / digital converter, 26 ... luminance / chroma separation unit, 27 ... chroma decoder

Claims (3)

A synchronization signal detection unit for detecting a horizontal synchronization signal and a vertical synchronization signal from a video signal obtained by input or reception;
Whether the number of horizontal lines in one vertical synchronization period determined by the vertical synchronization signal detected by the synchronization signal detection unit is the number of horizontal lines defined by the video signal format, whether the video signal is a standard video signal or a non-standard video signal. A standard signal discriminating unit for discriminating;
The number of horizontal lines within one vertical synchronization period determined by the vertical synchronization signal detected by the synchronization signal detection unit is detected in units of 1/2 horizontal line, and the interlace signal is detected when the detected number of horizontal lines is an odd number. An interlace / progressive discriminating unit that judges that the signal is a progressive signal when it is an even number ,
The video signal format is discriminated by the frequency of the horizontal sync signal and the vertical sync signal detected by the sync signal detector, and the discriminating result in the standard signal discriminator and the interlace / progressive discriminator is determined by the discriminated video signal format. A control unit that distinguishes between a standard signal and a non-standard video signal, distinguishes between an interlace signal and a progressive signal, and sets the video signal obtained by the input or reception based on the distinction to a corresponding processing state. Bei example,
As the setting in the control unit, when it is determined that the signal is an interlace signal of a non-standard video signal, the video signal processing of the interlace signal is executed, and when it is determined that the signal is a progressive signal of the non-standard video signal, the video signal processing of the progressive signal is executed. A video signal processing device. A synchronization signal detection unit for detecting a horizontal synchronization signal and a vertical synchronization signal from a video signal obtained by input or reception;
Whether the number of horizontal lines in one vertical synchronization period determined by the vertical synchronization signal detected by the synchronization signal detection unit is the number of horizontal lines defined by the video signal format, whether the video signal is a standard video signal or a non-standard video signal. A standard signal discriminating unit for discriminating;
The number of horizontal lines within one vertical synchronization period determined by the vertical synchronization signal detected by the synchronization signal detection unit is detected in units of 1/2 horizontal line, and the interlace signal is detected when the detected number of horizontal lines is an odd number. An interlace / progressive discriminating unit that judges that the signal is a progressive signal when it is an even number ,
The video signal format is discriminated by the frequency of the horizontal sync signal and the vertical sync signal detected by the sync signal detector, and the discriminating result in the standard signal discriminator and the interlace / progressive discriminator is determined by the discriminated video signal format. The standard signal and the non-standard video signal are distinguished from each other, and the interlace signal and the progressive signal are distinguished. Based on the distinction, the input or received video signal is set to a corresponding processing state, and the setting is performed. A control unit that executes video signal processing of an interlace signal when determined as an interlace signal of a non-standard video signal, and executes video signal processing of a progressive signal when determined as a progressive signal of a non-standard video signal ;
The video signal obtained by the input or reception under the control of the control unit is processed for display, and either the video signal processing of the interlace signal or the video signal processing of the progressive signal is executed under the control from the control unit. A video signal processing unit;
And a display unit for displaying the video signal processed by the video signal processing unit. Synchronization signal detection processing for detecting a horizontal synchronization signal and a vertical synchronization signal from a video signal obtained by input or reception;
Whether the number of horizontal lines in one vertical synchronization period determined by the vertical synchronization signal detected in the synchronization signal detection process is the number of horizontal lines defined by the video signal format, whether the video signal is a standard video signal or a non-standard video signal. Standard signal discrimination processing to discriminate;
The number of horizontal lines in one vertical synchronization period determined by the vertical synchronization signal detected in the synchronization signal detection process is detected in units of 1/2 horizontal line, and an interlace signal is detected when the detected number of horizontal lines is an odd number. An interlace / progressive discrimination process that determines that the signal is a progressive signal when it is an even number ;
The video signal format is determined by the frequency of the horizontal sync signal and the vertical sync signal detected in the sync signal detection process, and the discriminant result in the standard signal discrimination process and the interlace / progressive discrimination process is used to determine the video signal format. The standard signal and the non-standard video signal are distinguished from each other, and the interlace signal and the progressive signal are distinguished. Based on the distinction, the input or received video signal is set to a corresponding processing state, and the setting is performed. Execute the control processing to execute the video signal processing of the interlace signal when it is determined as the interlace signal of the non-standard video signal, and to execute the video signal processing of the progressive signal when it is determined as the progressive signal of the non-standard video signal. A video signal processing method.

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