JP2002116740A - Picture display control device and display control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display control device and a display control method for displaying videos in two or more kinds of modes in a desired width and at a desired position. SOLUTION: It is made possible to display the videos in two or more modes in a desired width and at a desired position by judging an external mode setting signal 107 for each horizontal scanning period using the external mode setting signal 107 for altering a horizontal synchronous signal HD and a display mode, and an external clock as inputs, and moreover, display quality is prevented from deteriorating, by displaying the video in a fixed color for one or more horizontal scanning periods immediately after the mode is changed over.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen display control device and a display control method for displaying two or more types of images having different aspect ratios (images of two or more modes) on the same liquid crystal panel.

[0002]

2. Description of the Related Art A conventional screen display control device and screen display control method will be described below.

FIG. 5 is a schematic circuit diagram of a conventional screen display control device.

In FIG. 5, reference numeral 501 denotes a horizontal counter circuit, 502 denotes a horizontal display area setting circuit, 503 denotes an internal mode setting circuit, 504 denotes a fixed color generating circuit, 505 denotes a sampling clock generating circuit, 506 denotes a vertical counter circuit,
Reference numeral 507 denotes an on-screen display position circuit. In FIG. 5, a signal line 508 is an external clock, 509 is an external mode setting signal, 510 is an output count value of a horizontal counter circuit, 511 is an output signal of an internal mode setting circuit, 512 is an output signal of a horizontal display area setting circuit, and 513 is an output signal of a horizontal display area setting circuit. An output signal to the liquid crystal display panel as an output signal of the fixed color generation circuit, 514
Is an output signal of the sampling clock generating circuit to the liquid crystal display panel, 515 is an output count value of the vertical counter circuit, 516 is an output signal of the on-screen display position setting circuit, and 517 is an external on-screen switching setting signal. .

Next, the operation will be described with reference to FIG.

The horizontal counter circuit 501 receives a horizontal synchronization signal HD externally synchronized with a video signal and an external clock 508 as inputs, and is reset when the horizontal synchronization signal HD is input, and every time the external clock 508 is input. Count. The vertical counter circuit 506 receives a vertical synchronizing signal VD and a horizontal synchronizing signal HD which are externally synchronized with the video signal, and is reset when the vertical synchronizing signal VD is input, and counts every time the horizontal synchronizing signal HD is input. I do.

[0007] The on-screen display position circuit 507 receives the output count value 515 of the vertical counter circuit 506 as an input, and when the output count value 515 of the vertical counter circuit 506 reaches a predetermined value, the on-screen display position is changed. The signal 516 to be determined is output. The horizontal display area setting circuit 502 receives the output count value 510 of the horizontal counter circuit 501 as an input, and
When the output count value 510 reaches a predetermined value set in advance, a signal 512 indicating a horizontal display area is output. The internal mode setting circuit 503 outputs the vertical synchronization signal VD
, A horizontal synchronization signal HD, an external mode setting signal 509, an external on-screen switching setting signal 517, an output signal 516 of an on-screen display position setting circuit 507, and an output signal 512 of a horizontal display area setting circuit 502. When the horizontal synchronization signal HD becomes active after the VD becomes active, the polarity of the external mode setting signal 509 and the external on-screen switching setting signal 517 are determined.
A signal 511 for determining whether to display 16: 9 in the entire screen 4: 3 display, the entire screen 16: 9 display, or the 4: 3 display is output. The fixed color generation circuit 504 receives the output count value 510 of the horizontal counter circuit 501 and the output signal 511 of the internal mode setting circuit 503 as inputs, and outputs the output count value 510 of the horizontal counter circuit 501 in advance by the output signal 511 of the internal mode setting circuit 503. When the fixed value is reached, a fixed color output signal 513 is output to a liquid crystal display panel (not shown) at the timing of outputting the fixed color. Sampling clock generation circuit 505
Receives an output signal 511 of the internal mode setting circuit 503 as an input, outputs a sampling clock corresponding to the output signal 511 of the internal mode setting circuit 503 to a liquid crystal display panel (not shown), and displays a full screen 4: 3 display or a full screen 16:
The display screen is switched to one of the nine display and the 16: 9 display within the 4: 3 display.

Next, a screen display state of the conventional screen display control device and operation waveforms corresponding to each display state will be described with reference to FIGS.

FIG. 6 is a diagram showing the screen display state and the operation of main signals (the same signals as in FIG. 5 use the same numbers. Hereinafter, the same numbers indicate the same signals or circuits). .

Reference numeral 601 denotes a screen display state of a full screen 16: 9 display. Reference numeral 602 denotes a screen display state of a full screen 4: 3 display. Reference numeral 603 denotes a screen display state of a 4: 3 display at the top of the screen and a 16: 9 display at the bottom of the screen. 60
Reference numeral 4 denotes a screen display state of the full screen 16: 9 display.
511 is an output signal of the internal mode setting circuit, 515 is an output count value of the vertical counter circuit, 516 is an output signal of the on-screen display position setting circuit, 509 is an external mode setting signal, and 517 is an external on-screen switching setting signal. .

Screen display state 601 of 16: 9 display on full screen
Indicates a screen display state when the polarity of the external mode setting signal 509 is Lo and the polarity of the external on-screen switching setting signal 517 is Lo when the vertical synchronization signal VD falls.

The screen display state 602 of the full screen 4: 3 display is a screen display state when the polarity of the external mode setting signal 509 is Hi and the polarity of the external on-screen switching setting signal 517 is Lo when the vertical synchronization signal VD falls. Is shown.

A 4: 3 display at the top of the screen and a 16: 9 display at the bottom of the screen
The display screen display state 603 indicates a screen display state where the polarity of the external mode setting signal 509 is Hi and the polarity of the external on-screen switching setting signal 517 is Hi when the vertical synchronization signal VD falls.

Screen display state 604 of full screen 16: 9 display
Indicates a screen display state when the polarity of the external mode setting signal 509 is Lo and the polarity of the external on-screen switching setting signal 517 is Hi when the vertical synchronization signal VD falls.

The output signal 516 from the on-screen display position setting circuit is displayed in a 4: 3 format at the top of the screen and 1 at the bottom of the screen.
This is a signal indicating the display position of 16: 9 display when performing 6: 9 display.

In the example shown here, when the output count value 515 of the vertical counter circuit is 200, the output signal 516 of the on-screen display position setting circuit becomes Hi and 1
The display position of the 6: 9 display is shown. The output signal 511 of the internal mode setting circuit is "0" in the case of 16: 9 display.
This indicates that "1" is displayed in the case of 4: 3 display.

Next, an example of an operation waveform at the time of switching from the 4: 3 display at the upper part of the screen to the 16: 9 display at the lower part of the screen will be described with reference to FIG.

Reference numeral 701 indicates the switching timing of the output signal 511 of the internal mode setting circuit when switching from the 4: 3 display at the top of the screen to the 16: 9 display at the bottom of the screen.

Reference numeral 702 denotes an internal signal of the sampling clock generation circuit at the time of 16: 9 display, and 703 denotes an internal signal of the sampling clock generation circuit at the time of 4: 3 display, which is transmitted to a liquid crystal display panel (not shown). The display width in the horizontal direction can be switched by switching the sampling clock with the timing signal for sampling the video signal. In other words, in the sampling clock generation circuit, the internal signal 702 of the sampling clock generation circuit at the time of 16: 9 display or 4:
Internal signal 7 of sampling clock generation circuit at the time of display 3
03 is the output signal 511 of the internal mode setting circuit.
The output signal 514 of the sampling clock generation circuit is output.

Reference numeral 705 denotes a horizontal line display state, wherein the inner fixed color display portion is shown in black, and the video display portion is shown in a white frame.

In FIG. 7, 4: 3 display is performed until the output count value 515 of the vertical counter circuit reaches 200, and 16: 9 display is performed for the output count value 515 of the vertical counter circuit from 201.

The vertical synchronizing signal VD is H during the illustrated period.
i.

The output count value 515 of the vertical counter circuit
Is 200, and when the output signal 512 of the horizontal display area setting circuit becomes Lo, the output signal 516 of the on-screen display position setting circuit becomes Hi.

The switching timing 701 from the 4: 3 display to the 16: 9 display is based on the horizontal synchronization signal HD when the output signal 516 of the on-screen display position setting circuit is Hi.
Is output when falls.

Output signal 512 of horizontal display area setting circuit
Is a signal that rises when the output count value 510 of the horizontal counter circuit reaches 60 and falls when it reaches 860.

In the case of 16: 9 display, an image is displayed on a liquid crystal display panel (not shown) while the polarity of the output signal 512 of the horizontal display area setting circuit is Hi, and a liquid crystal display panel (not shown) is displayed during a period of Lo. Do not display video. In the case of 4: 3 display, the output signal 513 of the fixed color generation circuit is a signal in which the output count value 510 of the horizontal counter circuit falls at 140 and rises at 780, and the output count immediately before switching to 16: 9 display is counted. The value 510 is a signal that rises at 780 and falls at 860. When the polarity of the output signal 513 of the fixed color creation circuit is Hi, a fixed color is output to a liquid crystal display panel (not shown), the output signal 513 of the fixed color creation circuit is Lo, and the output of the horizontal display area setting circuit is output. When the polarity of the signal 512 is Hi, 4: 3 display is realized by outputting a video signal to a liquid crystal display panel (not shown).

When the horizontal synchronizing signal HD is Lo, the output signal 510 of the horizontal counter circuit is reset.

FIG. 8 is a diagram showing an example of a display state when 16: 9 display is performed in a 4: 3 display of a striped image.

Reference numeral 801 denotes how the image is viewed immediately after switching from 4: 3 display to 16: 9 display. How to see video 801 immediately after switching from 4: 3 display to 16: 9 display
5 shows an example in which a sudden change in the video mode is accompanied by a sudden change in the sampling clock, and the display state is deteriorated.

As described above, in the conventional screen display control device and display control method, when the sampling clock is switched in the display screen and 16: 9 display is performed in 4: 3 display, the external mode setting signal 509 and the external mode setting signal are output. The on-screen switching setting signal 517 was required, and the 16: 9 display location could only be displayed in the location previously set by the on-screen display position setting circuit 507. In addition, 4:
Immediately after switching from 3 display to 16: 9 display, the display state may be degraded due to switching of the output signal 514 of the sampling clock generation circuit.

[0031]

In the conventional screen control device and control method, in order to display 16: 9 in 4: 3 display, 16: 9 can be displayed only in a preset place and width. Immediately after the display switching, the switching of the output signal of the sampling clock generating circuit may cause the screen to be degraded due to the influence of the jitter, thereby deteriorating the screen display.

The present invention solves such a conventional problem, and displays a 16: 9 display at an arbitrary position and an arbitrary width in a 4: 3 display screen by a change in an external input signal, or A screen display control device which enables a 4: 3 display to be displayed at an arbitrary position and an arbitrary width in a 16: 9 display screen and does not cause deterioration of the screen display immediately after switching the display state in the display screen. And a display control method.

[0033]

According to a first aspect of the present invention, there is provided a screen display control apparatus capable of displaying at least two or more types of modes on the same screen. The clock is input,
A horizontal counter circuit for counting the number of clocks in one horizontal scanning period, an external mode setting signal for designating one of a plurality of modes, and an output signal of the horizontal counter circuit are inputted, and An internal mode setting circuit for determining the external mode setting signal in the non-video display area and setting an internal mode corresponding to the external mode setting signal for each horizontal scan; An output signal of a mode setting circuit, a fixed color generation circuit that outputs a fixed color at a timing within one horizontal scanning period in accordance with the output signal of the internal mode setting circuit, and an output signal of the internal mode setting circuit And a sampling clock generation circuit that outputs a sampling clock corresponding to the internal mode set by the internal mode setting circuit. For example, characterized in that is. According to this configuration, by having the internal mode setting circuit for setting the internal mode for each horizontal scan, it is possible to display two or more types of images at arbitrary positions and in arbitrary widths.

According to a second aspect of the present invention, there is provided a screen display control device for inputting a count value of the horizontal counter circuit and outputting a signal indicating a video display area within one horizontal scanning period to the internal mode setting circuit. The screen display control device according to claim 1, further comprising a display area setting circuit. By including the horizontal display area setting circuit, the output signal of the horizontal display area setting circuit can be effectively used,
Power saving design is possible.

According to a third aspect of the present invention, there is provided a screen display control device wherein a fixed color is displayed on the display screen for at least one horizontal scanning period immediately after switching of the output signal of the internal mode setting circuit. A screen display control device according to any one of claims 1 and 2. According to this configuration, a fixed color can be displayed on the display screen by the output signal of the fixed color generation circuit for at least one horizontal scanning period immediately after switching of the output signal of the internal mode setting circuit, and a stable screen Display becomes possible.

According to a fourth aspect of the present invention, the input period of the external mode setting signal is three horizontal scanning periods or more. With this configuration, the period of the external mode setting signal input to the internal mode setting circuit is 3
By setting the period to be equal to or longer than the horizontal scanning period, stable screen display can be performed.

According to the display control method of the present invention,
In a display control method that displays at least two types of video on the same screen, a horizontal synchronization signal and a clock are input and created based on the output signal of a horizontal counter circuit that counts clocks within one horizontal scanning period Determining an external mode setting signal designating one of a plurality of modes of video in a non-video display period in a horizontal scanning period by a horizontal display area setting signal to be set, and setting a corresponding internal mode; Generating a signal for displaying a fixed color at a timing within one horizontal scanning period based on the output signal of the horizontal counter circuit corresponding to the signal for setting the internal mode. And outputting the sampling clock
A screen in an arbitrary mode is displayed at an arbitrary vertical position with an arbitrary vertical width. According to this method, images of two or more modes can be displayed at an arbitrary position and an arbitrary width.

A display control method according to a sixth aspect of the present invention is characterized in that:
6. The display control method according to claim 5, wherein a fixed color is displayed on the display screen for at least one horizontal scanning period immediately after the switching of the internal mode setting signal. By this method, a stable screen is obtained by displaying a fixed color on the display screen for at least one horizontal scanning period immediately after the switching of the internal mode setting signal.

A display control method according to a seventh aspect of the present invention comprises:
7. The display control method according to claim 6, wherein an input period of the external mode setting signal is three or more horizontal scanning periods. According to this method, a stable screen display can be achieved by setting the period of the external mode setting signal input to the above-described internal mode setting circuit to three or more horizontal scanning periods.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a circuit constituting a screen display control device according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a horizontal counter circuit,
02 is a horizontal display area setting circuit, 103 is an internal mode setting circuit, 104 is a fixed color generation circuit, and 105 is a sampling clock generation circuit. Further, a signal line 106 is an external clock, 107 is an external mode setting signal, 108 is an output count value of the horizontal counter circuit 101, 109 is an output signal of the internal mode setting circuit 103, 110 is an output signal of the horizontal display area setting circuit 102, 111 is a fixed color creation circuit 10
An output signal 4 is an output signal to a liquid crystal display panel (not shown), and an output signal 112 is a sampling clock generation circuit 105 and is an output signal to a liquid crystal display panel (not shown).

Next, the operation will be described with reference to FIG.

The horizontal counter circuit 101 receives a horizontal synchronizing signal HD externally synchronized with a video signal and an external clock 106 as inputs. The horizontal counter circuit 101 is reset when the horizontal synchronizing signal HD is input, and every time the external clock 106 is input. Count. The horizontal display area setting circuit 102 receives the output count value 108 of the horizontal counter circuit 101 as an input,
When the output count value 108 of the horizontal counter circuit 101 reaches a predetermined value set in advance, an output signal 110 indicating a horizontal display area is output. The internal mode setting circuit 103 receives the external mode setting signal 107 and determines the polarity of the external mode setting signal 107 when the output signal 110 of the horizontal display area setting circuit 102 becomes active,
A signal for determining whether to display the entire screen 4: 3 display, the entire screen 16: 9 display, the 16: 9 display within the 4: 3 display, or the 4: 3 display within the 16: 9 display is output. The fixed color creation circuit 104 is a horizontal counter circuit 101
When the output count value 108 and the output signal 109 of the internal mode setting circuit 103 are input, and the output count value 108 of the horizontal counter circuit 101 becomes a predetermined value preset by the output signal 109 of the internal mode setting circuit 103, The fixed color output signal 111 is output at the timing of outputting the fixed color. Sampling clock generation circuit 1
Reference numeral 05 designates an output signal 109 of the internal mode setting circuit 103 as an input, outputs an output signal 112 of the sampling clock generation circuit 105 corresponding to the output signal 109 of the internal mode setting circuit 103, and displays a full screen 4: 3 display or a full screen A 16: 9 display, a 16: 9 display in an arbitrary width and an arbitrary position in a 4: 3 display, or a 4: 3 display in an arbitrary width and an arbitrary position in a 16: 9 display can be performed.

FIG. 1 shows a screen display control device provided with a horizontal display area setting circuit 102. The output count value 108 of the horizontal counter circuit 101 is directly input to the internal mode setting circuit 103, and the internal mode setting circuit 103 outputs a signal indicating the horizontal display area corresponding to the internal mode, so that the function of the horizontal display area setting circuit 102 can also be achieved, and the circuit scale can be reduced. However, the advantage that the horizontal display area setting circuit 102 exists independently is that by using the output signal 110 of the horizontal display area setting circuit 102 as a non-horizontal display area signal, it can be used for a power saving signal or the like.

Next, a screen display state of the screen display control device of the present invention and operation waveforms corresponding to each display state will be described with reference to FIGS.

FIG. 2 is a diagram showing a screen display state and operation waveforms of main signals.

Reference numeral 201 denotes a screen display state of a full screen 16: 9 display. Reference numeral 202 denotes a screen display state of a full screen 4: 3 display. 203 is one at the top and bottom of the screen
The screen display state of 4: 3 display at the center of the screen with 6: 9 display is shown. Reference numeral 204 denotes a screen display state of 4: 3 display at the top of the screen and 16: 9 display at the bottom of the screen. 205: 4: 3 display at the top and bottom of the screen, 16: at the center of the screen
9 shows a screen display state of nine displays. 107 is an external mode setting signal, and 109 is an output signal of the internal mode setting circuit. The vertical synchronization signal VD is a vertical start signal for screen display.

Screen display state 201 of full screen 16: 9 display
Indicates a screen display state when the polarity of the external mode setting signal 107 is Lo. Full screen 4: 3 display screen display state 202 or 16: 9 display at the top and bottom of the screen and 4: 3 display screen display state 203 at the center of the screen or 16: 9 at the bottom of the screen with 4: 3 display at the top of the screen The screen display state 204 of display or the screen display state 205 of 4: 3 display at the top and bottom of the screen and 16: 9 display at the center of the screen is as follows.
While the polarity of the external mode setting signal 107 is Hi,
4: 3 display is received and displayed every horizontal scanning period, and during the period when the polarity of the external mode setting signal 107 is Lo, 1 is displayed.
6: 9 display is received and displayed every horizontal scanning period.

The output signal 109 of the internal mode setting circuit is 1
"0" is output at the time of 6: 9 display, and "1" is output at the time of 4: 3 display.

Next, referring to FIG.
An example of an operation waveform at the time of switching to a screen display state of 6: 9 display and further 4: 3 display will be described.

Reference numeral 301 denotes an output signal 1 of the internal mode setting circuit at the time of switching from a 4: 3 display at the top of the screen to a 16: 9 display at the center of the screen and to a 4: 3 display at the bottom of the screen.
9 shows the switching timing. Reference numeral 302 denotes an internal signal of the sampling clock generation circuit at the time of 16: 9 display, and reference numeral 303 denotes an internal signal of the sampling clock generation circuit at the time of 16: 9 display, which outputs a video signal to a liquid crystal display panel (not shown). This is a timing signal to be sampled. 112 is the output signal 10 of the internal mode setting circuit.
9 is an output signal of a sampling generation circuit that outputs a sampling clock of 4: 3 display or 16: 9 display corresponding to 9.

By switching the sampling clock, the display width in the horizontal direction can be switched. That is,
In the sampling clock generation circuit, either the internal signal 302 of the sampling clock generation circuit at the time of 16: 9 display or the internal signal 303 of the sampling clock generation circuit at the time of 4: 3 display is changed to the internal mode by switching the frequency division ratio or the like. The output signal 112 of the sampling clock generation circuit is selected by the output signal 109 of the setting circuit.

Reference numeral 305 denotes a horizontal line display state, wherein the inner fixed color display portion is shown in black, and the video display portion is shown in a white frame.

When the output signal 110 of the horizontal display area setting circuit falls and the external mode setting signal 107 is Hi, the output signal 109 of the internal mode setting circuit is 4: 3.
Outputs the signal "1" for display and outputs the external mode setting signal 1
When 07 is Lo, the output signal 109 of the internal mode setting circuit outputs a signal “0” for performing 16: 9 display.

Output signal 110 of horizontal display area setting circuit
Rises when the output count value 108 of the horizontal counter circuit reaches 60, and falls when it reaches 860.

At the time of 16: 9 display, an image is displayed on the liquid crystal display panel (not shown) while the polarity of the output signal 110 of the horizontal display area setting circuit is Hi, and the liquid crystal display panel (not shown) is displayed during the period of Lo. ) Does not display video.

The output signal 111 of the fixed color generation circuit at the time of 4: 3 display is the output count value 108 of the horizontal counter circuit.
Falls at 140 and rises at 780. When the polarity of the output signal 111 of the fixed color generation circuit is Hi, a signal for displaying a fixed color is output to a liquid crystal display panel (not shown). The polarity of the output signal 111 of the fixed color generation circuit is Lo and the horizontal display area. When the polarity of the output signal 110 of the setting circuit is Hi, a 4: 3 display is realized by outputting a video signal to a liquid crystal display panel (not shown).

Further, the output signal 111 of the fixed color generation circuit is immediately after switching from the upper 4: 3 display to the 16: 9 central display, and from the 16: 9 central display to the 4: 3 lower display. A signal of the polarity of Hi is output during one horizontal display period immediately after the switching. Thus, a fixed color is displayed for one horizontal display period immediately after the screen switching.

When the horizontal synchronizing signal HD is Lo, the output signal 108 of the horizontal counter circuit is reset.

FIG. 4 shows the display deterioration when the image of the stripe pattern is switched from the upper part 4: 3 display of the screen to the central part 16: 9 display, and further from the central part 16: 9 display to the upper part 4: 3 display of the screen. FIG. 5 is a diagram showing an example of a display state for preventing the display.

Immediately after switching from 4: 3 display to 16: 9 display and immediately after switching from 16: 9 display to 4: 3 display, a fixed color is displayed for one or more horizontal periods.

The upper part of the screen 4: 3 display to the center part 16:
The fixed color 401 is displayed for at least one horizontal period immediately after the switching of the nine displays, and further from the central part 16: 9 display to the upper part 4:
Fixed color 401 for more than one horizontal period immediately after switching to 3 displays
Is displayed, when the display state is changed within the horizontal scanning period, it is prevented that the display state is deteriorated due to abrupt switching of the sampling clock.

However, immediately after switching from 4: 3 display to 16: 9 display or immediately after switching from 16: 9 display to 4: 3 display, a period in which the polarity of the external mode setting signal 107 is Hi, or Lo. Since the fixed color is displayed by the output signal 111 of the fixed color generation circuit 104 for one or more horizontal periods immediately after the switching if the period is less than or equal to two horizontal scanning periods, the image is not accurately displayed. A period in which the polarity of the setting signal 107 is Hi or a period in which the polarity is Lo requires at least three horizontal scanning periods.

FIG. 9 is a schematic diagram showing an example of a video system including the present invention to explain the features of the present invention.

Reference numeral 901 denotes a video medium such as TV, CD, DVD, etc .; 902, an external input such as a remote controller; 903, a control unit of a video system constituted by a microcomputer or the like; 904, a video signal for processing a signal from the video medium A processing unit 905 is a screen display control unit of the present invention, 906 is a liquid crystal display panel for displaying an image, HD is a horizontal synchronization signal synchronized and separated from the video signal, and VD is a vertical synchronization signal synchronized and separated from the video signal. .

Video media 9 including TVs, such as CDs and DVDs
The video signal No. 01 is converted into display data by the video signal processing unit 904 and displayed on the liquid crystal display panel. In the video signal processing unit 904, a horizontal synchronization signal HD and a vertical synchronization signal VD are generated by synchronizing and separating from the video signal.

In the screen display control unit 905, the external clock 106 and the external mode setting signal 107 are input from the control unit, and the horizontal synchronizing signal HD is input from the video signal processing unit 904. The control unit 903 receives a signal from the external input 902 and performs control of the video medium 901, control of the video signal processing 904, control of the screen display control unit 905, and the like.

Since the screen display control unit 905 of the present invention receives the horizontal synchronizing signal VD and does not input the vertical synchronizing signal HD, the circuit configuration is simplified and the circuit scale can be reduced. Although the vertical display control is performed by the control unit, it is mainly handled by a microcomputer program, so there is little increase in the scale of the control unit. Is enlarged.

In this embodiment, 4: 3 display and 16: 9 display
Although two types of display modes have been described, two or more display modes can be selected by increasing the number of bits of the external mode setting signal from one bit to two or more bits. Further, in response to the increase in the number of bits of the external mode setting signal, it is possible to cope with the increase in the number of bits of the output signal of the internal mode setting circuit and the increase of the internal signal of the sampling clock.

Note that the waveform polarities of the vertical synchronizing signal VD and the horizontal synchronizing signal HD shown in FIGS. 2, 3, 6, and 7 are merely examples, and may be reversed depending on how the sync separation is performed. Further, the output signal 110 of the horizontal display area setting circuit in FIG. 3 falls or rises, the output count value 108 of the horizontal counter circuit or the output signal 111 of the fixed color creation circuit rises or falls, and the output count value of the horizontal counter circuit. 108, the output signal 516 of the on-screen display position setting circuit in FIGS. 6 and 7 rises or falls, the output count value 515 of the vertical counter circuit and the output signal 512 of the horizontal display area setting circuit falls or rises, The output count value 510 of the counter circuit or the output signal 513 of the fixed color generation circuit rises or falls, and the output count value 510 of the horizontal counter circuit is an example, and varies depending on the screen display control device.

Further, in FIGS. 3 and 4, the screen display state due to the change in the polarity of the external mode setting signal 107 is shown in FIGS.
FIG. 8 shows an example of a screen display state due to a polarity change of the external mode setting signal 509 and the external on-screen switching setting signal 517, which changes depending on the display method.

[0072]

As described above, according to the present invention, by switching the external mode setting signal in the non-video display section within the horizontal scanning period, the 16: 9 display can be displayed at an arbitrary position in the 4: 3 display screen. In addition, it can be displayed in an arbitrary width, or a 4: 3 display can be displayed in an arbitrary place and an arbitrary width in a 16: 9 display screen, and by displaying a fixed color for at least one horizontal period immediately after switching, horizontal display is possible. By switching the display state during the scanning period,
An object of the present invention is to realize an excellent screen display control device and a screen control method that can prevent the display state from deteriorating.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit constituting a screen display control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a screen display state of the present invention and operation waveforms of main signals.

FIG. 3 is a diagram showing an example of an operation waveform when switching from a 4: 3 display to a 16: 9 display and further to a 4: 3 display screen display state;

FIG. 4 shows an image of a striped pattern from the upper part of the screen at 4: 3 display to the center part of the screen at 16: 9 and further at the center part of the screen at 16: 9.
The figure which shows an example of the display state at the time of switching from display to screen upper part 4: 3 display.

FIG. 5 is a schematic circuit configuration diagram of a conventional screen display control device.

FIG. 6 is a diagram showing a conventional screen display state and operation waveforms of main signals.

FIG. 7 is a diagram showing an example of an operation waveform at the time of switching from a 4: 3 display at the top of the screen to a 16: 9 display at the bottom of the screen.

FIG. 8 shows an image of a stripe pattern in 4: 3 display at 16:
9 is a diagram showing an example of a display state when 9 displays are performed.

FIG. 9 is a schematic diagram of an example of a video system.

[Explanation of symbols]

101, 501 Horizontal counter circuit 102, 502 Horizontal display area setting circuit 103, 503 Internal mode setting circuit 104, 504 Fixed color generation circuit 105, 505 Sampling clock generation circuit 201 Full screen 16: 9 screen display state 202 Full screen 4 : 3 screen display state 203 Screen display state of 16: 9 display at top and bottom of screen and 4: 3 display at center of screen 204 Screen display of 4: 3 display at top of screen and 16: 9 display at bottom of screen State 205 Screen display state of 4: 3 display at the top and bottom of the screen and 16: 9 display at the center of the screen 301 Display from 4: 3 display at the top of the screen to 16: 9 display at the center of the screen, and further to 4: 3 display at the bottom of the screen Output signal switching timing of internal mode setting circuit at the time of switching to screen display state 401 Upper part of screen 4: 3 display to center part 16 of screen: The display further the center of the screen 16: 9 screen from the display top 4:
Fixed color display immediately after switching to 3 display 506 Vertical counter circuit 507 On-screen display position circuit 601 Full screen 16: 9 display screen display state 602 Full screen 4: 3 display screen display state 603 Upper screen 4: 3 Screen display state of 16: 9 display at the bottom of the screen in display 604 Screen display state of full screen 16: 9 display 701 Internal when switching from 4: 3 display at the top of the screen to 16: 9 display at the bottom of the screen Output signal switching timing of the mode setting circuit 801 16:
Example of display state when 9 displays are performed

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 102 H04N 5/66 102B F term (Reference) 2H093 NC13 NC27 ND01 ND55 ND60 5C006 AB05 AF23 AF24 AF44 AF78 BB11 BC16 BF22 FA05 FA06 5C025 BA02 BA13 DA06 5C058 AA06 BA22 BB19 5C080 AA10 BB05 JJ01 JJ02 JJ04

Claims (7)

[Claims] 1. A horizontal counter for receiving a horizontal synchronizing signal and a clock and counting the number of clocks in one horizontal scanning period in a screen display control device capable of displaying images in at least two or more types of modes on the same screen. A circuit, an external mode setting signal designating one of a plurality of modes, and an output signal of the horizontal counter circuit,
An internal mode setting circuit for determining the external mode setting signal in a non-video display area within one horizontal scanning period, and setting an internal mode corresponding to the external mode setting signal for each horizontal scan; A fixed color generation circuit that receives a circuit count value and an output signal of the internal mode setting circuit, and outputs a fixed color at a timing within one horizontal scanning period corresponding to the output signal of the internal mode setting circuit; A screen display control device, comprising: a sampling clock generation circuit that receives an output signal of an internal mode setting circuit and outputs a sampling clock corresponding to the internal mode set by the internal mode setting circuit. 2. A horizontal display area setting circuit for receiving a count value of the horizontal counter circuit and outputting a signal indicating a video display area within one horizontal scanning period to the internal mode setting circuit. Item 6. The screen display control device according to Item 1. 3. The display device according to claim 1, wherein a fixed color is displayed on the display screen for at least one horizontal scanning period immediately after switching of the output signal of the internal mode setting circuit. Screen display control device. 4. An input period of the external mode setting signal is three.
4. The screen display control device according to claim 3, wherein the period is equal to or longer than a horizontal scanning period. 5. A display control method for displaying at least two or more modes of video on the same screen, wherein a horizontal synchronizing signal and a clock are input, and an output signal of a horizontal counter circuit for counting clocks within one horizontal scanning period. Determining an external mode setting signal designating one of a plurality of modes of video in a non-video display period in a horizontal scanning period by a horizontal display region setting signal generated based on the above, and setting a corresponding internal mode Generating a signal for displaying a fixed color at a timing within one horizontal scanning period based on an output signal of the horizontal counter circuit corresponding to the signal for setting the internal mode; and Outputting a sampling clock corresponding to the signal to be set, and displaying a screen in an arbitrary mode at an arbitrary vertical position with an arbitrary vertical width. Display control method, characterized in that. 6. The display control method according to claim 5, wherein a fixed color is displayed on the display screen for at least one horizontal scanning period immediately after the switching of the internal mode setting signal. 7. An input period of the external mode setting signal is three.
7. The display control method according to claim 6, wherein the display control period is equal to or longer than a horizontal scanning period.