JP2006284708A - Display panel, its driving method and driving apparatus, and display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display an image corresponding to an image signal on a display panel of an image range with an arbitrary aspect ratio, while maintaining the aspect ratio of the image, in a liquid crystal display apparatus of a dot sequential drive system. <P>SOLUTION: During a mode in which a narrow image is displayed on an effective image area in a wide panel by maintaining roundness, a frequency of each horizontal scanning clocks for the effective image area and a non-effective image area is changed by making a frequency dividing ratio of a master clock CLK different for each area. For example, the horizontal scanning clock HCK for dot-sequentially addressing a display pixel in the effective image area is set to an 8fH specification, which is lower than a horizontal scanning clock (6 fH specification) for the non-effective image area for driving in a wide size. At this time, a duty ratio of 50% is maintained at any frequency. The non-effective area is displayed in black by using a video blanking pulse BLK. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display panel (display device body), a driving method and a driving device (pulse signal generation circuit), and a display device (video display system) including a display panel and a driving device. More specifically, the present invention relates to a mechanism for driving a dot sequential drive type active matrix display panel. In particular, the present invention relates to a mechanism for displaying an image corresponding to a video signal on a display panel having an arbitrary aspect ratio while maintaining an aspect ratio (also referred to as an angle of view or an aspect ratio) of the image.

  As a driving method for a display panel in which pixels are arranged in a matrix, for example, a liquid crystal display device (liquid crystal panel), individual pixel electrodes are arranged for each of the pixels, and a thin film transistor (TFT) is provided for each of these pixel electrodes. A so-called active matrix driving method (hereinafter simply referred to as an active matrix type) in which a switching element such as a thin film transistor) is connected to selectively drive pixels is known.

  In an active matrix liquid crystal display device, for example, a TFT substrate on which a thin film transistor is formed as a switching element and a counter substrate on which a color filter, a counter electrode, and the like are overlapped, and a liquid crystal is sealed between these substrates. Is configured. In this liquid crystal panel, liquid crystal orientation is controlled by switching control using thin film transistors and voltage application based on a video signal, and video display is performed by changing light transmittance.

  By the way, in an active matrix liquid crystal panel drive system, generally, a video signal and a horizontal and vertical synchronizing signal (or a composite video signal including horizontal and vertical synchronizing signals) are used as a timing generator (pulse signal generator) and an analog signal. The driver receives the signal and supplies various timing signals from the timing generator and AC video signals from the analog signal driver to the liquid crystal panel for display driving.

  In the active matrix type liquid crystal display device, as a driving method thereof, a line sequential method for displaying an image by line sequential scanning driving and a dot sequential method in which each pixel is sequentially driven pixel by line (one row). There is a drive system.

  On the other hand, some display panels have various aspect ratios. Typical examples are 3 (vertical): 4 (horizontal) narrow size (hereinafter also referred to as narrow panel), which is generally used in conventional television systems, and high definition standards. 9 (vertical): 16 (horizontal) wide size (hereinafter also referred to as a wide panel).

  Here, when displaying on a narrow panel based on a 3: 4 narrow image signal or displaying on a wide panel based on a 9:16 wide image signal, the aspect ratio of the original image is maintained as it is. However, if the relationship between the panel size and the image signal size collapses, the aspect ratio of the original image cannot be maintained when simply displayed. For example, if an attempt is made to display on a wide panel wider than the video signal based on a 3: 4 video signal, the displayed video will be a horizontally extended video.

  In order to solve this problem, in order to display a video signal of 3: 4 on a wide panel, it is converted to an aspect ratio of 3: 4. In addition, display is made at a certain signal level such as a black frame in the areas at both ends, which is the remaining area, so as not to give the viewer a sense of incongruity.

  Various methods have been proposed as a method for realizing such a mechanism. For example, there is a method of adding a signal of a certain level to the left and right of a 3: 4 video signal by video signal processing, squeezing it to a 3: 4 size (compression processing for each horizontal period), and displaying it on a wide panel. . However, this method causes a cost increase because the video signal processing becomes complicated and the circuit scale increases.

  On the other hand, in Patent Documents 1 and 2, when an image is displayed on a wide panel by a dot sequential driving method based on a video signal of 3: 4, the frequency of the master clock is changed by changing the frequency division number of the phase lock loop. By switching the frequency, the horizontal scanning clock frequency at the time of wide display is 0.75 times the horizontal scanning clock of the central display unit, and the horizontal scanning clock of both side black display units is 1.5 times that of the side black. A mechanism for performing 4: 3 display is described. In short, the display screen is divided into a plurality of regions in the row direction of the display pixels, and horizontal scanning clocks having different frequencies corresponding to these regions are set in the shift register.

JP-A-8-289232 Japanese Patent Laid-Open No. 2003-157058

  In Patent Document 3, when an image is displayed on a wide panel by a line-sequential driving method based on a video signal of 3: 4, the display screen is divided into a plurality of regions in the row direction of the display pixels. In response to the above, there is described a mechanism for setting sampling frequencies of different frequencies in the horizontal scanning circuit by switching the frequency division ratio of a reference clock having a predetermined frequency.

JP 2001-337644 A

  However, if the frequency division number of the phase-locked loop is changed as in the mechanisms described in Patent Documents 1 and 2, a 3: 4 video signal and a video signal with a wide angle of view wider than that are obtained. When switching while the video is displayed, the phase lock loop is momentarily unlocked, which may cause image disturbance. In addition, the frequency of the master clock is reduced, so that a certain level of signal is displayed in the left and right invalid video areas, and a period that can be used for control signals for video display devices, that is, blanking outside the valid video area. The period will be reduced.

  On the other hand, in the mechanism described in Patent Document 3, since the sampling frequency is changed by switching the division ratio while keeping the frequency of the reference clock corresponding to the master clock constant, the lock of the phase lock loop is performed. Does not happen. However, the mechanism described in Patent Document 3 is for the line-sequential driving method, and there is a problem if the mechanism is applied to the point-sequential driving method as it is.

  For example, the division ratio cannot be switched while maintaining the duty ratio of the horizontal scanning clock at 50%. If the duty ratio of the horizontal scanning clock cannot be maintained at 50%, when writing a video signal to a pixel at each logical level of the horizontal scanning clock, a difference in display time occurs between adjacent pixels, resulting in bright and dark stripes. Resulting in.

  Another method is to have multiple phase-lock loop division counters, so that the phase-lock loop is virtually the same as the angle of view of the corresponding video signal, and the master clock to be used is the video signal. A method to cope with by selecting according to the angle of view is also conceivable. However, this method has a plurality of phase lock loops such as a plurality of multi-bit counters in the frequency division counter of the phase lock loop, which increases the circuit scale.

  The present invention has been made in view of the above circumstances, and even when a video signal is written to a pixel at each logical level of a scanning clock in a dot sequential driving method, an image corresponding to the video signal It is an object of the present invention to provide a simple mechanism for displaying on a display panel having an angle of view of an arbitrary aspect ratio while maintaining the aspect ratio of the image.

  In the present invention, the frequency of the scanning clock for addressing the display pixels in the effective image area having the aspect ratio X: Z (Z <Y) in the display screen having the aspect ratio X: Y is set to the effective image area. The display pixels in the invalid video area except for are set lower than the frequency of the scanning clock for addressing dot-sequentially. At this time, the duty ratio is kept the same at any frequency. A typical example of the duty ratio is 50% in the case of the dot sequential driving method in which writing is performed with both H / L of the binary (H / L) scanning clock.

  Here, a typical example to which the above-described control mode is applied is a horizontal direction when a 3 (vertical): 4 (horizontal) video is displayed in a 9 (vertical): 16 (horizontal) display panel. Regarding scanning (horizontal shift operation), the relationship between X and Y or Z is relative, and it is free to decide which is vertical and which is horizontal. That is, in the present invention, as long as the above relationship is maintained, the relationship between the display panel and the video size displayed on the display panel can take various forms. For example, it may be a case where a video having a narrow horizontal size is displayed in a wide screen or a video having a narrow vertical size displayed in a wide screen. When the 9 (vertical): 16 (horizontal) video is displayed in the 3 (vertical): 4 (horizontal) display panel, the above-described control mode is applied to the vertical scanning (vertical shift operation). Can do.

  The inventions described in the dependent claims define further advantageous specific examples of the present invention. For example, when switching the frequency for each region while maintaining the same duty ratio, the output signals of the common oscillator may be divided by different frequency division ratios. In other words, without changing the frequency division number of the phase lock loop, the master clock that is the output signal of the oscillator is kept at a constant frequency, and the division ratio of the master clock is set so that the effective video area is more effective than the invalid video area. Just make it bigger. By switching the frequency of the scanning clock to be slower in the effective video area than in the invalid video area while maintaining the master clock at a constant frequency, video display on the display panel is possible when switching video display with different aspect ratios. It is possible to switch without causing image distortion even if the image is kept.

  According to the present invention, since the scanning clock is switched between the effective video area and the invalid video area while maintaining the duty ratio, the video signal is written to the pixel at each logical level of the scanning clock in the dot sequential driving method. Even when the image is displayed, the image panel corresponding to the video signal is maintained with the aspect ratio of the image maintained, that is, the display panel with an arbitrary aspect ratio without breaking the roundness of the original video. Can be displayed. It is only necessary to switch the frequency of the scanning clock for each video while maintaining the duty ratio, and the circuit configuration is simple as compared with the case of dealing with video signal processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overall configuration of liquid crystal display device>
FIG. 1 shows an overall configuration of an embodiment of a liquid crystal display device using, for example, a liquid crystal cell as an electro-optical element, in which an embodiment of a driving device (pulse signal generation circuit) according to the present invention is applied to a driving signal generator. FIG.

  As shown in FIG. 1, the liquid crystal display device 1 is arranged so that a plurality of display pixels P constitute an effective video area having an aspect ratio of X: Y (for example, 9:16), which is a display aspect ratio. The display panel unit 100 includes a drive signal generation unit 200 that is an example of a panel control unit that generates various pulse signals for driving and controlling the display panel unit 100, and a video signal processing unit 300. The drive signal generation unit 200 and the video signal processing unit 300 are built in a one-chip IC (Integrated Circuit).

  In the display panel unit 100, a pixel array unit 103, a vertical driving unit 105, a horizontal driving unit 106, a level shifter unit (L / S) 107, a terminal unit (pad unit) 108 for external connection, and the like are integrated on a substrate 102. Is formed. That is, peripheral drive circuits such as a vertical drive unit 105, a horizontal drive unit 106, and a level shifter unit 107 are formed on the same substrate 102 as the pixel array unit 103.

  As an example, the pixel array unit 103 is driven by the vertical drive unit 105 from one or both sides in the horizontal direction shown in the figure, and is driven by the horizontal drive unit 106 from one side or both sides in the vertical direction shown in the figure. Yes.

  Various pulse signals are supplied to the terminal unit 108 from the drive signal generation unit 200 arranged outside the liquid crystal display device 1. Similarly, the video signal Vsig is supplied from the video signal processing unit 300.

  As an example, as a vertical drive pulse signal, in addition to a shift start pulse IN which is an example of a vertical write start pulse, a vertical scan clock VCK and a vertical scan clock xVCK (a logically inverted version of VCK), a standby signal Necessary pulse signals such as STB (or xSTB obtained by logically inverting STB) and enable pulse EN are supplied. Further, as a horizontal drive pulse signal, a horizontal start pulse HST which is an example of a horizontal write start pulse, a horizontal scan clock HCK, and a horizontal scan clock xHCK (HCK logically inverted from the horizontal scan clock HCK). Etc.) are supplied. Note that the vertical scanning clock xVCK and the standby signal xSTB may be generated by logically inverting the vertical scanning clock VCK and the standby signal STB in the vertical drive unit 105. Similarly, the horizontal scanning clock xHCK may be generated by logically inverting the horizontal scanning clock HCK in the horizontal driving unit 106.

  Each terminal of the terminal unit 108 is connected to the vertical driving unit 105 and the horizontal driving unit 106 via the wiring 109. For example, each pulse supplied to the terminal unit 108 is supplied to the vertical drive unit 105 and the horizontal drive unit 106 via a buffer after the voltage level is internally adjusted by the level shifter unit 107. In the illustrated example, only the vertical driving unit 105 is interposed via the level shifter unit 107. The vertical drive unit 105 scans the pixel array unit 103 line-sequentially, and the horizontal drive unit 106 writes an image signal in the pixel array unit 103 in synchronization with this.

  Although not shown, the pixel array unit 103 has a panel structure including a pair of substrates 102 and a liquid crystal held between them. For example, pixels including pixel transistors and the like are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (driving side substrate), and scanning lines are wired for each row with respect to this pixel array. In addition, a signal line is wired for each column. The first glass substrate is disposed to face the second glass substrate (opposite side substrate) with a predetermined gap, and is bonded together with a sealant (not shown). Then, the liquid crystal material is sealed in a region inside the position of the sealant.

  In the pixel array unit 103, scanning lines (gate lines) 12 and signal lines (data lines) 14 are formed. A pixel electrode and a thin film transistor (TFT) for driving the pixel electrode are formed at the intersection between the two. A pixel P is composed of a combination of a pixel electrode and a thin film transistor.

  Although details are omitted, the gate electrode of the thin film transistor is connected to the corresponding scanning line 12, the drain region is connected to the corresponding pixel electrode, and the source region is connected to the corresponding signal line 14. The scanning line 12 is connected to the vertical driving unit 105, while the signal line 14 is connected to the horizontal driving unit 106.

  The vertical drive unit 105 sequentially selects each pixel P via the scanning line 12 based on the vertical drive system pulse signal supplied from the drive signal generation unit 200. The horizontal drive unit 106 writes an image signal to the selected pixel P via the signal line 14 based on the horizontal drive system pulse signal supplied from the drive signal generation unit 200.

  Here, the horizontal driving unit 106 is configured by a shift register, a precharge circuit, a sampling switch (horizontal switch), and the like, and a video signal for each pixel P in a row selected by the vertical driving unit 105 in a pixel unit. Write. That is, in this embodiment, dot sequential driving is performed in which a video signal is written in units of pixels for each pixel P in the selected row. In addition, when writing video signals in pixel units by dot sequential driving, writing is performed in both the H and L periods of the horizontal scanning clock HCK for controlling writing to the pixels, that is, in the half clock period of the horizontal scanning clock HCK. To reduce the writing time.

  The vertical drive unit 105 includes a combination of logic gates (including latches), and selects each pixel P of the pixel array unit 103 in units of rows. 1 shows a configuration in which the vertical drive unit 105 is disposed only on one side of the pixel array unit 103, but a configuration in which the vertical drive unit 105 is disposed on both the left and right sides of the pixel array unit 103 is employed. Is also possible.

  Similarly, FIG. 1 shows a configuration in which the horizontal drive unit 106 is disposed only on one side of the pixel array unit 103, but a configuration in which the horizontal drive unit 106 is disposed on both upper and lower sides with the pixel array unit 103 interposed therebetween is employed. It is also possible.

  Although details will be described later, the drive signal generation unit 200 of the present embodiment is included in a relatively wide display screen (hereinafter also referred to as a wide screen) having an aspect ratio (aspect ratio) X: Y (for example, 9:16). In order to display an image having an aspect ratio of X: Z (Z <Y: for example, 3: 4) (hereinafter also referred to as a narrow image) without breaking the roundness, the frequency of various pulse signals of the horizontal drive system is wide. It is characterized in that it is configured to switch between an effective video area that is an area for displaying a narrow image in the screen and an invalid video area that is an area other than the effective video area in the wide screen.

  Further, the frequency switching is characterized in that pulse signals for different regions are generated at different frequencies based on one reference clock signal generated by a PLL circuit or the like. In particular, the horizontal scanning clock HCK for controlling writing to the pixels is characterized in that the duty ratio is maintained at about 50% even when the frequency is switched. In this embodiment, when writing a video signal in pixel units by dot sequential driving, the writing time is shortened by writing in both the H period and the L period of the horizontal scanning clock HCK. Even when the frequency is switched, the duty ratio is maintained at about 50%, so that display unevenness due to different writing times between adjacent pixels in the same region does not occur.

  Also, when displaying a narrow image in a wide screen, a display mode in which the narrow image is displayed in the center of the wide screen, a display mode in which the narrow image is displayed on the left, or a display mode in which the narrow image is displayed on the right is adopted. Can do. For the invalid video area excluding the narrow image, so-called blanking processing is performed so that an unobtrusive image is not displayed and output.

<Outline of dot sequential drive method>
FIG. 2 shows an active matrix liquid crystal display device 1 in which a liquid crystal cell is used as a display element (electro-optical element) of a pixel, in which a clock drive system is adopted as a horizontal drive circuit of a dot sequential drive system. It is a figure which shows the example of a structure. The horizontal drive unit 106 sequentially samples the input video signal Vsig every 1H, and performs processing for writing to each pixel P selected in units of rows by the vertical drive unit 105. In FIG. Is configured to include a horizontal transfer processing unit 161, a clock extraction switch group 162 as a changeover switch group, and a sampling switch group 163.

  For example, when the horizontal transfer processing unit 161 is configured to perform simultaneous writing by dividing the pixel P of the pixel array unit 103 into a plurality of blocks in the horizontal direction, the number of horizontal pixels / the number of simultaneous samplings of the pixel array unit 103 (for example, If the number of horizontal pixels is 1024 and 12 dots simultaneous sampling, it is composed of 1024/12 = 85 remainders (86, which is 86), and a horizontal start pulse HST supplied from the drive signal generator 200 is given. Then, the shift operation is performed in synchronization with the horizontal scanning clocks HCK and xHCK of opposite phases supplied from the drive signal generation unit 200.

  The shift stage is provided with a latch circuit (shift register) composed of transfer switches, D-type flip-flops, etc., and a number of stages corresponding to the total number of columns of pixels is connected in multiple stages to form a shift register group. Is done. A horizontal start pulse HST is transferred for each stage to perform dot sequential addressing of pixels.

  Thereby, from each shift stage of the horizontal transfer processing unit 161, shift pulses Vs1 to Vsn having the same pulse width as the period of the horizontal scanning clocks HCK and xHCK are sequentially output for each half clock of the horizontal scanning clocks HCK and xHCK. . These shift pulses Vs1 to Vsn are given to the switches 162-1 to 162-n of the clock sampling switch group 162.

  One end of each of the switches 162-1 to 162-n of the clock sampling switch group 162 is alternately connected to the clock lines 164-1 and 164-2 for inputting the horizontal scanning clocks HCK and xHCK, and the horizontal transfer processing unit 161 is connected. When the shift pulses Vs1 to Vsn are applied from the respective shift stages, the horizontal scanning clocks HCK and xHCK are sequentially extracted in the ON state. These extracted pulses are given to the switches 163-1 to 163-n of the sampling switch group 163 as sampling pulses Vh1 to Vhn.

  One end of each of the switches 163-1 to 163-n of the sampling switch group 163 is connected to the video line 165 for transmitting the video signal Vsig supplied from the video signal processing unit 300, and the switch 162 of the clock sampling switch group 162 is connected. The video signal Vsig is sampled by sequentially turning on in response to sampling pulses Vh1 to Vhn extracted and sequentially applied at -1 to 162-n, and the pixel array unit 103 (not shown; see FIG. 1) To the signal lines 114-1 to 114-n. That is, when the sampling pulses Vh1 to Vh4 are given from the horizontal transfer processing unit 161, the video signal Vsig input through the video line 165 is sequentially sampled by sequentially turning on in response to the sampling pulses Vh1 to Vh4. 1 to 114-n.

  When the liquid crystal display device 1 is used for color image display, a video line 165 corresponding to each color of red, green, and blue is provided, and the analog video signal Vsig-B for each color is provided on the video line 165 corresponding to each color. Vsig-R and Vsig-G are supplied independently to perform simultaneous writing to the three pixels of red, green and blue.

  Note that the configuration example of the horizontal transfer processing unit 161 and the sampling switch groups 162 and 163 shown here is merely an example, and at least a configuration capable of writing a video signal to the pixel P at each logical level of the horizontal scanning clock HCK. It only needs to be provided, and various changes are possible. Of course, it is not essential that the pixel P of the pixel array unit 103 is divided into a plurality of blocks in the horizontal direction for simultaneous writing.

<Schematic configuration of drive signal generator>
3 and 4 are diagrams for explaining the overall outline of the drive signal generation unit 200 that is a characteristic part of the liquid crystal display device 1 of the present embodiment. Here, FIG. 3 is a block diagram showing an overall outline of the drive signal generation unit 200. FIG. 4 is a diagram illustrating an example of a display mode when a narrow screen is displayed in a wide screen by various pulse signals of the horizontal scanning system generated by the drive signal generation unit 200.

  As shown in FIG. 3, the drive signal generation unit 200 of the present embodiment generates a PLL circuit 210 that generates a master clock CLK based on an input horizontal synchronization signal Hsync, and various pulse signals of the horizontal scanning system. A horizontal scanning system pulse signal generation unit 220 and a vertical scanning system pulse signal generation unit (an example of a vertical scanning clock generation unit) 230 that generates various pulse signals of the vertical scanning system are provided.

  The PLL circuit 210 includes a voltage controlled oscillator (VCO) 212, a loop filter 214, a phase comparison unit (P / C) 216, and a counter (in particular, also referred to as a PLL counter) 218. The voltage controlled oscillator 212 generates a master clock CLK having a frequency corresponding to the voltage signal supplied to the voltage control input terminal, and supplies the master clock CLK to the PLL counter 218. The PLL counter 218 divides the master clock CLK, which is a reference clock signal, by counting the number of clocks equal to the number of pixels for one row, and sends the internal horizontal synchronization pulse inthd, which is a reference horizontal signal, to the phase comparison unit 216. Supply.

  The phase comparison unit 216 is supplied with the internal horizontal synchronization pulse inthd divided by the PLL counter 218 and the horizontal synchronization signal Hsync from the previous stage. The phase comparator 216 detects the phase difference between the two pulse signals inthd and Hsync, and supplies a voltage signal representing the detected phase error to the loop filter 214. The loop filter 214 generates a signal voltage obtained by removing high frequency components and noise from the error signal obtained from the phase comparison unit 216 and supplies the signal voltage to the voltage control input terminal of the voltage controlled oscillator 212. The master clock CLK and the internal horizontal synchronization pulse inthd generated by the PLL circuit 210 are supplied to the horizontal scanning system pulse signal generation unit 220.

  In the PLL circuit 210 having such a configuration, when the horizontal synchronization signal Hsync is input to the phase comparison unit 216, the phase comparison unit 216 divides the master clock CLK generated by the PLL counter 218 to a clock having an Hsync cycle. The phase is compared with the rounded internal horizontal sync pulse inthd. The phase comparison unit 216 adjusts the oscillation frequency of the master clock CLK by inputting the phase comparison result to the voltage control input terminal of the voltage controlled oscillator 212 oscillating the master clock CLK via the loop filter 214. . As a result, the horizontal synchronization signal Hsync and the internal horizontal synchronization pulse inthd can be synchronized. In this embodiment, the oscillation frequency of the master clock CLK is set to be six times the horizontal scanning clock HCK frequency for displaying a video on a desired video display device.

  The horizontal scanning system pulse signal generation unit 220 includes a horizontal driving system pulse generation unit (an example of a horizontal scanning clock generation unit) 400 that generates a horizontal driving system pulse signal, and a video sample pulse that generates a pulse signal of the video signal processing system. A generation unit (an example of a video sample signal generation unit) 500.

  The horizontal drive system pulse generation unit 400 is based on the master clock CLK supplied from the voltage controlled oscillator 212 of the PLL circuit 210 and the internal horizontal synchronization pulse inthd supplied from the PLL counter 218, to the horizontal drive unit 106 of the display panel unit 100. A binary (L / H) pulse signal for controlling the signal is generated. As an example, the horizontal scanning clock HCK and the horizontal start pulse HST are generated at a predetermined timing in synchronization with the master clock CLK. In particular, with respect to the horizontal scanning clock HCK, the duty ratio is always maintained at 50%.

  The phase of the horizontal scanning clock HCK and the horizontal start pulse HST is set to a wide mode for displaying on a wide screen (for example, aspect ratio 9:16) based on a wide image signal, or to a narrow image signal (for example, an aspect ratio of 3: 4 to a wide screen). ) Based on the narrow mode to be displayed on the basis of (). Preferably, the phase can be finely adjusted based on the horizontal display control pulse phase control pulse P12.

  The vertical scanning system pulse signal generation unit 230 generates a vertical start pulse VST in synchronization with the horizontal start pulse HST supplied from the horizontal drive system pulse generation unit 400 for each frame period based on a vertical timing signal supplied from the outside. When generated, a vertical scanning clock VCK is generated for each horizontal scanning period, and these are supplied as control signals to the vertical driving unit 105 of the display panel unit 100.

  The video sample pulse generation unit 500 generates a binary (L / H) pulse signal for controlling the video signal processing unit 300 based on a predetermined control pulse generated by the horizontal drive system pulse generation unit 400. To do. As an example, video sample pulses SH1 to SH4 are generated at a predetermined timing in synchronization with the master clock CLK.

  The phase of the video sample pulses SH1 to SH4 is based on a wide mode for displaying on a wide screen (eg, aspect ratio 9:16) based on a wide video signal, or on a wide screen based on a narrow video signal (eg, aspect ratio 3: 4). In accordance with the narrow mode to be displayed, the phase is switched to each preset phase. Preferably, the phase can be finely adjusted based on the SH pulse phase control pulse P14.

  Further, the horizontal scanning system pulse signal generation unit 220 includes a video blanking pulse generation unit 600 that generates a video blanking pulse BLK for invalidating an image signal in an invalid video region, and an invalid video region during a narrow image display operation. A switching control pulse generation unit 700 is provided that generates a control pulse P11 for switching the frequency of various pulse signals between the effective video area.

  The video blanking pulse generation unit 600 is provided as a configuration specific to the present embodiment, and is a video switching control signal generation unit that generates a video switching control signal for outputting a certain level of video to the invalid video region. It is an example. The video blanking pulse generator 600 generates a video blanking pulse BLK that invalidates image information in an invalid video area excluding the valid video area when a narrow screen is displayed in the valid video area at a predetermined position in the wide screen. Based on a predetermined control pulse generated by the horizontal drive system pulse generator 400, it is generated at a predetermined timing in synchronization with the master clock CLK.

  Here, the video blanking pulse generation unit 600 outputs an active H video blanking pulse BLK at a predetermined position in the horizontal period corresponding to the invalid video area when a narrow image is displayed, while the video blanking pulse generator 600 outputs a video blank when displaying a wide image. The ranking pulse BLK is always inactive (= L). The video blanking pulse BLK is supplied to the video signal processing unit 300. In the video signal processing unit 300, the video signal level of the invalid video region corresponding to the period during which the video blanking pulse BLK is active is set to a constant level.

  The phase of the video blanking pulse BLK is based on a wide mode for displaying on a wide screen (eg, aspect ratio 9:16) based on a wide video signal, or on a wide screen based on a narrow video signal (eg, aspect ratio 3: 4). The phase is switched to a preset phase according to the narrow mode to be displayed. Preferably, the phase can be finely adjusted based on the BLK active position control pulse P16.

  The switching control pulse generator 700 is horizontally driven so as to generate various pulse signals with timing and frequency according to the display aspect ratio based on the display aspect ratio switching control pulse P10 (display mode signal) supplied from the outside. The system pulse generator 400 and the video sample pulse generator 500 are controlled.

  Correspondingly, the horizontal drive system pulse generation unit 400 and the video sample pulse generation unit 500 have a wide image display as shown in FIG. Wide pulse generation function unit for generating operation pulse signals (with reference child -WD) and narrow pulse generation function unit for generating narrow image display operation pulse signals (with reference child -NR) individually Have. In addition, a switching unit 730 that switches between a pulse signal for wide image display operation and a pulse signal for narrow image display operation based on a control pulse P11 generated by the switching control pulse generation unit 700 is provided. It should be noted that the arrangement position of the switching unit 730 shown here is in principle, and depending on the circuit configuration of the horizontal drive system pulse generation unit 400 and the video sample pulse generation unit 500, it appropriately enters the inside thereof. Can be provided.

  Here, in the present embodiment, in the narrow mode in which the narrow screen is displayed on the wide screen based on the narrow video signal, a round image with a roundness ratio of “1” is applied to a narrow image having an aspect ratio of 3: 4 or the like in the effective video area in the wide screen. The auxiliary image can be displayed in the invalid video area which is the remaining area. For this reason, in the narrow pulse generation function unit, a pulse signal having a frequency lower than the frequency of the pulse signal generated by the wide pulse generation function unit is generated in advance. That is, the frequency of the pulse signal of the horizontal scanning system of the effective video area is set lower than that of the other invalid video areas.

  Then, based on the control pulse P11 generated by the switching control pulse generation unit 700, the switching unit 730 generates a pulse signal having a frequency corresponding to a wide frequency generated by the wide pulse generation function unit (of the reference element -WD) The frequency of the pulse signal is switched between the effective video area and the invalid video area by switching the pulse signal having a frequency lower than that of the wide correspondence generated by the narrow pulse generation function unit (with reference element -NR). To.

  In this way, instead of changing the frequency of the master clock CLK, the horizontal drive frequency (frequency of the horizontal scanning clock HCK) of the video display device is switched between the effective video area and the other invalid video area, that is, one horizontal scan. You can switch within the period. In conjunction with switching the frequency of the horizontal scanning clock HCK between the effective video area and the other invalid video area, the horizontal scanning clock HCK also relates to the pulse signal (video sample pulse SH in this example) of the video signal processing system. The frequency is switched within one horizontal scanning period at the same timing as the frequency switching.

  As a result, as shown in the center of the screen in FIG. 4B, for example, based on a narrow video signal of 3: 4, an image display device having a wider angle of view (for example, 9:16) than the narrow video signal. It will be possible to display normally without breaking the roundness. When a shift operation is performed with a horizontal scanning clock HCK having a certain frequency, as shown in FIG. 4A, when a 3: 4 video enters a 9:16 wide panel, the horizontal direction is 4 / As a result of being stretched three times, a horizontally extended video display is made on the entire 9:16 screen. On the other hand, in the present embodiment, since the display control is performed by reducing the frequency of the pulse signal of the horizontal scanning system only in the effective image area, the 3: 4 image enters the 9:16 wide panel. In this case, the horizontal direction can be displayed by being compressed to 3/4 times, and the roundness of the narrow image displayed in the wide screen can be maintained.

  As shown in the left and right parts of the screen in FIG. 4B, the invalid video area excluding the valid video area does not obstruct the display of useless images. It is better to display the video. For this reason, the video blanking pulse BLK is used to replace the video signal in the period excluding the 3: 4 video display period with a signal of a certain level and display in the invalid video area of the video display device. For example, left and right black frame writing is performed during the blanking period before the start of the effective video area, and the horizontal scanning clock HCK2 switches the frequency at the boundary between the black frame writing unit and the effective video area.

  At this time, the video signal processing unit 300 sets the video signal Vsig to a certain level (for example, black) → effective video (for a narrow image) → a certain level (for example, black) in advance, and on the display panel unit 100 side. This can be dealt with by sequentially shifting the horizontal start pulse HST from either the left or right side.

  Alternatively, the shift operation in the horizontal transfer processing unit 161 of the display panel unit 100 can be performed independently for the effective video area and the invalid video area, thereby performing processing on the video signal Vsig itself. It can be dealt with without any problems. In this case, as an example, as shown in the upper part of the outside of the screen of FIG. 4B, the invalid video area is displayed sequentially from both sides at the same time, while the valid video area is left (or right) invalid. It is possible to perform control so that display is performed by dot sequential driving after the end of writing of the video area. This point will be described later.

<Timing of pulse signal>
FIG. 5 shows the relationship between the horizontal start pulse HST and the horizontal scanning clock HCK and the video sample pulses SH1 to SH4 generated by the drive signal generation unit 200 of the present embodiment, the clock signal master clock CLK, and the horizontal synchronization signal Hsync. It is an example of a timing chart. FIG. 6 is a partial detail view of FIG. FIG. 7 is an example of a timing chart of a conventional pulse signal as a comparative example.

  In the narrow image display operation, in FIG. 5, the frequency switching position t12 of the horizontal scanning clock HCK from the reset position t10 of the horizontal scanning clock HCK corresponds to the invalid video area, and the control pulse P11 generated by the switching control pulse generation unit 700 is displayed. Set by

  The switching unit 730 performs switching operation between the pulse signal generated by the wide pulse generation function unit and the pulse signal generated by the narrow pulse generation function unit based on the control pulse P11. As a result, the active period of the horizontal start pulse HST is set to the start point of the effective image area on the wide screen during the wide image display operation, but from the signal replacement period of a certain level (t11 in FIG. 5) during the narrow image display operation. Set to the front. As a result, it is possible to display a signal at a certain level (for example, a black level) also in the invalid video area in front of the effective video area start position (frequency switching position t12) of the video display device.

  Further, since the horizontal scanning clock HCK and the video sample pulse SH are selected in the period t10 to t12, the pulse signal generated by the wide pulse generation function unit is selected. Display control is performed. On the other hand, in the period excluding periods t10 to t12, since the pulse signal generated by the narrow pulse generation function unit is selected, display control is performed based on the pulse signal having a frequency lower than the normal frequency. Note that only the horizontal scanning system performs frequency switching, and the vertical scanning system does not need to perform frequency switching.

  For example, in the period excluding periods t10 to t12, the horizontal scanning clock HCK has a low frequency with the duty ratio maintained at 50%, and the video sample pulse SH is output in accordance with the horizontal scanning clock HCK having a low frequency. Is done. Further, the horizontal start pulse HST becomes active at a position close to the horizontal synchronization signal Hsync for a signal display period of a certain level with respect to the wide image display operation.

  Further, the video blanking pulse BLK becomes active H at least from the reset position t10 of the horizontal scanning clock HCK to the frequency switching position t12 of the horizontal scanning clock HCK. In this embodiment, in order to arrange invalid video areas on both the left and right sides of the effective video area, the invalid video areas are slightly wider than that, and the horizontal scanning is performed from a position t14 before the reset position t10 of the horizontal scanning clock HCK. The period between the frequency switching position t12 of the clock HCK is active H, and the actual invalid video area becomes wider than the theoretical invalid video area on the time axis. During the wide image display operation, the video blanking pulse BLK is fixed at the L output.

  Which timing is assigned to pixel writing at a constant signal level (for example, black level) during the period in which the video blanking pulse BLK is active H can be dealt with only by video signal processing, or a shift in the display panel unit 100 It may be determined by how the pulses are handled. As an example, as shown in the upper part of the screen of FIG. 4B, when writing at a constant signal level (for example, black level) from both the left and right sides of the panel surface, writing is performed simultaneously from left to right of t11 in FIG. When t12 is reached, the writing on the right side of the panel surface is stopped, and the writing on the left side of the panel surface is shifted to writing a narrow image in the effective video area. In this case, the invalid video area is formed in the same size on the left and right of the effective video area on the display panel unit 100. If the left and right stop timings are different, the left and right invalid video areas can be formed in different sizes. Further, at this time, by adjusting the left and right stop timings to be different so as to maintain the same size of the effective video area, the position of the effective video area on the display panel unit 100 is maintained while maintaining the same size. Can be adjusted.

  More specifically, when outputting a pulse signal for projecting a 3: 4 image on a 9:16 wide panel when the display aspect ratio switching control pulse P10 is in the L level narrow mode, as shown in FIG. For the invalid video region in principle from the reset position t10 of the horizontal scanning clock HCK to the frequency switching position t12 of the horizontal scanning clock HCK, there are six horizontal scanning clocks HCK as the master clock CLK (for example, frequency = 20.0 MHz). Minute (referred to as 6fH specification). That is, the reset position t10 of the horizontal scanning clock HCK is set as the FRP inversion position, and after the reset position t10, 1HCK = 6 fH is output. By doing so, the frequency of the horizontal scanning clock HCK becomes about 3.3 MHz. The duty ratio of the horizontal scanning clock HCK at the time of 6 fH specification is 50%.

  The FRP inversion position is a switching position when performing 1H (one horizontal scanning period) inversion driving. Here, 1H inversion driving means that the polarity of the video signal is inverted every horizontal period, and the display is reversed in polarity between the odd and even lines, thereby canceling out the flicker, and the entire display screen is flickering. This is a driving system that provides a display without any problem.

  Further, after the frequency switching position t12 of the horizontal scanning clock HCK, the effective video area has a frequency division ratio of the master clock CLK in the invalid video area in order to reduce the frequency of the pulse signal of the horizontal scanning system to 3/4 times. To be bigger than. Specifically, one horizontal scanning clock HCK is set to eight master clocks CLK (referred to as 8fH specifications). That is, after the frequency switching position t12, the signal is output at 1HCK = 8fH. By doing so, the frequency of the horizontal scanning clock HCK becomes 2.5 MHz. By assigning four master clocks CLK to each logical level of the horizontal scanning clock HCK, the duty ratio of the horizontal scanning clock HCK can be maintained at 50% even in the 8fH specification.

  Further, when the frequency of the horizontal scanning clock HCK is switched within one horizontal scanning period, the pulse signals of other horizontal scanning systems are also switched within one horizontal scanning period at the same timing as the frequency switching of the horizontal scanning clock HCK. Switch the frequency. For example, with respect to the video sample pulse SH, before the frequency switching position t12 of the horizontal scanning clock HCK, as in the wide mode, the half clock (= 3CLK) of the horizontal scanning clock HCK is divided into three to obtain the video sample pulse SH. To do. As an example, the video sample pulse SH2 is always at the H level, and the remaining video sample pulses SH1, SH3, and SH4 are each given an H level of 1 CLK. Further, after the frequency switching position t12, the video sample pulse SH is output to an approximate position obtained by dividing the half clock (= 4CLK) of the horizontal scanning clock HCK into three using the reverse phase of the master clock CLK, thereby obtaining the 8fH specification.

  As described above, according to the drive signal generation unit 200 of the present embodiment, based on one reference clock generated by the PLL circuit 210, a normal frequency pulse signal for a wide image display operation and a narrow image display operation Since a pulse signal having a frequency lower than the normal frequency is selectively generated, even if switching is performed while the image is displayed, image disturbance does not occur. Further, since the frequency of the master clock CLK is not lowered to switch between the wide image display operation and the narrow image display operation, the period of the video blanking pulse BLK for displaying a constant level signal in the invalid video area is small. It will never be.

  Also, with respect to the horizontal scanning clock HCK, since the frequency is switched while maintaining the duty ratio at 50%, the video signal is transmitted to the pixel at each logical level of the binary horizontal scanning clock HCK by the dot sequential driving method. In writing, even if the frequency is switched, there is no difference in display time between adjacent pixels.

  Further, each pulse signal for wide image display operation and narrow image display operation is generated based on one reference clock generated by the PLL circuit 210, and it is not necessary to have a plurality of PLL circuits. The circuit scale of the circuit is not increased. The functional unit for generating each pulse signal for wide image display operation and narrow image display operation, and the functional elements for switching each pulse signal may have a relatively simple configuration such as a decoder, flip-flop, or selector. However, the circuit scale can be reduced as compared with the case where a plurality of PLL circuits are provided.

<Schematic configuration of video signal processing circuit>
FIG. 8 is a block diagram showing an overall outline of the video signal processing unit 300 in the liquid crystal display device 1 of the present embodiment.

  The video signal processing unit 300 displays three color image signals S0-R, -G, B of red (Red), green (Green), and blue (Blue) to be displayed in order to display a color image on the liquid crystal display device 1. For each of the above, a blacking process is performed based on the video blanking pulse BLK generated by the video blanking pulse generation unit 600 of the horizontal scanning system pulse signal generation unit 220, thereby displaying an auxiliary image in the invalid video area. A blanking circuit 302 is provided. Although not shown, the video blanking circuit 302 is provided for each of red, green, and blue. The video blanking circuit 302 sets the video signal level of the invalid video area corresponding to the active period of the video blanking pulse BLK to a certain level (typically black level).

  In this way, information of a certain level (typically black level) can be added to the portion (typically left and right) excluding the effective video portion of 3: 4. In the display panel section 100, the horizontal start pulse HST is shifted in order from one of the left and right, so that it is possible to display at a certain level (for example, black) → effective image → a certain level (for example, black).

  The video blanking circuit 302 has a configuration necessary when the horizontal transfer processing unit 161 of the display panel unit 100 shifts the horizontal start pulse HST in order from one of the left and right. This is not always necessary depending on the configuration of the processing unit 161.

  The video signal processing unit 300 includes a first sample hold circuit 310R, 310G, and 310B for each of the three video signals of red, green, and blue output from the video blanking circuit 302. 310 and a second sample-and-hold unit 320 having second sample-and-hold circuits 320R, 320G, and 320B for each of three video signals of red, green, and blue.

  In each of the first sample and hold circuits 310R, 310G, and 310B of the first sample and hold unit 310, the corresponding video sample pulses SH1 (for red), SH2 (for green), and SH3 (for blue) are driven signal generation unit 200. Are supplied independently from each other. The fourth video sample pulse SH4 is commonly supplied from the drive signal generation unit 200 to the second sample hold circuits 320R, 320G, and 320B of the second sample hold unit 320.

  The first sample hold circuits 310R, 310G, 310B and the second sample hold circuits 320R, 320G, 320B sample the input analog signal potential during the active (High) period of each video sample pulse SH1 to SH4, During the inactive (Low) period, the sampled signal potential is held. The analog video signals Vsig-B, Vsig-R, and Vsig-G of each color output from the second sample hold unit 320 are supplied to the video lines 165 corresponding to the colors of the display panel unit 100.

  Here, in order to display an image on the liquid crystal display device 1 based on the input video signal, the horizontal start pulse HST, the horizontal scanning clock HCK, and the video sample pulse shown in the timing charts of FIGS. The horizontal direction control of the video signal displayed on each pixel is performed by SH1 to SH4.

  The horizontal start pulse HST becomes control data for the horizontal transfer processing unit 161 used for horizontal display control of the liquid crystal display device 1, and the horizontal scanning clock HCK is used as a clock for the horizontal transfer processing unit 161. Writing to the pixel P is controlled by each output of the horizontal transfer processing unit 161. Therefore, the writing start timing to the pixels can be determined by the horizontal start pulse HST, and the sequential writing period to each pixel P can be determined by the horizontal scanning clock HCK.

  Further, the horizontal display start position of the video can be controlled by the position at which the horizontal start pulse HST is activated (H level in this example) with respect to the horizontal synchronization signal Hsync of the video signal. For example, the drive signal generation unit 200 determines the position where the horizontal start pulse HST becomes active so that the center of the video signal is displayed on the center of the display panel 100 of the liquid crystal display device 1.

  Further, since the horizontal direction of the displayed video can be expanded and contracted by the frequency of the horizontal scanning clock HCK, the horizontal scanning clock HCK can be displayed with the correct aspect ratio of the original source (displayed with a roundness ratio = 1). Need to be frequency.

  Further, when the liquid crystal display device 1 is adapted for color display, blue (Red), red (Red), green (red) using video sample pulses SH1 to SH4 that are one cycle in the half clock period of the horizontal scanning clock HCK. Green) is simultaneously written into the three color pixels.

  The video sample pulses SH <b> 1 to SH <b> 4 are pulses used in a sample and hold system for displaying information on each time for each pixel P of RGB. Here, the half clock period of the horizontal scanning clock HCK is divided into three equal parts, and the video sample pulses SH1, SH2, and SH3 are sampled for the red, green, and blue analog video signals S1-B, S1-R, and S1-G, respectively. Sample hold processing is performed in the first sample hold unit 310 using the hold control pulses independently.

  Thereafter, the video sample pulse SH4 is commonly used as sampling hold control pulses for the red, green, and blue analog video signals S2-B, S2-R, and S2-G, and is output from the first sample hold unit 310. The analog video signal outputs S2-B, S2-R, and S2-G are subjected to sample hold processing (particularly referred to as resampling processing) by the second sample hold unit 320. That is, all video signals of the respective colors B, G, and R are resampled at the timing of the fourth video sample pulse SH4. By supplying the video signals Vsig-B, Vsig-G, and Vsig-R output from the second sample hold unit 320 to the video lines 165 corresponding to the respective colors of the display panel unit 100, three pixels of red, green, and blue Write simultaneously to.

  In the present embodiment, among the four types of video sample pulses SH1, SH2, SH3, and SH4, the green video sample pulse SH2 is always active (= H). For this reason, the green video signal is through.

<First Embodiment of Drive Signal Generation Unit>
FIG. 9 and FIG. 10 are diagrams illustrating the first embodiment of the drive signal generation unit 200 that is a characteristic part of the liquid crystal display device 1 of the present embodiment. In each embodiment described below, a control pulse output from each functional unit is referred to as P @@@ with reference to the functional unit (the illustration may be omitted).

  This first embodiment is provided with a function for adjusting the phase of the horizontal start pulse HST, the horizontal scanning clock HCK, and the video sample pulse SH and an active position adjusting function for the video blanking pulse BLK in the overall outline shown in FIG. This is the most basic of the drive signal generator 200.

  Here, FIG. 9 shows a horizontal drive system pulse generator 400 that generates horizontal drive system pulses with different frequencies for each region and a video sample pulse with different frequencies for each region, which is used in the drive signal generator 200 of the first embodiment. 2 is a block diagram (basic configuration diagram) for explaining basic elements of a video sample pulse generation unit 500 for generating the FIG. 10 is a block diagram (detailed configuration diagram) showing a detailed configuration example of the horizontal drive pulse generator 400, the video sample pulse generator 500, and the video blanking pulse generator 600 in the first embodiment.

  FIG. 9 shows the principle of a circuit that generates a horizontal start pulse HST, a horizontal scanning clock HCK, and a video sample pulse SH. As described with reference to FIG. 3, the master clock CLK and the internal horizontal synchronization pulse inthd are supplied from the PLL circuit 210 to the horizontal drive system pulse generation unit 400 constituting the horizontal scanning system pulse signal generation unit 220. The period of the master clock CLK is set to be six times the horizontal scanning clock HCK frequency during wide image display.

  The horizontal drive system pulse generator 400 constituting the horizontal scanning system pulse signal generator 220 has an H counter 412 that performs an up-count operation based on the master clock CLK.

  The internal horizontal synchronization pulse inthd supplied from the PLL circuit 210 is supplied to the reset input terminal RS of the H counter 412 and is used for reset control of the H counter 412. That is, the H counter 412 counts up for each master clock CLK and is reset by the internal horizontal synchronization pulse inthd.

  The horizontal drive system pulse generator 400 is a functional unit that generates the horizontal start pulse HST, and includes decoders 422 and 424 that generate control pulses hstj and hstk that become active H based on a previously stored decode value, And a JK flip-flop 428 for generating a horizontal start pulse HST based on the control pulses hstj and hstk output from the decoders 422 and 424. The control pulse hstj output from the decoder 422 is supplied to the J input terminal of the JK flip-flop 428, and the control pulse hstk output from the decoder 424 is supplied to the K input terminal of the JK flip-flop 428. Note that the horizontal start pulse HST and the horizontal scanning clock HCK may be synchronized with the master clock CLK by supplying the master clock CLK generated by the PLL circuit 210 to the clock terminal of the JK flip-flop 428.

  With such a configuration, the decoders 422 and 424 generate control pulses hstj and hstk that become active H with the decode value stored in advance with respect to the counter value of the H counter 412, and the decoders 422 and 424 generate these control pulses. A horizontal start pulse HST is generated by the JK flip-flop 428 by the control pulses hstj and hstk thus generated, and an active H horizontal start pulse HST is output from the non-inverting output terminal Q thereof.

  In addition, the horizontal drive system pulse generation unit 400 is a functional unit that generates the horizontal scanning clock HCK, and includes a decoder 432 that generates a control pulse P432 that becomes active H based on a previously stored decode value, an OR gate 434, And an HCK counter 436 that performs an up-count operation based on the master clock CLK.

  Further, the horizontal drive system pulse generation unit 400 is a functional unit that generates the horizontal scanning clock HCK, and includes decoders 442 and 444 that generate control pulses hckj and hckk that become active H based on a previously stored decode value, And a JK flip-flop 428 for generating a horizontal scanning clock HCK based on control pulses hckj and hckk output from the decoders 442 and 444. The control pulse hckj output from the decoder 442 is supplied to the J input terminal of the JK flip-flop 428, and the control pulse hckk output from the decoder 444 is supplied to the K input terminal of the JK flip-flop 428.

  The OR gate 434 receives the control pulse P432 output from the decoder 432 at one input terminal, and receives the control pulse hckk output from the decoder 444 as a feedback input to the other input terminal. The obtained control pulse P434 is output as a control pulse hckrs. That is, the control pulse hckrs is generated by taking the logical sum of the control pulses P432 and hckk generated by the decoder 432 and the decoder 444.

  The OR output P434 of the OR gate 434 is supplied as a control pulse hckrs to the reset input terminal RS of the HCK counter 436 in the next stage and used for reset control of the HCK counter 436. That is, the HCK counter 436 counts up every master clock CLK and is reset by the control pulse hckrs.

  With such a configuration, the decoders 442 and 444 generate the control pulses hckj and hckk that become active H with the decode value stored in advance with respect to the counter value of the HCK counter 436, and the decoders 442 and 444 generate these control pulses. The horizontal scanning clock HCK is generated by the JK flip-flop 428 by the control pulses hckj and hckk, and the active horizontal scanning clock HCK is output from the non-inverting output terminal Q.

  At this time, the horizontal scanning clock HCK is reset once per horizontal period by the decoder 432, and one clock time of the horizontal scanning clock HCK is determined by the decoder 444. The decoder 444 is set so that one clock of the horizontal scanning clock HCK is equivalent to six clocks of the master clock CLK.

  Furthermore, the video sample pulse generation unit 500 constituting the horizontal scanning system pulse signal generation unit 220 becomes active H based on a prestored decode value as a functional unit that generates the video sample pulses SH1, SH3, and SH4. Decoders 542-SH1, 542-SH3, 542-SH4 for generating control pulses P542-SH1, P542-SH3, P542-SH4, and control pulses P544-SH1, which become active H based on the previously stored decode value, Decoders 544-SH1, 544-SH3, 544-SH4 (collectively referred to as decoders 544) for generating P544-SH3 and P544-SH4 (collectively referred to as control pulses P544).

  Further, the video sample pulse generation unit 500 is a functional unit that generates the video sample pulse SH2, and a decoder 542 that generates a control pulse P542-SH2 that becomes active H based on a previously stored decode value as the video sample pulse SH2. -Has SH2. The decoders 542-SH1, 542-SH2, 542-SH3, and 542-SH4 are collectively referred to as a decoder 542. The control pulses P542-SH1, P542-SH2, P542-SH3, and P542-SH4 are collectively referred to as a control pulse P542.

  Further, the video sample pulse generation unit 500 performs OR gates 546-SH1, 546-SH3, and 546-SH4 (collectively referred to as OR gates 546) that take the logical sum of the control pulses P542 and P544 output from the decoders 542 and 544. And D-type flip-flops 548-SH1, 548-SH3, 548- for synchronizing the OR outputs P546-SH1, -SH3, -SH4 (collectively referred to as OR outputs P546) of the OR gate 546 with the master clock CLK. SH4 (collectively referred to as D-type flip-flop 548).

  In the D-type flip-flop 548, the OR output P546- of the OR gate 546 is supplied to the D input terminal, and the master clock CLK generated by the PLL circuit 210 is supplied to the clock terminal CK.

  With such a configuration, the decoders 542 and 544 generate control pulses P542 and P544 that become active H with the decode value stored in advance with respect to the counter value of the HCK counter 436, and these decoders 542 and 544 generate the control pulses. In response to the control pulses P542 and P544, the active H video sample pulses SH1, SH3, and SH4 are generated by the D-type flip-flop 548 (except for -SH2). On the other hand, the decoder 542-SH2 always sets the active H fixed output for the video sample pulse SH2.

  Here, using the drive signal generation unit 200 shown in FIG. 9, based on the video signal of 3: 4, a video display device having a wider angle of view than the video signal (in this example, the liquid crystal display device 1). When an image is to be displayed on the display panel unit 100), the displayed image becomes a horizontally extended image as shown in FIG. In order to avoid this problem, the 3: 4 video signal is displayed at a predetermined position (typically in the center) of the video display device without losing the roundness, and more preferably, the remaining invalidity at that time It is preferable to prevent the viewer from feeling uncomfortable by displaying a certain signal level in the video area (left and right areas in the previous example).

  As a technique for this, when displaying an image based on a video signal of 3: 4, as in the mechanism described in Japanese Patent Laid-Open No. 2003-1557058, the frequency division number of the PLL is changed. By reducing the frequency of the master clock CLK, the angle of view of the original source (3: 4 in this example) can be displayed on a video display device having a wider angle of view.

  However, in this method, if the frequency division number of the PLL is changed, the PLL is switched when switching the video signal of 3: 4 and the video signal of the normal angle of view wider than that while keeping the video display. There is a risk that the image will be distorted because the lock is released for a moment. In addition, since the frequency of the master clock CLK is reduced, a period for displaying a signal at a certain level in the left and right invalid video areas, a period that can be used for a control signal for a video display device, that is, a block outside the valid video area. The ranking period will be reduced.

  As another method, by having a plurality of PLL frequency dividing counters or the like, it is possible to have a PLL circuit substantially corresponding to the angle of view of the corresponding video signal, and the master clock CLK to be used is the angle of view of the video signal. A method to deal with by selecting according to is also conceivable. However, in this method, since the PLL frequency dividing counter has a plurality of PLL circuits such as a plurality of multi-bit counters, the circuit scale of the PLL circuit is increased.

  In order to solve such a problem, the horizontal scanning system pulse signal generation unit 220 of the drive signal generation unit 200 according to the present embodiment includes one signal generated by the PLL circuit 210 as described with reference to FIG. A component capable of selectively generating a pulse signal having a normal frequency for a wide image display operation and a pulse signal having a frequency lower than the normal frequency for a narrow image display operation within one horizontal scanning period based on a reference clock. Provided. Hereinafter, an example of the configuration will be specifically described with reference to FIG.

  As shown in FIG. 10, the horizontal scanning system pulse signal generation unit 220 of this embodiment adds a display aspect ratio switching control pulse P10 to the basic configuration shown in FIG. 9, and this display aspect ratio switching control pulse. With P10, in addition to a normal operation (wide image display operation) for displaying on a video display device with a wide angle of view based on a video signal with a wide angle of view, a special operation (displaying based on a video signal with a narrow angle of view) ( Narrow image display operation) is performed by switching without causing image disturbance.

  Specifically, the horizontal scanning system pulse signal generation unit 220 is generally independent of a wide image display operation (referencer-WD) and a narrow image display operation (referencer-NR). The horizontal drive system pulse generator 400 and the video sample pulse generator 500 shown in FIG. In addition, a video blanking pulse generation unit 600 that generates a video blanking pulse BLK used exclusively for the narrow image display operation is provided.

  The video blanking pulse generation unit 600 generates decoders 622 and 624 that generate control pulses blkj and blkk that become active H based on a previously stored decode value, and control pulses blkj and blkk output from the decoders 622 and 624. And a JK flip-flop 626 for generating a video blanking pulse BLK based on the above.

  The control pulse blkj output from the decoder 622 is supplied to the J input terminal of the JK flip-flop 626, and the control pulse blkk output from the decoder 624 is supplied to the K input terminal of the JK flip-flop 626. Note that the video blanking pulse BLK may be synchronized with the master clock CLK by supplying the master clock CLK generated by the PLL circuit 210 to the clock terminal of the JK flip-flop 626.

  Further, the display aspect ratio switching control pulse P10 is supplied to the clear (reset) terminal CLR of the JK flip-flop 626. When the H level is supplied to the clear terminal CLR, the JK flip-flop 626 sets the non-inverting output terminal Q to the L level.

  With such a configuration, the decoders 622 and 624 generate control pulses blkj and blkk that become active H with the decode value stored in advance with respect to the counter value of the H counter 412, and the decoders 622 and 624 generate these control pulses. A video blanking pulse BLK is generated by the JK flip-flop 428 by the control pulses blkj and blkk thus generated, and an active high video blanking pulse BLK is output from the non-inverting output terminal Q thereof.

  In the horizontal scanning system pulse signal generation unit 220 of this embodiment, the H counter 412, the decoder 432, the OR gate 434, the HCK counter 436, and the decoder 542 -SH 2 are used for a wide image display operation and a narrow image. It is configured to be shared for display operation. It goes without saying that the functional elements arranged at the subsequent stage of the switching unit 730 are also shared for the wide image display operation and the narrow image display operation.

  The horizontal scanning system pulse signal generation unit 220 is stored in advance as a switching control pulse generation unit 700 that generates a control pulse P11 for switching each pulse signal for wide image display operation and narrow image display operation. A decoder 724 that generates a control pulse P744 that becomes active H based on the decoded value, a JK flip-flop 726 that generates a control pulse P726 based on the control pulses P432 and P744 output from the decoders 432 and 724, and an OR gate 728 And have.

  The control pulse P432 output from the decoder 432 is supplied to the J input terminal of the JK flip-flop 726, and the control pulse P724 output from the decoder 724 is supplied to the K input terminal of the JK flip-flop 726. The OR gate 728 is supplied with a control pulse P726 output from the JK flip-flop 726 at one input terminal and supplied with a display aspect ratio switching control pulse P10 at the other input terminal.

  With such a configuration, when the display aspect ratio switching control pulse P10 is at the L level, the switching control pulse generation unit 700 does not change the frequency of the master clock CLK but interlocks with the horizontal scanning clock HCK of the video display device. The control pulses for various horizontal scanning systems such as the horizontal start pulse HST, the video sample pulses SH1 to SH4, and the video blanking pulse BLK to be switched are switched between the effective video area and the other invalid video areas. A control pulse (generally equal to the video blanking pulse BLK) can be obtained as the OR output of the OR gate 728.

  Further, the horizontal scanning system pulse signal generation unit 220 serves as the switching unit 730 for switching between the wide image display operation and the narrow image display operation, and the horizontal drive system pulse generation unit 400 uses the wide image display operation and the narrow image display operation. Selector pulses 732 and 733 for switching each control pulse hstj-WD, hstj-NR, hstk-WD, hstk-NR for display operation, and control pulses hckj-WD for wide image display operation and narrow image display operation , Hckj-NR, hckk-WD, and selectors 734 and 735 for switching between hckk-NR. The selection output of the selector 732 is supplied to the J input terminal of the JK flip-flop 428, and the selection output of the selector 733 is supplied to the K input terminal of the JK flip-flop 428. The selection output of the selector 734 is supplied to the J input terminal of the JK flip-flop 428, and the selection output of the selector 735 is supplied to the K input terminal of the JK flip-flop 428 and one input terminal of the OR gate 434.

  The horizontal scanning system pulse signal generation unit 220 similarly applies to each of the OR gates 546 for the wide image display operation and the narrow image display operation with respect to the video sample pulses SH1, SH3, and SH4. A selector 738 for switching between the logical sum outputs P546-WD and P546-NR of WD and -NR is provided. In the figure, only one of the video sample pulses SH1, SH3, and SH4 is shown, and actually, three similar circuit configurations are provided. The selection output of the selector 738 is supplied to the D input terminal of the D flip-flop 548.

  The selectors 732, 733, 734, 735, and 738 are commonly supplied with control pulse P728 output from the OR gate 728 at their control input terminals. In both cases, when the logic level is H (= 1), each control pulse input for the wide image display operation is selected and output. When the logic level is L (= 0), the narrow image display operation is performed. Select each control pulse input for output.

  With such a configuration, the frequency of various control pulses of the horizontal scanning system of the video display device can be switched between the effective video area and the other invalid video areas, without changing the frequency of the master clock CLK. That is, when the display aspect ratio switching control pulse P10 is at the H level, a wide image display operation is performed for displaying on the video display device with a wide angle of view based on the video signal with a wide angle of view. This is a narrow image display operation in which display is performed on a partial area (effective video area) of a corner video display device based on a video signal with a narrow field angle.

  In the narrow image display operation, the drive signal generation unit 200 of the present embodiment sets the frequency of the pulse signal for the invalid video region to be the same as that for the wide image display operation, but lowers the frequency of the pulse signal for the effective video region. It is characterized by a point.

  That is, when a narrow image display operation in which the display aspect ratio switching control pulse P10 is at L level, first, the frequency of the horizontal scanning clock HCK, video sample pulses SH1 to SH4 (except for SH2 in this embodiment), and the video blanking pulse BLK. Alternatively, a control pulse for switching the frequency describing the generation position of the horizontal start pulse HST between the effective video area and the other invalid video area is obtained as an OR output of the OR gate 728.

  Each selector 732 to 738 is controlled in selection operation based on the OR output of the OR gate 728. As a result, as shown in FIGS. 5 and 4, the horizontal start pulse HST, the horizontal scanning clock HCK, the video The decode values of all the pulse signals of the sample pulses SH1 to SH4 are changed in the valid video area and the other invalid video areas. Further, since the clear terminal CLR of the JK flip-flop 626 becomes L level, the active H video blanking pulse BLK is output from the non-inverting output terminal Q of the JK flip-flop 626.

Second Embodiment
11 and 12 are diagrams illustrating a second embodiment of the drive signal generation unit 200 that is a characteristic part of the liquid crystal display device 1 of the present embodiment. The second embodiment is characterized in that, in addition to the configuration of the first embodiment, a phase adjustment function of the horizontal start pulse HST, the horizontal scanning clock HCK, and the video sample pulse SH is provided.

  Here, FIG. 11 shows a horizontal drive system pulse generator 400 that generates horizontal drive system pulses with different frequencies for each region and a video sample pulse with different frequencies for each region, which is used in the drive signal generator 200 of the second embodiment. 2 is a block diagram (basic configuration diagram) for explaining basic elements of a video sample pulse generation unit 500 for generating the FIG. 12 is a block diagram (detailed configuration diagram) showing a detailed configuration example of the horizontal drive pulse generator 400, the video sample pulse generator 500, and the video blanking pulse generator 600 in the second embodiment.

  In the configuration shown in FIG. 11, a phase adjustment function for the horizontal start pulse HST, the horizontal scanning clock HCK, and the video sample pulses SH1 to SH4 is added to the principle circuit of the drive signal generation unit 200 shown in FIG. First, the horizontal display control pulse phase control pulse P12 is supplied to the H counter 412. The phase control of the horizontal display control pulse by the H counter 412 is performed by changing the output value when the H counter 412 is reset.

  Specifically, the horizontal display control pulse phase control pulse P12 is supplied to the H counter 412, the output value when the H counter 412 is reset is changed, and the reset value is changed, whereby the horizontal start pulse HST, Each pulse signal of the scanning clock HCK and the video sample pulses SH1 to SH4 can have an offset with respect to the internal horizontal synchronizing pulse inthd output from the PLL counter 218.

  Further, in order to add a single phase adjustment function for the video sample pulses SH1 to SH4, the SH pulse phase control pulse P14 is further supplied to the decoders 542 and 544, so that the phase of the video sample pulse SH that becomes active H is horizontal. The scanning clock HCK and the horizontal start pulse HST can be individually adjusted.

  The video sample pulse SH (except SH2 in this embodiment) is active every half clock of the horizontal scanning clock HCK, and further, one horizontal scanning clock HCK is equivalent to six master clocks CLK (6fH specification). Therefore, the active period of the video sample pulse SH can be adjusted by 6 positions by using the reverse phase of the master clock CLK. In other words, the phase of the video sample pulse SH can be adjusted in units of half clocks of the master clock CLK.

  In the present embodiment, since the video sample pulse SH2 is always set to the H level, such phase adjustment is actually meaningless, and the SH pulse phase control pulse P14 is set to each of the video sample pulses SH1, SH3, and SH4. May be supplied individually, and three SH pulse phase control pulses P14 may be prepared. Since the video sample pulses SH1 to SH4 are mutually related pulses, the phase of the video sample pulses SH1 to SH4 is actually adjusted in conjunction with one system of SH pulse phase control pulse P14. . In order to adjust 6 positions, the SH pulse phase control pulse P14 is controlled by 3 bits as indicated by “3” for P14 in the figure.

  Thereby, even when the video signal and the horizontal display control pulse (horizontal start pulse HST, horizontal scanning clock HCK, video sample pulse SH) have a time difference due to the respective delays inside and outside the video display device, fine adjustment is performed. Will be able to.

  When such a mechanism is added to the circuit configuration of the drive signal generation unit 200 of the first embodiment shown in FIG. 10, the configuration shown in FIG. 12 is obtained. As can be seen from the figure, the horizontal display control pulse phase control pulse P12 is supplied to the H counter 412, and the output value at the time of resetting the H counter 412 is changed, so that the horizontal start pulse HST can be obtained even during the narrow image display operation. Each pulse signal of the horizontal scanning clock HCK can be offset with respect to the internal horizontal synchronizing pulse inthd output from the PLL counter 218.

  Further, by supplying the SH pulse phase control pulse P14 also to the decoders 542-NR and 544-NR, the video sample pulse SH (except SH2 in the present embodiment) that becomes active H even during the narrow image display operation. The phase can be further individually adjusted with respect to the horizontal scanning clock HCK. If the phase adjustment amount is different between the wide image display operation and the narrow image display operation, two SH pulse phase control pulses P14 may be prepared.

  Here, for example, a video signal having an aspect ratio of 3: 4 such as NTSC (National Television System Committee) or PAL (Phase Alternation by Line) is displayed on a video display device having an angle of view of 9:16. As described above, since one horizontal scanning clock HCK = 8 CLK (8 fH specification) with respect to the master clock CLK, the video sample pulse SH can be adjusted by 8 positions under the above conditions.

  In order to adjust the video sample pulse SH by 8 positions during the narrow image display operation, the SH pulse phase control pulse P14 is controlled by 3 bits as indicated by “3” for P14 in the figure. .

  As a result, even during the narrow image display operation, the video signal and the horizontal display control pulse (horizontal start pulse HST, horizontal scanning clock HCK, video sample pulse SH) have a time difference due to the respective delays inside and outside the video display device. In this case, the position of the horizontal display control pulse can be finely adjusted.

<Third Embodiment>
FIG. 13 is a diagram illustrating a third embodiment of the drive signal generation unit 200 that is a characteristic part of the liquid crystal display device 1 of the present embodiment. The third embodiment is characterized in that in addition to the configuration of the second embodiment, a phase adjusting function of the video blanking pulse BLK is provided. Here, FIG. 13 is a block diagram (detailed configuration diagram) showing a detailed configuration example of the horizontal drive pulse generator 400, the video sample pulse generator 500, and the video blanking pulse generator 600 in the third embodiment. .

  In the configuration of the second embodiment, as described above, there is a time difference due to the delay between the video signal and the horizontal display system control pulse (horizontal start pulse HST, horizontal scanning clock HCK, video sample pulse SH) inside and outside the video display device. In such a case, the time difference can be adjusted by adjusting the output value when the H counter 412 is reset and the phase of the video sample pulse SH. However, if the phase is adjusted by adjusting the output value when the H counter 412 is reset, the active position of the video blanking pulse BLK also has an offset with respect to the internal horizontal synchronization pulse inthd output from the PLL counter 218. As a result, the video blanking pulse BLK position becomes inappropriate with respect to the invalid video region, and there is a possibility that an unsightly image is displayed and output near the boundary between the invalid video region and the invalid video region.

  Similarly, when the sampling phase of the video signal is changed by adjusting the video sample pulse SH based on the SH pulse phase control pulse P14, similarly to the narrow image on which the video blanking pulse BLK position is displayed. There is a possibility that an unpleasant image may be displayed and output near the boundary between the invalid video area and the invalid video area.

  In order to surely solve this problem, in the configuration of the third embodiment, by supplying the BLK active position control pulse P16 to the decoders 622 and 624, the video blanking pulse that becomes active H during the narrow image display operation. The phase of BLK, that is, the active period of video blanking pulse BLK can be finely adjusted. For example, when a narrow image is displayed at the center of the wide screen, the invalid video area can be on the left and right of the narrow image. Therefore, the signal blanking pulse BLK is set so that the signal display area at a certain level is symmetrical on the left and right. Adjust the active period individually.

<Details of horizontal drive shift register>
FIG. 14 is a diagram illustrating a configuration example of the horizontal driving unit 106 provided in the display panel unit 100. The transfer processing unit 160 shown here does not change the frequency of the master clock CLK but displays the frequency of the pulse signal of the horizontal scanning system when displaying a narrow image on the wide screen without breaking the roundness. This is a very effective configuration and shift operation in combination with a mechanism for switching between the video area and other invalid video areas (that is, within one horizontal scanning period).

  The shift operation of the horizontal transfer processing unit 161 of this example is characterized in that it can be performed independently for the effective video area and the invalid video area (particularly the portion after the end position of the effective video area). ing. Here, the outline of the shift operation in the case where the narrow image is displayed without breaking the roundness with the central portion in the wide screen as the effective video area will be described as follows.

  First, the active period of the horizontal start pulse HST is set before the position corresponding to the invalid video area before the effective video area. As a result, it is possible to display a signal at a certain level (for example, black level) also in the invalid video area before the start position of the effective video area.

  Also, for the invalid video area on the reverse side, that is, the invalid video area after the end position of the valid video area, when a certain level of signal is written to the invalid video area on the front side of the valid video area, it is simultaneously shifted from the reverse side. Perform the action. As a result, signal display at a certain level (for example, black level) can be simultaneously performed on both the invalid video area before the start position of the effective video area and after the end position.

  During the period of replacement with these constant level signals, video signal constant level replacement control is performed based on the video blanking pulse BLK generated by the video blanking pulse generator 600. Note that the video signal Vsig input to the display panel unit 100 is a 3: 4 narrow image (effective video) itself, and the 3: 4 narrow image has a signal level when the signal is replaced with a certain level. Not specifically prepared. For this reason, here, a blanking signal (black signal) generally provided between the scanning signals is used for a certain level after replacement. This will be specifically described below.

  Basically, the horizontal transfer processing unit 161 is configured as a single shift register group in which transfer switches and flip-flops having a pair of input terminals and output terminals are connected in multiple stages corresponding to the total number of columns of pixels. Has been. The horizontal start pulse HST supplied to the horizontal transfer processing unit 161 is a horizontal start pulse lHST (the leading “l” means left) by the left / right inversion control signal RGT (RiGhT) and the left / right inversion control signal xRGT having the opposite phase. ) Or a horizontal start pulse rHST (the leading “r” means right). Further, when the left / right inversion control signal RGT is active H, it means a normal transfer that is transferred from the left side to the right side in the horizontal direction, and the left / right inversion control signals RGT and xRGT are input to the transfer switch in the horizontal transfer processing unit 161. As a result, the transfer direction can be selected.

  That is, in FIG. 14A, first, the horizontal transfer processing unit 161 is configured to be able to reverse the transfer direction. Further, in the horizontal drive unit 106, in the vicinity of the horizontal transfer processing unit 161, the level shifter unit 107H for the horizontal start pulse HST includes the left invalid video region Invalid-left (level shifter unit 107H-left) and the right invalid video region. For Invalid-right (level shifter 107H-right). A horizontal start pulse lHST is output from the level shifter unit 107H-left and supplied to the input terminal 161Lin of the invalid video area Invalid-left of the horizontal transfer processing unit 161, while a horizontal start pulse rHST is output from the level shifter unit 107H-right. Then, it is supplied to the input terminal 161Rin of the invalid video area Invalid-right of the horizontal transfer processing unit 161.

  The level shifters 107H-left and -right are also used for an effective image area (Effective). Which is used for the effective image area depends on the transfer direction, and in the present embodiment, when the horizontal left side to the right side, specifically, the physical left of the display panel unit 100 is used as a reference. The level shifter 107H-left is used for the effective image area during the forward transfer from the left side to the right side, and the level shifter 107H-right is used for the effective image area during the reverse transfer to transfer from the right side to the left side in the horizontal direction. Used for. This control is performed based on the left / right inversion control signals RGT, xRGT. The position and size of the invalid video area can be arbitrarily set and changed based on the video blanking pulse BLK input from the video blanking pulse generation unit 600.

  In addition, the horizontal drive unit 106 includes a display control signal generation unit (GEN) 800 that generates a control pulse for displaying a narrow image without breaking the roundness with the central portion in the wide screen as an effective video area. ing. The display control signal generation unit 800 includes a display control signal generation unit 800-left for the invalid video area Invalid-left on the left side and a display control signal generation unit 800-right for the invalid video area Invalid-right on the left side. It has been. The display control signal generation unit 800-left is supplied with a left / right inversion control signal RGT, the display control signal generation unit 800-right is supplied with a left / right inversion control signal xRGT, and each display control signal generation unit 800-left, − A display area switching signal NRW corresponding to the display aspect ratio switching control pulse P10 is commonly supplied to right.

  The display control signal generation unit 800-left generates a control signal NRL (NaRrow Left) to be supplied to a transfer switch in the invalid video area Invalid-left on the left side of the effective video area and a control signal xNRL in the opposite phase. In addition, the display control signal generation unit 800-right generates a control signal NRR (NaRrow Right) to be supplied to a transfer switch in the invalid video area Invalid-right on the right side of the effective video area and a control signal xNRR having a phase opposite to that. Note that the right / left inversion control signals RGT and xRGT are supplied to the transfer switch of the effective video area.

  The display control signal generation unit 800 supplies a control signal for level shifting to the horizontal start pulse lHST and the horizontal start pulse rHST while simultaneously selecting the horizontal start pulse HST to the display control signal generation unit 800, for example, left-right inversion Each control signal NRL, xNRL, NRR, xNRR is generated by performing logical synthesis of the control signals RGT, xRGT and the display area switching signal NRW.

  Each control signal NRL, xNRL, NRR, xNRR is supplied to the transfer direction control input terminal of the transfer switch in each region. As described with reference to FIG. 2, the connection form itself of the transfer switch constituting the horizontal transfer processing unit 161 is basically the same as that of the conventional transfer circuit, and the horizontal start pulse HST is sequentially transferred to the subsequent stage. They are connected to perform a shifting operation.

  Each transfer switch has two transfer direction control input terminals to which complementary inputs are input. When an H level is input to the positive transfer direction control input terminal and an L level is input to the counter transfer direction control input terminal, the forward transfer is performed. When the L level is input to the positive transfer direction control input terminal and the H level is input to the reverse transfer direction control input terminal, the reverse transfer is performed.

  In this example, in addition to the transfer direction being controlled by the left / right inversion control signals RGT and xRGT, the position and size of the invalid video area are the video blanking pulses input from the video blanking pulse generator 600. It can be arbitrarily set and changed based on BLK. For this reason, although not shown, the control signal RGT (xRGT) is based on the video blanking pulse BLK in order to appropriately assign each transfer switch to the left invalid video area, the right invalid video area, and the valid video area. , NRL (xNRL), or NRR (xNRR) is provided with a selector switch for switching whether to supply to the transfer direction control input terminal of the transfer switch. This is different from the conventional transfer circuit in which a control signal RGT (xRGT) for instructing the transfer direction is commonly supplied to all transfer switches.

  On the other hand, for the video signal applied to the pixel P, a video signal for using a blanking signal (black signal) provided between the scanning signals as a signal at a certain level for displaying a black image or the like in the invalid video area. As the switching control unit 820, as shown in FIG. 14B, the blanking signal extraction unit 822, the video signal Vsig supplied from the video signal processing unit 300, and the blanking signal extracted by the blanking signal extraction unit 822 are used. Are switched based on the video blanking pulse BLK supplied from the video blanking pulse generation unit 600, and a video signal switching unit 824 for outputting to the video line 165 is provided.

  With such a configuration, the horizontal driving unit 106 has a circuit configuration in which the horizontal start pulse HST can be input from both sides of the horizontal transfer processing unit 161. As a result, in the invalid video area on both sides, the horizontal start pulse HST can be used as a write start pulse for the invalid video area and transfer in opposite directions is possible, and the blanking signal (black signal) is sequentially sampled on the left and right simultaneously. Can continue. Effective video area transfer starts by selecting one of the last-stage shift pulses of the invalid video area as a write start pulse for the valid video area, and thereafter the same as the transfer process in the invalid video area. Transfer processing is performed. That is, the horizontal start pulse HST is continuously transferred from one of the invalid video areas to the effective video area for each stage, and the pixel is sequentially pointed. For the other invalid video area, the transfer of the horizontal start pulse HST is stopped when the valid video area is reached. Here, the frequency of the horizontal scanning clock HCK is lowered during the transfer of the effective video area.

  As described above, in this example, each transfer switch constituting the horizontal transfer processing unit 161 is assigned to each area, and the control signal RGT (xRGT) instructing the transfer direction is not commonly supplied to all transfer switches. Based on the control signal RGT (xRGT) and the display area switching signal NRW, the display control signal generation unit 800 controls the control signals NRL, xNRL, By generating NRR and xNRR, the transfer direction of each transfer switch in each area is controlled.

  By newly introducing the display control signal generation unit 800, the subordinate connection mode of each transfer switch of the horizontal transfer processing unit 161 can be made the same as the conventional one, that is, the existing transfer circuit can be completely diverted. In addition, by introducing a new method of controlling the transfer direction for each region, it is possible to switch between wide display and narrow display while using a wide panel without providing a switch element or a connection gate element in the middle of the transfer stage. The transfer direction can be switched.

  By adopting such a mechanism for the horizontal driving unit 106, a part of the function of a video signal processing circuit such as an external DSP can be substantially incorporated into the display panel unit 100, and the DSP chip size can be reduced. The substrate 102 and the liquid crystal display device 1 itself can also be reduced in size.

  For example, when displaying based on a video signal of 3: 4 on a 9:16 wide panel, a signal of a certain level is added to the left and right of the video signal of 3: 4 by video signal processing, and the signal is converted to 3: 4. It is not necessary to take a method of squeezing the size and displaying on the wide panel, and the video signal processing circuit for performing these processes can be deleted. Also, since the sampling frequency is temporarily reduced in the effective video area by the proportion of the effective video, there is no need to squeeze the 3: 4 video signal to the NTSC standard, and the external video processing circuit such as a DSP is simplified and small-scaled. Can be

  In addition, the cell configuration and layout of the horizontal drive circuit that requires high-frequency drive are exactly the same, and when displaying on the wide panel based on the narrow video signal, the invalid video area is changed to the effective video area. The horizontal start pulse HST is continuously transferred for each stage over the stage to perform pixel dot sequential addressing, and a shift pulse delay or rounding occurs at the boundary between the invalid video area and the valid video area for black display or the like. There is no. This means that a constant slew rate can always be ensured in the horizontal drive circuit, and it can sufficiently cope with an increase in driving frequency. In addition, since the shift pulse for the invalid video area can be used as the horizontal start pulse HST for the valid video area, there is no possibility that the waveform will collapse.

  In addition, since the horizontal start pulse HST is continuously transferred from the invalid video area to the valid video area for each stage to perform pixel dot sequential addressing, when displaying on the wide panel based on the narrow video signal, The size and position of the invalid video area can be arbitrarily changed.

  As a result, problems that may occur when the mechanism described in JP-A-7-298171 is employed can be solved. For example, Japanese Patent Application Laid-Open No. 7-298171 proposes a mechanism that enables switching between wide display and normal display using a horizontal address circuit (equivalent to the horizontal transfer processing unit 161) using a single shift register. This mechanism is provided with a wide input switch element for injecting a horizontal start pulse HST at the input terminal of the flip-flop located at the top stage at the time of wide display, and at the same time at the input terminal of the flip-flop located at a specific intermediate stage at the time of normal display. This is dealt with by providing a normal input switch element for injecting a start pulse HST.

  However, when dealing with such a switch element, it is impossible to arbitrarily change the size of the invalid video area. In addition, since a switching element is provided in a part of a horizontal driving circuit that requires high frequency driving, a shift pulse delay or rounding occurs. In the mechanism described in Japanese Patent Laid-Open No. 7-298171, a method of introducing a dummy switch element for load adjustment in order to average the pulse delay and rounding is also proposed, but this is very difficult for high frequency driving. It is only a measure with no future potential.

  In Japanese Patent Laid-Open No. 7-298171, a connection gate element is interposed at the boundary between the invalid video area and the valid video area to enable the horizontal start pulse HST to be transferred at the wide display seam, while at the normal display horizontal seam. A mechanism has also been proposed in which the transfer of the horizontal start pulse HST is controlled in the forward direction or the reverse direction by interrupting the transfer of the start pulse HST, and bi-directional dot sequential addressing of pixels is performed. However, if a connection gate element is interposed in a part of a horizontal drive circuit that requires high-frequency driving, a pulse delay or rounding occurs as in the case where the switch element is provided in a part of the horizontal drive circuit.

  Further, in order to realize the mechanism described in JP-A-7-298171, it is necessary to route the horizontal start pulse HST to an intermediate stage. However, when wiring for high-frequency pulse signals is routed, there is an element that can be very strongly affected by wiring delay and capacitance, and the waveform can collapse and transfer cannot be started.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, there are various modified methods for the dot sequential driving method. As long as the video signal is written to the pixel P at each logic level of the horizontal scanning clock HCK, the mechanism described in the above embodiment is used. The same can be applied.

  In the above-described embodiment, an analog video signal is input, and this is sampled and applied to a liquid crystal display device equipped with an analog interface driving circuit that drives each pixel dot-sequentially. The above embodiment also applies to a liquid crystal display device equipped with a digital interface drive circuit that latches and converts this into an analog video signal, samples the analog video signal, and drives each pixel dot-sequentially. The mechanism described above can be similarly applied.

  Furthermore, in the above embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a pixel display element has been described as an example. However, the present invention is not limited to application to a liquid crystal display device, and is driven in a dot sequential manner. The mechanism described in the above embodiment can be similarly applied to all types of active matrix type displays.

It is a figure which shows the outline of the whole structure of one Embodiment of the liquid crystal display device to which one Embodiment of the drive device which concerns on this invention is applied. It is a figure which shows the structural example of the horizontal drive circuit of a dot sequential drive system. It is a block diagram which shows the whole outline | summary of a drive signal generation part. It is a figure which shows an example of the display mode at the time of displaying a narrow screen in a wide screen. It is an example of the timing chart of the pulse signal produced | generated in a drive signal production | generation part. FIG. 6 is a partial detail view of FIG. 5. It is an example of the timing chart of the conventional pulse signal. It is a block diagram which shows the whole video signal processing circuit outline. It is a basic composition figure explaining a 1st embodiment of a drive signal generating part. It is a detailed block diagram explaining 1st Embodiment of a drive signal production | generation part. It is a basic block diagram explaining 2nd Embodiment of a drive signal production | generation part. It is a detailed block diagram explaining 2nd Embodiment of a drive signal production | generation part. It is a detailed block diagram explaining 3rd Embodiment of a drive signal production | generation part. It is a figure which shows the structural example of the horizontal drive part provided in a panel part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 100 ... Display panel part, 102 ... Board | substrate, 103 ... Pixel array part, 105 ... Vertical drive part, 106 ... Horizontal drive part, 107 ... Level shifter part, 108 ... Terminal part, P ... Pixel 112 ... Scanning Lines 114, signal lines 161, horizontal transfer processing units 200, drive signal generation units 210, PLL circuits 212, voltage controlled oscillators 220, horizontal scanning system pulse signal generation units 230, vertical scanning system pulse signals generation , 300 ... Video signal processor, 400 ... Horizontal drive system pulse generator, 500 ... Video sample pulse generator, 600 ... Video blanking pulse generator, 700 ... Switch control pulse generator, 730 ... Switch unit, 800 ... Display control signal generation unit, 820 ... video signal switching control unit

Claims (11)

A plurality of display pixels arranged in a matrix so as to form a display screen having an aspect ratio of X: Y and the display pixels arranged in a line are turned on by sequentially shifting the write start pulse at each logic level of the scan clock. A method of driving a display panel having an addressing unit for sequentially addressing,
The frequency of the scanning clock for addressing the display pixels in the effective image area, which is the area of the aspect ratio X: Z (Z <Y) in the display screen having the aspect ratio X: Y, in a dot-sequential manner While maintaining the duty ratio of the scanning clock for addressing the display pixels in the invalid video area, which is an area excluding the effective video area in the display screen having the ratio X: Y, in a dot sequential manner, the frequency is lower than that frequency. A driving method characterized by setting. 2. The driving method according to claim 1, wherein the scanning clock for each of the effective video area and the invalid video area is acquired by dividing the output signal of a common oscillator with a different division ratio. . A plurality of display pixels arranged in a matrix so as to form a display screen having an aspect ratio of X: Y and the display pixels arranged in a line are turned on by sequentially shifting the write start pulse at each logic level of the scan clock. A drive device for driving a display panel having an address designating unit for sequentially addressing,
The frequency of the scanning clock for addressing the display pixels in the effective image area, which is the area of the aspect ratio X: Z (Z <Y) in the display screen having the aspect ratio X: Y, in a dot-sequential manner While maintaining the duty ratio of the scanning clock for addressing the display pixels in the invalid video area, which is an area excluding the effective video area in the display screen having the ratio X: Y, in a dot sequential manner, the frequency is lower than that frequency. A drive device comprising a scan clock generation unit for setting. An oscillator that generates a reference clock signal;
The scan clock generation unit acquires the scan clock for each of the effective video area and the invalid video area by dividing the clock signal output from the oscillator with a different division ratio. The drive device according to claim 3. The drive device according to claim 3, wherein the scan clock generation unit is configured to be able to finely adjust the generation timing of the scan clock. The driving apparatus according to claim 3, further comprising: a video switching control signal generating unit that generates a video switching control signal for outputting a video of a certain level in the invalid video area. The drive device according to claim 6, wherein the video switching control signal generation unit is configured to be able to change a position and a size of the invalid video area. A video sample signal generator for generating a sample signal for sampling a video signal representing the video having the aspect ratio X: Z;
The driving apparatus according to claim 3, wherein the video sample signal generation unit adjusts the generation timing of the sample signal in accordance with a change in the frequency of the scan clock by the scan clock generation unit. The driving apparatus according to claim 8, wherein the video sample signal generation unit is configured to be able to finely adjust the generation timing of the sample signal. Write start pulses supplied from a plurality of display pixels arranged in a matrix and a driving device so as to constitute a display screen having an aspect ratio X: Y are sequentially shifted at each logical level of a scanning clock supplied from the driving device. A display panel having an address designating unit for addressing the display pixels arranged in a line in a dot-sequential manner,
A video signal switching control unit that outputs a part of the video signal supplied from the driving device by replacing it with a signal of a certain level based on the video switching control signal supplied from the driving device. Display panel. The display pixels arranged in a line are dot-sequentially shifted by sequentially shifting a plurality of display pixels arranged in a matrix to form a display screen having an aspect ratio of X: Y and a write start pulse at each logic level of the scanning clock. A display panel having an address designating unit for addressing and a drive device for driving the display panel,
The driving device uses the scanning clock for addressing the display pixels in the effective video area which is the area of the aspect ratio X: Z (Z <Y) in the display screen of the aspect ratio X: Y in a dot-sequential manner. While maintaining the duty ratio of the scanning clock for addressing the display pixels in the invalid video area, which is an area excluding the effective video area in the display screen having the aspect ratio X: Y, in a dot-sequential manner, A display device comprising a scan clock generation unit that is set lower than the frequency.

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