JPH08304773A - Matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE: To prevent a liquid crystal from being deteriorated by an excessive DC-biasing of a liquid crystal panel by bringing an output from a row driving means and/or a column driving means into a high impedance state for a prescribed period at the time of starting a power source supply. CONSTITUTION: For a liquid crystal panel 1 aligning therein (n) lines of row electrodes 1a and (m) lines of column electrodes 1b in a grid shape and sealing liquid crystals between them for matrix displaying, a scanning driver (row driving means) 3 sequentially outputs shifted scanning signals to (n) lines of the row electrodes 1a, and a signal driver (column driving means) 4 outputs data signals (m) lines of the column electrodes 1b by means of the inputted display signals. Here, a display control circuit 5 controls a generation timing of scanning signals from the scanning driver 3 and data signals from the signal driver 4, and brings at least either of the outputs from the scanning driver 3 and the signal driver 4 to a high impedance state, for one field period at least at the time of starting a power source supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device which forms display pixels by liquid crystal and performs a matrix display.

[0002]

2. Description of the Related Art Conventionally, various types of matrix type liquid crystal display devices have been proposed as disclosed in Japanese Patent Laid-Open No. 5-119746. In this matrix type liquid crystal display device, a scanning signal and a data signal are respectively supplied to a liquid crystal panel in which n row electrodes and m row electrodes are arranged in a grid pattern to display an image.

Here, the scan signal and the data signal are created by a scan driver and a signal driver. The scan driver sequentially shifts and applies scan signals to n row electrodes to select a line, and the signal driver is
It inputs RGB signals and gives data signals to the liquid crystal panel. These scan driver and signal driver are controlled by the display control circuit.

That is, the display control circuit inputs the vertical synchronizing signal and the horizontal synchronizing signal, controls the generation timing of the scanning driver and the scanning signal and the data signal output from the signal driver, and makes the display screen of the liquid crystal panel predetermined. Rewrite with frequency.

[0005]

In the matrix type liquid crystal display device having such a structure, immediately after the power supply to the device is started, the scanning signal and the data applied from the scanning driver and the signal driver to the liquid crystal panel are displayed. The signal is in an indefinite state, and an excessive DC bias may be applied to the liquid crystal in such a state.

When such an excessive DC bias is applied to the liquid crystal, problems such as deterioration of the liquid crystal and shortening of the life occur. The present invention has been made in view of the above problems,
The purpose is to prevent the application of such a DC bias.

[0007]

In order to achieve the above object, in the invention described in claim 1, n row electrodes (1a) and m column electrodes (1b) are arranged in a grid pattern. And a liquid crystal panel (1) in which liquid crystal is enclosed between them for matrix display, and row driving means (3) for sequentially shifting and outputting scanning signals to the n row electrode (1a).
According to the input display signal, the m column electrodes (1
A column driving means (4) for outputting a data signal to b) and a vertical synchronizing signal and a horizontal synchronizing signal are input, and the scanning signal and the column driving means (4) from the row driving means (3) are input according to these synchronizing signals. In a matrix type liquid crystal display device including display control means (circuit A in 5) for controlling the generation timing of the data signal from the row driving means (3) and the row driving means (3) at the start of power supply. It is characterized in that it is provided with an initial control means (circuits A, 40, 41 in 5) for bringing at least one output of the column drive means (4) into a high impedance state.

According to a second aspect of the present invention, in the first aspect of the invention, the initial control means sets the high impedance state only during a field period synchronized with a vertical synchronizing signal (circuit A in 5). Is characterized by. According to a third aspect of the present invention, in the first aspect of the invention, the initial control means is configured to operate 1
It is characterized in that it has a timer circuit (40) which is in the high impedance state for a timer time corresponding to a period longer than a field.

According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, at least one of the row driving means (3) and the column driving means (4) is
Output means (4a) for switching the output to the liquid crystal panel between the output permitting state and the high impedance state.
˜4 m), and the initial control means (circuits A, 40, 41 in 5) has the output means (4 a-4 m).
Is placed in a high impedance state.

According to the invention described in claim 5, the n-row electrode (1a) and the m-row column electrode (1b) are arranged in a grid pattern, and liquid crystal is enclosed between them to perform a matrix display. The liquid crystal panel (1) and the n row electrodes (1
row driving means (3) for sequentially shifting and outputting the scanning signal to a), and column driving means (4) for outputting a data signal to the column electrodes (1b) of m rows according to the input display signal,
A display control means (in 5) for inputting a vertical synchronizing signal and a horizontal synchronizing signal and controlling the generation timing of the scanning signal from the row driving means (3) and the data signal from the column driving means (4) according to these synchronizing signals. In a matrix type liquid crystal display device including the circuit A), a power supply detection means (30, 31) for detecting the start of power supply, and the power supply detection means (30, 31) for detecting the start of power supply. After that, the initial control means (32 to 3) for prohibiting the DC bias application between the row electrode (1a) and the column electrode (1b) of the liquid crystal panel (1) for at least one field period.
It is characterized by having 6).

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0012]

According to the invention described in claims 1 to 4, at the start of power supply, the output of at least one of the row driving means and the column driving means is set to a high impedance state for at least one field period. . Therefore, during that period, since the voltage is not applied to the liquid crystal panel, it is possible to prevent an excessive DC bias from being applied to the liquid crystal panel at the start of the voltage supply, and it is possible to solve the problem such as deterioration of the liquid crystal. it can.

In particular, as in the second aspect of the present invention, since the control is performed in the high impedance state only during the period of the field synchronized with the vertical synchronizing signal, the high impedance state is changed to the normal display operation. Since the switching timing of can be synchronized with the vertical synchronization signal, the display can be rewritten from the beginning of the display screen, and the display can be displayed without any discomfort.

Further, according to the invention described in claim 5, when the power supply is started, the DC bias application prohibited state is initially set between the row electrodes and the column electrodes of the liquid crystal panel for at least one field period. Therefore, similarly to the above, it is possible to prevent deterioration of the liquid crystal due to an excessive DC bias at the start of voltage supply.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing an embodiment of the present invention. In FIG. 1, a liquid crystal panel 1 has n rows of row electrodes 1a and m rows of column electrodes 1b arranged in a grid pattern, and liquid crystal is sealed between them, so that n rows of row electrodes 1a are provided.
And a plurality of pixels are formed at the positions where the m column electrodes 1b intersect.

A video signal for displaying (TV, VTR, etc.) is input to the video circuit 2 as a composite signal, and the color signal (RGB signal) is input in the video circuit 2.
And a sync signal (vertical sync signal a, horizontal sync signal b). The scan driver 3 sequentially shifts and applies scan signals to the n-row row electrodes 1a formed on the liquid crystal panel 1,
Select a line. The signal driver 4 is a video circuit 2
The RGB signal is input, and the data signal is output to the m-row column electrodes 1b formed on the liquid crystal panel 1. Then, scanning signals are applied to the row electrodes 1a and the column electrodes 1b of the liquid crystal panel 1,
The data signals are respectively supplied to display images. As the scan driver 3 and the signal driver 4,
The same materials as those disclosed in JP-A-5-119746 can be used.

The display control circuit 5 inputs the vertical synchronizing signal a and the horizontal synchronizing signal b from the video circuit 2 and controls the generation timing of the scanning signal and the data signal output from the scanning driver 3 and the signal driver 4, The display screen of the liquid crystal panel 1 is rewritten at a predetermined frequency. A detailed configuration of the display control circuit 5 is shown in FIG.

A vertical synchronizing signal a and a horizontal synchronizing signal b are input to the display control circuit 5. The vertical synchronizing signal a is a signal for giving a display operation start timing of one field,
This identifies the first line. Horizontal sync signal b
Is a signal that gives the generation timing of the scanning signal. The waveforms of these signals a and b are shown in FIG. Vertical sync signal a
Is input to the first counter control circuit 22. The first counter control circuit 22 is composed of two flip-flops 22a and 22b, an OR circuit 22c, and an inverter 22d. 1 of sync signal b
The low-level reset signal k is output only for the clock. This low level reset signal k resets the V counter 25.

The V counter 25 outputs shift data c for the scanning driver 3 for determining the vertical display position. After the reset by the reset signal k, the V counter 25 performs the counting operation in synchronization with the rising of the vertical synchronizing signal a. , When the predetermined count value is reached, the shift data c is output. The timing of the reset signal k and the shift data c is shown in FIG. The period from the reset of the V counter 25 to the output of the shift data c corresponds to the vertical blanking period.

The horizontal synchronizing signal b is supplied to the inverter 27.
And output the output signal d for the scan driver 3. The scan driver 3 creates a scan signal for each scan line according to the shift data c and the output signal d. Further, the horizontal synchronization signal b is input to the second counter control circuit 23. This second counter control circuit 23
Has the same configuration as the first counter control circuit 22,
After the horizontal synchronizing signal b falls, the clock signal f is synchronized with the rising edge of the clock signal f from the oscillation circuit 21.
The low level reset signal 1 is output only for one clock. This reset signal 1 resets the H counter 26.

The H counter 26 outputs the shift data e for the signal driver 4 which determines the horizontal display position. After the reset by the reset signal l, the H counter 26 counts the clock signal f and reaches a predetermined count value. At the same time, the shift data e is output. The timing of the reset signal 1 and the shift data e is shown in FIG. The period from the fall of the horizontal synchronizing signal b to the output of the shift data e corresponds to the horizontal blanking period.

The signal driver 4 creates and outputs a data signal corresponding to the RGB signal by the shift data e and the clock signal f. Further, a signal obtained by inverting the horizontal synchronizing signal b and the shift data e by the inverter 28 is R
It is input to the S flip-flop 29. The flip-flop 29 is set by the fall of the horizontal synchronizing signal b and reset by the signal obtained by inverting the shift data e by the inverter 28. When the flip-flop 29 is in the set state, that is, when the high level signal is output, the signal driver 4 allows the output of the data signal.

That is, as shown in FIG. 4, the signal driver 4 has switch elements 4a to 4m for controlling the output of the data signals X ₁ ... X _m , and the flip-flop 29.
Is set to output a high level, the output of the data signals X ₁ ... X _m to the m column electrodes 1b of the liquid crystal panel 1 is permitted via the switch elements 4a to 4m. Further, while the low level signal is supplied to the switch elements 4a to 4m, the switch elements 4a to 4m are in a high impedance state (switch open state), and no voltage is applied to the liquid crystal panel 1. By controlling the output of the data signals X ₁ ... X _m in this manner, it is possible to reduce power consumption.

The above-mentioned configuration (circuit A in FIG. 2) is the same as the conventional one. With such a configuration, since the data of the H counter 25 and the V counter 26 is indefinite at the start of power supply, unnecessary shift data is output until the data is initialized, that is, reset. there is a possibility. Also, the scan driver 3 and the signal driver 4
In the above, a shift register and the like are provided for outputting a scanning signal and a data signal, and the output is unstable until the data is updated after the start of power supply. At the start of such power supply, the voltage applied to the liquid crystal panel 1 is unstable, and an excessive DC bias may be applied to the liquid crystal to deteriorate the liquid crystal.

Therefore, in the present embodiment, in order to eliminate such a problem, the circuit B in FIG. 2 is added, and a direct current is applied to the liquid crystal panel 1 until the data applied to the liquid crystal panel 1 reaches a desired state. No bias is applied. The circuit B will be described below. In this circuit B, a CR circuit (power supply voltage detection circuit) 30 composed of a resistor and a capacitor detects rising of the power supply voltage V _DD to the liquid crystal display device according to the present embodiment. That is, the output voltage i from the CR circuit 30 rises as the power supply voltage V _DD rises, the waveform is shaped by the buffer 31, and the signal j shown in FIG. 3 is output. The output signal j is inverted by the inverter 32 and input to the third counter control circuit 34. Further, the vertical synchronizing signal a is inverted by the inverter 33 and input to the third counter control circuit 34.

The third counter control circuit 34 has the same structure as the first and second counter control circuits 22 and 23, and is synchronized with the fall of the vertical synchronizing signal a after the rise of the output signal j. Then, the signal n that is at the low level for one cycle of the vertical synchronizing signal a is output. Flip flop 3
5 is reset when the output signal j is low level, and the output h is low level. After that, at the rising edge of the signal n from the third counter control circuit 34, its output h becomes high level.

Here, while the output h of the flip-flop 35 is at a low level, the output g of the AND circuit 36
Is at the low level, the switch element 4 of FIG.
a to 4 m are in a high impedance state, and no voltage is applied to the liquid crystal panel 1 during that period. The period in which the output h of the flip-flop 35 is at a low level corresponds to one cycle of the vertical synchronizing signal a, that is, one field, after the supply of the power supply voltage V _DD is started. Therefore, no matter what the data in the H counter 25, the V counter 26, and the data in the scan driver 3 and the signal driver 4 are after the power supply is started,
In the first one-field period, no voltage is applied to the liquid crystal panel 1, so that it is possible to prevent the application of a DC bias to the liquid crystal panel 1 and prevent its deterioration.

From the next field, since the output h of the flip-flop 35 is at high level, it is possible to display an image with regular data.
Therefore, by switching to the high impedance state only during the field period synchronized with the vertical synchronization signal a, the switching timing from the high impedance state to the normal display operation can be synchronized with the vertical synchronization signal, and thus the first display screen The display can be rewritten from the display, and the display can be performed without a feeling of strangeness.

In the above embodiment, the data signal side is set to the high impedance state. However, the scanning signal side may be set to the high impedance state with the same configuration, or both of them may be set to the high impedance state. May be. In addition, as described above, one or both of the outputs to the liquid crystal panel 1 is not limited to the high impedance state, and the point is that the DC bias is not applied to the liquid crystal panel 1 at the start of the power supply voltage supply. As another means for prohibiting the application of such a DC bias, for example, the both-end voltage applied to the liquid crystal panel 1 may be set to an equal potential such as 0V.

Further, the period for prohibiting the application of such a DC bias is not limited to one field as in the above embodiment, but may be a period for a plurality of fields. further,
Although the high impedance state is shown by synchronizing with the vertical synchronizing signal a after the power supply is started, the high impedance state is maintained by the timer circuit for a period of at least one field without using such synchronization. The state may be controlled to prohibit the application of the DC bias to the liquid crystal panel 1.

An embodiment in which such a timer circuit is provided in the signal driver 4 will be described below. FIG. 5 shows a partial configuration of the signal driver 4. Reference numeral 40 denotes the above-mentioned timer circuit, which is an integrating circuit 40a and a CMOS comparator circuit 40.
b, a D flip-flop 40c,
The output is input to the AND circuit 41. In this embodiment, the output m of the flip-flop 29 shown in FIG. 3 is directly input to the AND circuit 41 of the signal driver 4.

In the above structure, when the supply of the power supply voltage V _DD is started, the timer circuit 40 starts operating and the voltage integrated by the integrating circuit 40a is compared with the reference voltage by the comparator circuit 40b. The output of the comparator circuit 40b is at a low level until a certain time has elapsed, and the D flip-flop 40c inputs the low level signal to the RB terminal and outputs the low level signal. Therefore, AND
The output of the circuit 41 becomes low level, and the switch element 4a
No voltage is applied to the liquid crystal panel 1 because ˜4 m is in a high impedance state.

After a certain time has passed, the comparator circuit 40b
When the output of D becomes high, the D flip-flop 40
The clock c inputs the output m of the flip-flop 29 of FIG. 2 and sets its output to the high level. Therefore, after that, the output m of the flip-flop 29 is directly applied to the switch elements 4a to 4m, and normal liquid crystal display is performed.

FIG. 6 is a partial block diagram of the signal driver 4 in which the timer circuit 40 of FIG. 5 is replaced with a timer circuit 50. The general counter circuit 50c increases the degree of freedom in setting the time in which the switch elements 4a to 4m are in the high impedance state, and the capacitor of the integrating circuit 50a can be downsized, so that the chip size can be reduced. Figure 7
6 shows a time chart of the circuit of FIG.

The timer circuit may be provided on the scan driver 3 side, or may be provided on both the scan driver 3 and the signal driver 4.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of a matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a detailed configuration of a display control circuit in FIG.

FIG. 3 is a timing chart showing signal waveforms of respective parts in FIG.

FIG. 4 is a partial configuration diagram showing a partial configuration of a signal driver.

FIG. 5 is a partial configuration diagram of a signal driver showing another embodiment of the present invention.

6 is a partial configuration diagram of a signal driver 4 in which the timer circuit 40 of FIG. 5 is replaced with a timer circuit 50. FIG.

FIG. 7 is a timing chart showing signal waveforms of respective parts in FIG.

[Explanation of symbols]

1 ... Liquid crystal panel, 1a ... Row electrodes, 1b ... Column electrodes, 2 ... Video circuit, 3 ... Scan driver, 4 ... Signal driver, 40
... Timer circuit, 5 ... Display control circuit.

Claims (5)

[Claims] 1. A liquid crystal panel in which n row electrodes and m column electrodes are arranged in a grid pattern and liquid crystal is enclosed between them to perform a matrix display, and a scanning signal is applied to the n row electrodes. A row driving means for sequentially shifting and applying, a column driving means for applying a data signal to the column electrodes of m rows by an input display signal, and a vertical synchronizing signal and a horizontal synchronizing signal are input, and according to these synchronizing signals, In a matrix type liquid crystal display device comprising a display control means for controlling the generation timing of a scanning signal from the row driving means and a data signal from the column driving means, at the start of power supply, at least one field period,
A matrix type liquid crystal display device comprising an initial control means for setting an output of at least one of the row drive means and the column drive means to a high impedance state. 2. The matrix type liquid crystal display device according to claim 1, wherein the initial control means sets the high impedance state only during a field period synchronized with a vertical synchronization signal. 3. The matrix according to claim 1, wherein the initial control means has a timer circuit that is in the high impedance state for a timer time corresponding to a period of one field or more after power supply is started. Type liquid crystal display device. 4. At least one of the row driving means and the column driving means has an output means for switching an output to the liquid crystal panel between an output permitting state and a high impedance state. 4. The matrix type liquid crystal display device according to claim 1, wherein the initial control means sets the output means in a high impedance state. 5. A liquid crystal panel in which n row electrodes and m row electrodes are arranged in a grid pattern and liquid crystal is enclosed between them to perform a matrix display, and a scanning signal is applied to the n row electrodes. A row driving means for sequentially shifting and applying, a column driving means for applying a data signal to the column electrodes of m rows by an input display signal, and a vertical synchronizing signal and a horizontal synchronizing signal are input, and according to these synchronizing signals, In a matrix type liquid crystal display device having display control means for controlling the generation timing of the scanning signal from the row drive means and the data signal from the column drive means, a power supply detection means for detecting the start of power supply, After the start of power supply is detected by the power supply detection means, the DC bias application is prohibited between the row electrode and the column electrode of the liquid crystal panel for at least one field period. Matrix type liquid crystal display device characterized by comprising a period control means.