JP2001197331A - Synchronizing signal processing circuit and video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the disturbance of video on a screen by outputting a stable synchronizing signal even when the period of the inputted synchronizing signal is disturbed. SOLUTION: A synchronizing signal processing circuit 18 is provided with a circuit for detecting the edge of a horizontal synchronizing signal HSYNC to output a LOAD signal, a counter 24 for counting an asynchronous fixed clock signal CLK1 outputted by a fixed oscillator 19 to LOAD a counter value by a LOAD signal, flip-flops 26, 25 for respectively holding counter values showing the period of the last time and this time, a comparator 27 comparing the period of the last time with that of this time to output 'L' when the period does not fluctuates and to output 'H' when the period fluctuates, a flip-flop 28 for holding the comparison result, and a gate 29 for ORing the output of both of the parts 28 and 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal processing device, and more particularly to processing of a vertical synchronizing signal and a horizontal synchronizing signal of a video signal display device or the like.

[0002]

FIG. 8 shows a conventional video signal processing apparatus 100P.
FIG. In the figure, 1P is a vertical synchronization signal input terminal, and 2P is a horizontal synchronization signal input terminal. 3P is an R signal input terminal, 4P is a G signal input terminal, and 5P is a B signal input terminal. Also, 6P
Is a PLL circuit, 7P, 8P, 9P are A / D converters, 10P is a flip-flop, 11P is a shift register, and 12P is a video signal processing circuit. Further, 13P is a vertical synchronization signal output terminal, 14P is a horizontal synchronization signal output terminal, 15P is an R signal output terminal, 16P is a G signal output terminal, and 17P is a B signal output terminal.

Next, the operation of the conventional video processing signal device 100P will be described. The horizontal synchronization signal input from the horizontal synchronization signal input terminal 2P is input to the PLL circuit 6P,
The circuit 6P includes a clock signal CL synchronized with the horizontal synchronization signal.
Generate K. Also, the A / D converters 7P, 8P, 9P are:
R, G, B signal input terminals 3P, 4P, 5P
The input video signal is converted into an 8-bit digital signal based on the clock signal CLK input from the PLL circuit 6P and output to the video signal processing circuit 12P. Then, the video signal processing circuit 12P includes the PLL circuit 6
P, a horizontal synchronizing signal input from a vertical synchronizing signal input terminal 1P, an A / D converter 7
Gamma correction, contrast adjustment, and the like are performed based on R, G, and B 8-bit video signals input from P, 8P, and 9P.
Signal processing such as brightness adjustment and color tone adjustment is performed, and the processed video signals are output to R, G, and B output terminals 15P, 16P,
The signal is output to a video signal display device (not shown) from 17P.
The flip-flop 10P converts the vertical synchronization signal input from the vertical synchronization signal input terminal 1P into a PLL circuit 6P.
After latching in accordance with the clock signal CLK input from the controller, the signal is output from the vertical synchronization signal output terminal 13P to the video signal display device or the like. Also, the shift register 11P
The video signal processing circuit 12P multiplies and adds the horizontal synchronizing signal input from the LL circuit 6P to the clock signal CLK input from the PLL circuit 6P by a data delay generated for performing signal processing by multiplying and adding the data. After being delayed accordingly, the signal is output from the horizontal synchronization signal output terminal 14P to the video signal display device or the like.

[0004]

Since the conventional video signal processing apparatus is configured as shown in FIG. 8, when the period of the input synchronization signal is disturbed, that is, when the input signal is switched or when the cable is switched, Even if the sync signal is disturbed due to disconnection or insertion of a cable or a poor connection of a cable or a connector, the sync signal or the video signal after the video signal processing is output as it is to the video signal display device or the like. . Therefore, in the case of input switching or the like, the horizontal synchronizing signal and the vertical synchronizing signal are always discontinuous, so that the position of each data is shifted, which causes a problem that the video on the screen is disturbed. . In addition, since the video signal processing is usually performed with the vertical synchronization signal as a reference, in a state where the cycle of the vertical synchronization signal is disordered,
For example, when reading and writing gamma data, the data may be incorrect, and a state in which the image on the screen is disturbed and the screen does not return to a normal screen may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and outputs a stable synchronization signal to a video signal display device or the like even if the period of the input synchronization signal is disturbed. It is an object of the present invention to prevent image disturbance on a screen as much as possible.

[0006]

According to a first aspect of the present invention, there is provided a synchronization signal processing circuit which receives at least one of a vertical synchronization signal and a horizontal synchronization signal and inputs the at least one synchronization signal. Counting the period using a clock signal that is asynchronous with the at least one synchronous signal,
When detecting the fluctuation of the period of the at least one synchronization signal based on the counter value, a stable signal having no period fluctuation as a new at least one synchronization signal in place of the input at least one synchronization signal. Generation
It is characterized by outputting.

According to a second aspect of the present invention, there is provided a synchronous signal processing circuit according to the first aspect, wherein the at least one new synchronous signal is a synchronous signal having a fixed output level. It is characterized by being.

A synchronous signal processing circuit according to a third aspect of the present invention is the synchronous signal processing circuit according to the first aspect, wherein when the periodic variation of the at least one of the synchronous signals is detected, the at least one of the at least one synchronous signal is detected. A synchronizing signal having a cycle before the one of the synchronizing signals has a cycle variation is generated and output as the new at least one synchronizing signal.

A synchronous signal processing circuit according to a fourth aspect of the present invention is the synchronous signal processing circuit according to any one of the first to third aspects, wherein the period of the at least one synchronous signal is output from a fixed oscillator. Counting using the clock signal.

A video signal processing apparatus according to a fifth aspect of the present invention is a video signal processing apparatus for processing a video signal using a vertical synchronizing signal and a horizontal synchronizing signal. It is characterized by comprising the synchronous signal processing circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of the synchronization signal processing circuit according to the present embodiment is that a clock signal that is asynchronous with an input synchronization signal (a vertical synchronization signal or a horizontal synchronization signal, or both synchronization signals) is used. Generated by an internal fixed oscillator, the cycle of the input synchronization signal is counted using this clock signal, and based on the counter value, the presence or absence of the occurrence of the period variation of the input synchronization signal is detected, and the occurrence of the period variation is detected. Sometimes, instead of the input synchronizing signal, a stable signal having no cycle fluctuation is generated and output as a new synchronizing signal based on the clock signal and the counter value. As a materialization of the elements among these characteristic points or the elements, a method of generating a signal fixed at a predetermined level (“H” level or “L” level) as the new synchronization signal, or a periodic variation occurs. A method of generating a signal having the same period as the stable period of the previous input synchronization signal and having the same pulse width as the input synchronization signal as the new synchronization signal based on the clock signal and the counter value is considered. Can be The former corresponds to the first embodiment described later, and the latter corresponds to the second embodiment.

The first and second embodiments will be specifically described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a video signal processing apparatus 100 according to the present embodiment. In the figure, 1 is a vertical synchronizing signal input terminal, and 2 is a horizontal synchronizing signal input terminal. Further, 3 is an R signal input terminal, 4 is a G signal input terminal, and 5 is a B signal input terminal. 6 is a PLL circuit, and 7, 8, and 9 are A / A
D converter 10, 10 is a flip-flop, 18 is a synchronization signal processing circuit, and 12 is a video signal processing circuit.
Further, 13 is a vertical synchronizing signal output terminal, 14 is a horizontal synchronizing signal output terminal, 15 is an R signal output terminal, 16 is a G signal output terminal, and 17 is a B signal output terminal. FIG. 1 shows a case where only the horizontal synchronization signal HSYNC is input to the synchronization signal processing circuit 18. FIG.
8 is different from the video signal processing device 100P of FIG. 8 in that a synchronization signal processing circuit 18 is newly provided in place of the shift register 11P.

Next, the operation of the video processing signal device 100 according to the present embodiment will be described. The horizontal synchronizing signal HSYNC input from the horizontal synchronizing signal input terminal 2 is input to the PLL circuit 6, and the circuit 6 generates a clock signal CLK1 synchronized with the horizontal synchronizing signal HSYNC. A / D
The converters 7, 8, and 9 convert the video signals input from the R, G, and B signal input terminals 3, 4, and 5 into 8-bit digital signals based on the clock signal CLK input from the PLL circuit 6. The signal is converted into a video signal processing circuit 1
Output to 2. Then, the video signal processing circuit 12
The horizontal synchronization signal HSYNC input from the L circuit 6 and the vertical synchronization signal VS input from the vertical synchronization signal input terminal 1
YNC, R input from A / D converters 7, 8, and 9,
Gamma correction by the G and B 8-bit video signals,
Signal processing such as contrast adjustment, brightness adjustment, and color tone adjustment is performed, and the processed video signals are output from R, G, and B output terminals 15, 16, and 17 to a video signal display device (not shown) or the like. The flip-flop 10 is connected to the vertical synchronization signal VSYNC input from the vertical synchronization signal input terminal 1.
Is latched in accordance with the clock signal CLK input from the PLL circuit 6, and then output from the vertical synchronization signal output terminal 13 to the video signal display device or the like. Further, the synchronization signal processing circuit 18 receives the horizontal synchronization signal HSYNC from the horizontal synchronization signal input terminal 2, performs the synchronization signal processing including the above-described elements or the like, and then converts the processed new horizontal synchronization signal HSYNC. The signal is output from the horizontal synchronization signal output terminal 14 to the video signal display device or the like. Hereinafter, the circuit configuration and operation of the synchronization signal processing circuit 18 which forms the core of the present embodiment will be described.

FIG. 2 is a block diagram showing a circuit configuration of the synchronization signal processing circuit 18 of FIG. As shown in FIG. 2, the synchronization signal processing circuit 18 detects the rising edge or falling edge of the input synchronization signal, that is, the horizontal synchronization signal HSYNC according to the polarity of the signal HSYNC (when the horizontal synchronization signal HSYNC has a positive polarity). Detects a rising edge, and detects a falling edge when the horizontal synchronization signal HSYNC has a negative polarity), and outputs an LOAD signal; and an input horizontal synchronization signal HSYNC.
Oscillator 19, which generates and outputs a fixed clock signal CLK1 whose frequency is fixed to a predetermined value and which is asynchronous with
And count the fixed clock signal CLK1 and LOA
LOAD the counter value at that time according to the input of D signal
Thus, a counter 24 for measuring the period of the input synchronization signal HSYNC is provided. Further, the synchronization signal processing circuit 18 converts the LOAD signal into the fixed clock signal CLK.
A flip-flop 22 for holding a counter value latch signal according to the timing of 1 and a flip-flop for holding the counter value latch signal as a RESET signal for resetting the counter value to 0 after the counter 24 loads the counter value. In response to the counter value latch signal output from the flip-flop 23 and the flip-flop 22, the counter values (the LOAD values output from the counter 24) indicating the previous cycle and the current cycle in response to the timing of the fixed clock signal CLK1, respectively, are second and second. Second and first flip-flops 26 and 25 which hold the data as one cycle data signal
And the second cycle data signal indicating the previous cycle and the first cycle data signal indicating the current cycle are compared, and if the difference is within ± 1 (the synchronization signal is input stably without fluctuation in the cycle) Normally, the counter value should be constant, but since the fixed clock signal CLK1 that is asynchronous with the horizontal synchronization signal HSYNC is used, a difference of ± 1 occurs as a result of the comparison.) Is a case where the synchronizing signal is not input stably in other cases (such as when switching the input signal or disconnecting / connecting the cable, etc.). Changes, the LOAD value of the counter 24 fluctuates), a comparator 27 that outputs a signal of “H” level,
A flip-flop 28 that holds the comparison result signal output from the comparator 27 in accordance with the timing of the fixed clock signal CLK1, and a logical sum (OR) of the output of the flip-flop 28 and the horizontal synchronization signal input from the horizontal synchronization signal input terminal 20 1) An OR gate 29 for performing processing and an output signal of the OR gate 29 are held as a new horizontal synchronizing signal HSYNC and sent to a horizontal synchronizing signal output terminal 32 (this terminal corresponds to the horizontal synchronizing signal output terminal 14 in FIG. 1). And an output flip-flop 31.

Next, the operation of the synchronous signal processing circuit 18 having the above configuration will be described. When the horizontal synchronizing signal HSYNC input to the horizontal synchronizing signal input terminal 20 is input to the edge detection circuit 21, the horizontal synchronizing signal HSYNC is output when the horizontal synchronizing signal HSYNC has a positive polarity.
In addition to detecting the rising edge of C or, in the case of negative polarity, the falling edge, one clock of the clock signal CLK1 according to the fixed clock signal (hereinafter simply referred to as clock signal) CLK1 input from the fixed oscillator 19 A pulse corresponding to the width is generated, and the pulse is output to the flip-flop 22 and the counter 24 as a LOAD signal of the counter 24. The flip-flop 22 latches the input LOAD signal at the timing of the clock signal CLK1 input from the fixed oscillator 19, and outputs each of the flip-flops 23, 25, and 26 as a counter value latch signal.
Output to The flip-flop 23 latches the input counter value latch signal at the timing of the clock signal CLK1 input from the fixed oscillator 19, and outputs the latched signal to the counter 24 as a RESET signal. The counter 24 counts the clock signal CLK1 input from the fixed oscillator 19, and
In response to the timing of the output LOAD signal, the counter value at that time is LOADed, and
The value is output to the first flip-flop 25. Further, the counter 24 outputs the RE input from the flip-flop 23.
The counter value is reset according to the timing of the SET signal. Further, the first flip-flop 25 inputs the LOAD value of the counter 24 and
Output latch signal and fixed oscillator 1
9, the LOAD value is latched in accordance with the timing of the clock signal CLK1 input from the second clock signal 9, and the LOAD value is used as a first periodic data signal (corresponding to a signal providing periodic data at the time of the current measurement). 27 to a first input terminal. Further, the second flip-flop 26 inputs the LOAD value latched by the first flip-flop 25, and outputs the counter value latch signal output from the flip-flop 22 and the fixed oscillator 19.
The first period data signal is latched in accordance with the timing of the clock signal CLK1 inputted from the input terminal, and the latched signal is compared with the second period data signal (from the LOAD value held in the first flip-flop 25 by the last measurement). (Corresponding to the time period data) at the second input terminal of the comparator 27. As a result, the comparator 27 compares the counter values given by the first and second period data signals input from the two flip-flops 25 and 26. If the difference between the two counter values is within ± 1, the “L” level is set. A comparison result signal is output; otherwise, an “H” level comparison result signal is output to flip-flop. As a result, the flip-flop 28 outputs the output signal of the comparator 27 to the clock signal C
The latch is performed in accordance with the timing of LK <b> 1, and the latched signal is output to the first input terminal of the OR gate 29.

On the other hand, the horizontal synchronizing signal HSYNC inputted from the horizontal synchronizing signal input terminal 20 is inputted to a second input terminal of the OR gate 29.

As a result, the OR gate 29 performs an OR operation on both outputs of the flip-flop 28 and the horizontal synchronizing signal input terminal 20, and outputs the output signal as a new horizontal synchronizing signal HSYNC from the horizontal synchronizing signal output terminal 14. Output. Therefore, when the period of the horizontal synchronization signal HSYNC does not change, the horizontal synchronization signal HSYNC input from the horizontal synchronization signal input terminal 2 is output from the horizontal synchronization signal output terminal 32, while the period change is detected by the comparator 27. In this case, the output of the OR gate 29 is
7 is determined by the “H” level signal output from the horizontal synchronizing signal output terminal 32. The signal whose level is always fixed to the “H” level is output. This state corresponds to a state in which the output of the horizontal synchronization signal HSYNC is substantially stopped when viewed from an external video signal display device or the like. As a result, the image on the screen becomes a stable image such as all black.

Here, from the viewpoint of making the description of the above operation easier to understand, the horizontal synchronizing signal HS of the negative polarity is used.
FIGS. 3 and 4 are timing charts showing the operation of each unit in the synchronization signal processing circuit 18 when the YNC is input to the synchronization signal processing circuit 18. Symbol BL1 in both FIGS.
Indicates the boundary line between FIGS.

Although the synchronization signal processing circuit 18 shown in FIG. 2 shows a case where the horizontal synchronization signal HSYNC is fixed at the "H" level when the period of the horizontal synchronization signal HSYNC fluctuates, the horizontal synchronization signal HSYNC is used. May be fixed to the “L” level. At this time, the comparator 2
When the comparison value is not within ± 1, a signal at the “L” level is output on the contrary, and an AND gate may be used instead of the OR gate 29 in FIG.

(Embodiment 2) In Embodiment 1 described above, when the input signal is switched, when the cable is connected or disconnected, or when the horizontal synchronizing signal is disturbed due to poor contact of the cable or the connector, etc. Although the case where a signal having a level fixed to a predetermined level is output as a substitute for the input horizontal synchronizing signal has been described, it is the same as the period before the periodic fluctuation of the horizontal synchronizing signal input to the synchronizing signal processing circuit occurs. A synchronization signal having a period, that is, a synchronization signal having a constant period, may be generated and output as a new horizontal synchronization signal. Hereinafter, this embodiment for stabilizing the horizontal synchronizing signal from such a viewpoint will be described with reference to FIG.
It will be described based on. The configuration of the video signal processing device is the same as that shown in FIG.

FIG. 5 is a block diagram showing a circuit configuration of the synchronization signal processing circuit 18 according to the present embodiment. The synchronous signal processing circuit 18 in the figure has a different circuit configuration from the synchronous signal processing circuit 18 shown in FIG. 2 in the following points, but the other circuit configurations are the same. Therefore, only a different circuit configuration will be described. That is, in FIG. 5, the first flip-flop 25 outputs the first cycle data signal giving the cycle obtained by the current measurement to the (first) comparator 27 and the second flip-flop 26, It also outputs to the three flip-flops 31. The third
The flip-flop 31 latches the first cycle data signal (current cycle data) input by the first flip-flop 25 or outputs the clock signal CLK1 according to the level of the enable signal output by the flip-flop 28.
The signal (the cycle before the cycle fluctuation occurs, that is, the previous cycle data) held at the timing preceding by one cycle time is continued to be held as it is. That is, when the comparison result of the comparator 27 is within ± 1, the enable signal is at “H” level (enable).
The third flip-flop 31 latches the input first cycle data signal and updates the held cycle data to the current cycle data. On the other hand, when the comparison result of the comparator 27 is not within ± 1, since the enable signal is at the “L” level (disabled), the third flip-flop 31 holds the previous cycle data as it is. The (second) counter 33 basically performs the same operation as the (first) counter 24 described above.
However, the RESET signal is supplied to a comparator 34 described later.
Is the output signal. Also, the (second) comparator 34
The output of the third flip-flop 31 and the LO of the counter 33
An output that gives an AD value is compared, and an "L" level signal is output when the counter values given by both input signals are the same, and an "H" level signal is output when both counter values are different. The synchronizing signal width creation circuit 35 includes a comparator 3
The pulse width of the pulse output from the horizontal synchronizing signal HSYN having no period disorder is inputted from the horizontal synchronizing signal input terminal 20.
C is a circuit that adjusts the width so as to be the same as that of C. The selector 36 adjusts the output signal of the synchronizing signal width generation circuit 35 input to the selector 36 according to the level of the output signal of the flip-flop 28. Horizontal sync signal input terminal 20
And selectively outputs the input horizontal synchronization signal HSYNC. That is, when the level of the output signal of the comparator 27 is “L” level (there is no periodical fluctuation), the selector 36 outputs the horizontal synchronization signal HSYNC input from the horizontal synchronization signal input terminal 20 from the horizontal synchronization signal output terminal 32 as it is. On the other hand, when the level of the output signal of the comparator 27 is at the “H” level (when periodic fluctuation is detected),
The synchronization signal output from the synchronization signal width generation circuit 35 is used as a new horizontal synchronization signal HSYNC as the horizontal synchronization signal output terminal 32.
Output more.

Next, the operation of the synchronous signal processing circuit 18 having the above configuration will be described. When the horizontal synchronization signal HSYNC input to the horizontal synchronization signal input terminal 20 is input to the edge detection circuit 21 and the selector 36, the edge detection circuit 21 outputs a rising edge when the horizontal synchronization signal HSYNC has a positive polarity, When HSYNC has a negative polarity, a falling edge is detected, a pulse having a width of one clock of the clock signal CLK1 input from the fixed oscillator 19 is generated, and the pulse is generated by the (first and second) counters 24 and 24. The LOAD signal is output to the flip-flop 22 and the counters 24 and 33 as the LOAD signal of 33. The flip-flop 22 latches the input LOAD signal at the timing of the clock signal CLK1, and outputs the latched signal to each of the flip-flops 23, 25, and 26 as a counter value latch signal. Flip-flop 23
Converts the input counter value latch signal into a clock signal C
Latched at the timing of LK1, and the latched signal is RE
It outputs to the counter 24 as a SET signal. Counter 2
4 counts the clock signal CLK 1, loads the counter value at that time in response to the input of the LOAD signal output from the edge detection circuit 21, and outputs the LOAD value to the first flip-flop 25. Also, the counter 24
The counter value is reset according to the timing of the RESET signal input from the flip-flop 23. The first flip-flop 25 receives the LOAD value of the counter 24, latches the LOAD value according to the timing of the counter value latch signal, which is an enable signal of the first flip-flop 25, and the clock signal CLK1, and outputs the latched value to the second flip-flop 25. The second and third flip-flops 26 and 31 and the comparator 27 are output. Further, the second flip-flop 26 is connected to the L latched by the first flip-flop 25.
The OAD value is input, and the LOA input according to the timing of the counter value latch signal functioning as the enable signal of the second flip-flop 26 and the clock signal CLK1.
The D value is latched and the value is output to the comparator 27. As a result, the comparator 27 compares the current and previous cycle data (counter values) input from the two flip-flops 25 and 26, respectively, and if the difference is within ± 1, outputs the "L" level comparison result signal. Otherwise, it outputs an "H" level comparison result signal to the flip-flop 28 and the selector 36. The flip-flop 28 latches the output signal of the comparator 27 according to the timing of the clock signal CLK1, and outputs the latched signal to the input terminal of the third flip-flop 31 as an enable signal. Third flip-flop 31
As described above, when the output signal of the flip-flop 28 is at the “L” level, the first cycle data signal output from the first flip-flop 25 is
1 while the output signal of the flip-flop 28 is at "H" level.
The previous cycle data already held is held as it is without latching the cycle data signal.

On the other hand, the counter 33 counts the clock signal CLK1 input from the fixed oscillator, and
LOAD the counter value at the timing of the OAD signal,
The LOAD value is output to the comparator 34. Therefore, the comparator 34 determines the counter value given by the output signal of the third flip-flop 31 and the LOAD of the counter 33.
When the two values are the same, an "L" level signal is output. When the values are different, an "H" level signal is output. Reset. The synchronization signal width creation circuit 35 receives the horizontal synchronization signal generated by the comparator 34, changes the signal to a signal having a constant synchronization signal width as described above, and outputs the signal to the selector 36. . The selector 36 is
When the output signal of the comparator 27 is at "L" level, the horizontal synchronizing signal HS input from the horizontal synchronizing signal input terminal 2
While outputting YNC as it is, when the output signal of the comparator 27 is at "H" level, the synchronizing signal width generation circuit 3
5 selects a horizontal synchronizing signal to be output, and uses the selected horizontal synchronizing signal as a new horizontal synchronizing signal HSYNC.
Output from 2.

Here, too, from the viewpoint of making the description of the above operation easier to understand, the horizontal synchronizing signal H of the negative polarity is used.
FIGS. 6 and 7 are timing charts showing the operation of each unit in the synchronization signal processing circuit 18 when SYNC is input to the horizontal synchronization signal input terminal 20 of the synchronization signal processing circuit 18 in FIG. In both FIGS. 6 and 7, the symbol BL2 is used in both FIGS.
Indicates the boundary line.

As described above, the synchronization signal processing circuit 18 shown in FIG.
Then, when the period of the input horizontal synchronization signal HSYNC is disturbed, a stable horizontal synchronization having a fixed period is obtained by using the previous measurement value, the current measurement value, and the clock signal CLK1 of the period of the input horizontal synchronization signal HSYNC. Since the signal is generated, the circuit 18 can always output a stable horizontal synchronization signal HSYNC.

(Modifications Common to First and Second Embodiments) (1) In the first and second embodiments, the horizontal synchronizing signal HSY is used for both.
The case where the above-described synchronization signal processing (elements to) is applied to the NC has been described. Instead of the horizontal synchronization signal HSYNC, the same synchronization signal processing (elements to) is applied to the vertical synchronization signal VSYNC. May be. In this case, a synchronous signal processing circuit having the same circuit configuration as the synchronous signal processing circuit 18 shown in FIG. 2 or 5 may be provided instead of the flip-flop 10P in FIG.

(2) Further, the above-described synchronization signal processing (elements) may be performed on each of the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. At this time, the horizontal and vertical synchronization signals HSYN are replaced with the flip-flop 10P and the shift register 11P of FIG.
A synchronizing signal processing circuit having a circuit configuration similar to that of the synchronizing signal processing circuit 18 shown in FIG. 2 or 5, which uses C and VSYNC as input synchronizing signals, may be provided.

[0029]

According to each of the first to fifth aspects of the present invention, even when the period of the input synchronization signal is disturbed, a stable synchronization signal can be output, thereby preventing the image on the screen from being disturbed. .

In particular, according to the invention according to claim 4, a stable clock signal can always be generated inside the synchronization signal processing circuit regardless of the disturbance of the input synchronization signal, and the periodic fluctuation of the input synchronization signal can be achieved. Can be reliably detected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a video signal processing device according to Embodiments 1 and 2 of the present invention.

FIG. 2 is a diagram showing a configuration of a horizontal synchronization signal processing circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a timing chart of the horizontal synchronization signal processing circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a timing chart of the horizontal synchronization signal processing circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a horizontal synchronization signal processing circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a timing chart of the horizontal synchronization signal processing circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a timing chart of the horizontal synchronization signal processing circuit according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional video signal processing device.

[Explanation of symbols]

1 vertical synchronization signal input terminal, 2 horizontal synchronization signal input terminal, 3 R signal input terminal, 4 G signal input terminal, 5 B
Signal input terminal, 6 PLL circuit, 7, 8, 9 A / D converter, 10 flip-flop, 12 video signal processing circuit, 13 vertical synchronization signal output terminal, 14 horizontal synchronization signal output terminal, 15 R signal output terminal, 16G Signal output terminal, 17 B signal output terminal, 18 synchronization signal processing circuit,
19 fixed oscillator, 20 horizontal synchronization signal input terminal, 21
Edge detection circuit, 22, 23, 25, 26, 28, 3
1 flip-flop, 24, 33 counter, 27,
34 comparator, 29 OR gate, 32 horizontal synchronizing signal output terminal, 35 SYNC width generating circuit, 36 selector, 100 video signal processing device.

Claims (5)

[Claims] 1. A synchronization signal of at least one of a vertical synchronization signal and a horizontal synchronization signal is input, and a cycle of the at least one synchronization signal is counted using a clock signal that is asynchronous with the at least one synchronization signal. When detecting the fluctuation of the period of the at least one synchronization signal based on the counter value, a stable signal having no period fluctuation is replaced with the new at least one synchronization signal in place of the input at least one synchronization signal. A synchronizing signal processing circuit that generates and outputs a signal. 2. The synchronization signal processing circuit according to claim 1, wherein the at least one new synchronization signal is a synchronization signal having a fixed output level. . 3. The synchronization signal processing circuit according to claim 1, wherein, when the periodic variation of the at least one synchronization signal is detected, a cycle before the periodic variation of the at least one synchronization signal occurs. And generating and outputting the new synchronizing signal as at least one of the new synchronizing signals. 4. The synchronization signal processing circuit according to claim 1, wherein the period of the at least one synchronization signal is counted using the clock signal output from a fixed oscillator. A synchronization signal processing circuit. 5. A video signal processing device for processing a video signal using a vertical synchronizing signal and a horizontal synchronizing signal, comprising the synchronizing signal processing circuit according to claim 1. , Video signal processing device.