JP2885794B2 - Speed modulation signal generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator for velocity modulation of a television receiver. 2. Description of the Related Art In recent years, digital signal processing of a video signal has been advanced, and velocity modulation has been performed on a CRT using a luminance signal in the digital signal processing. Hereinafter, an example of the above-described speed modulation circuit will be described with reference to the drawings. FIG. 3 is a block diagram showing a conventional speed modulation circuit of a digital television. In FIG. 3, 1 is a luminance signal processing circuit, 2 is a color difference signal processing circuit, 3 and 4 are D / A converters, 5 is an RGB matrix circuit, 6
8 is a delay line, 9 is a CRT drive circuit, 10 is a cathode ray tube, 11 is a phase correction circuit, 12 is a differentiation circuit, 13 is velocity modulation (hereinafter abbreviated as VM).
A VM drive circuit 14 is a VM coil. The operation of the circuit configured as described above will be described. First, the operation of the VM circuit will be described with reference to FIG. As shown in FIG. 4A, the luminance signal converted to analog by the DA converter 3 is adjusted in delay time by the phase correction circuit 11, differentiated by the differentiating circuit 12, and shown in FIG. 4B. Thus, the waveform has a time delayed by Td. This signal is applied to the VM drive circuit 13 to drive the VM coil 14. On the other hand, the luminance signal passes through the RGB matrix circuit 5 and is time-adjusted by the delay lines 6 to 8 by the time Td to be delayed by the VM circuit, as shown in FIG. 4C. On the screen, the VM drive circuit modulates the horizontal deflection current. As shown in FIG. 4d, at the point P, the deflection speed is partially increased, and the waveform of the waveform on the CRT screen is changed. The rise is steep, and at point Q, the deflection speed is partially reduced, and the fall of the waveform on the CRT screen is steep. As a result, the contour as shown in FIG. The obtained signal can be obtained. Problems to be Solved by the Invention However, in the above-described method, a signal delay occurs due to the VM circuit, particularly, the differentiating circuit 12 and the VM drive circuit 13, so that a signal to be subjected to the VM operation is generated. The delay is compensated for each other by using a delay line in the signal system as shown in FIGS. However, the provision of the delay line causes an increase in the number of large components, deterioration of the frequency characteristics of the signal, and the like, and has a problem in configuration and performance. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a speed modulation signal generation circuit with less deterioration in performance. Means for Solving the Problems In the present invention, a delay circuit that delays a first digital signal for a predetermined time, a first D / A converter that converts the first digital signal into an analog signal, A second D / A converter for converting an output signal of the delay circuit into an analog signal, wherein a second D / A conversion is performed by using an output of the first D / A converter as a speed modulation signal. The output of the device is used as a video signal. Function The present invention provides a delay circuit that delays a signal in a digital signal processing circuit, a signal corrected by the time delayed by a VM circuit for a luminance signal as a VM signal, and a D / A By converting the signal into an analog signal by a converter, a highly accurate signal can be obtained. Embodiment Hereinafter, a VM signal generation circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of a VM signal generation circuit according to one embodiment of the present invention. In FIG. 1, those denoted by the same reference numerals as those in FIG. 4 indicate the same functions. 1
Reference numerals 5 and 16 denote a luminance signal processing circuit 1 and a color difference signal processing circuit 2, respectively.
And a delay circuit 17 for converting the digital luminance signal into an analog signal. In FIG. 1, the signal of the luminance signal processing circuit 1 is
It is applied to a D / A converter 17 to obtain the signal of FIG. 2a.
This signal has a waveform delayed by time Td as shown in FIG. 2B by the phase correction circuit 11, the differentiation circuit 12, and the VM drive circuit 13. On the other hand, the luminance signal is
, And is displayed on the CRT 10 via the D / A converter 3 via the RGB matrix circuit 5 and the CRT drive circuit 9 with a waveform as shown in FIG. 2C. At this time, the phases of the luminance signal and the VM signal are
The match at P 'and Q' allows the VM to work effectively as shown in FIG. 2d. In FIG. 1, the delay circuit has a Td of about 70 nS to about 150 nS. Therefore, if the clock cycle used in the digital signal processing circuit is 70 nS, the delay circuit is equivalent to 1 to 2 clocks. As a result, it will be small. As described above, in the digital luminance signal processing circuit, the delay circuit is provided, a signal is provided in consideration of the delay time of the VM signal, and by using the VM D / A converter, any unstable delay line is generated in the signal system. Without providing this, a highly accurate VM signal generation circuit can be obtained. As described above, according to the present invention, by providing a digital delay circuit and a D / A converter for generating a VM signal, a highly accurate time-adjusted VM can be provided without deteriorating signal line performance. Signal can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a speed modulation signal generation circuit according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation thereof, and FIG. 3 is a conventional speed modulation signal generation circuit. FIG. 4 is an operation waveform diagram thereof. 1, a luminance signal processing circuit, 2, a color difference signal processing circuit,
4,17 …… D / A converter, 15,16 …… Delay circuit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hirohiko Sakashita               Matsushita, 1006 Kadoma, Kazuma, Osaka               Kiki Sangyo Co., Ltd. (72) Inventor Minami Yamaguchi               Matsushita, 1006 Kadoma, Kazuma, Osaka               Kiki Sangyo Co., Ltd.                (56) References JP-A-52-36919 (JP, A)                 JP-A-50-69917 (JP, A)

Claims (1)

(57) [Claims] A first delay circuit for delaying the digitized luminance signal for a predetermined time; a first D / A converter for converting the digitized luminance signal into an analog signal; and an output signal of the first delay circuit Second D / A to convert a signal to an analog signal
A converter, a speed modulation circuit for inputting an output signal of the first D / A converter, a second delay circuit for delaying the digitized color difference signal for a predetermined time, and a second delay circuit. A third D / A converter for converting an output into an analog signal, using outputs of the second and third D / A converters as a video signal, a processing time of the speed modulation circuit, 1, second
Wherein the delay times of the delay circuits are equal to each other.