GB2181912A

GB2181912A - A clamping circuit

Info

Publication number: GB2181912A
Application number: GB08611863A
Authority: GB
Inventors: John David Millward; Kevin David Brown
Original assignee: Rank Cintel Ltd
Current assignee: Rank Cintel Ltd
Priority date: 1985-10-21
Filing date: 1986-05-15
Publication date: 1987-04-29
Also published as: GB2181912B; GB8525861D0; GB8611863D0

Abstract

The clamping circuit clamps a threshold of an analog to digital converter to a signal level just below the black level of a television signal. During the blanking period, a negative-going peak is superimposed on the input signal to produce the waveform 76. Each time this crosses the 0000,0001 threshold of the ADC, the polarity of the output 77 of a comparator changes. The comparator compares the ADC output and a reference value. The input signal is biased according to the integral of the comparator output. When signal levels are stable, the comparator output is symmetrical, its integral is zero and no change occurs in the biassing. If signal levels drift, the negative going peak crosses the threshold for the second time relatively sooner or later. The comparator output becomes assymmetric and has a non-zero integral. Consequently, the biassing level changes to compensate for the drift. <IMAGE>

Description

SPECIFICATION A clamping circuit for an analogue to digital converter The present invention relates to analogue to digital conversion and to clamping signals, that is, ensuring that a particular part of a signal is held at a specified value.

The invention is applicable in a telecine projector, for example. A telecine projector is a device which converts images stored in the frames of movie film into television signals for display, recordal or transmission. The film images are projected onto an array of photoelectric sensors to generate an electrical signal which is subsequently processed to meet the requirements of a chosen television signal standard. It is desirable that at least some of the signal processing takes places digitally.

One function of the signal processing normally carried out in telecine equipment and television cameras, is known as gamma correction. Another is aperture correction.

Gamma correction is applied to the signal to compensate for the non-linearity of the light output with respect to signal input of cathode ray tubes (CRTs), which will eventually display the signal. The light output is normally related to the signal input magnitude by a power law, typically with an index of about 2.5. Compensation is provided in the telecine projector by processing the output of the sensor array, which is assumed to have a linear response, according to a power law with an index which is approximately the reciprocal of the CRT response index, so that the light output of the CRT becomes linearly related to the light input to the sensor array. The index is typically 0.4, but in some circumstances may be as low as 0.2.

If gamma and aperture correction are carried out by analogue circuits, subsequent processing being digital, analogue to digital conversion with 8-bit resolution is found to give satisfactory performance. 8-bit analogue to digital converters (ADCs) capable of operation at up to 50 MHz are commercially available. This frequency is adequately high.

If digital circuits are also to perform the gamma and aperture correction, 14-bit resolution is found to be necessary, with a sampling rate of at least 30 MHz. At the present time, a 14-bit ADC operable at this rate is not commercially available.

The problem can be overcome by using an ADC as shown in Figure 1. This type of ADC is known, and is called herein an "iterative ADC". The iterative ADC 10 receives an analogue input signal at 12. The analogue signal is converted by an 8-bit ADC 14 to provide an output which, after a delay provided by a delay circuit 16, forms one input to an adder circuit 18.

The output of the ADC 14 is also converted back to an analogue signal by a digital to analogue circuit (DAC) 20, and compared by a comparator 22 with the original input signal at 12, which has been delayed by a delay circuit 24. The-output from comparator 22 is a difference signal representing the difference between the actual input signal level at 12 and the level represented by the output of the ADC 14. This difference signal is amplified by a factor of 64 by an amplifier 25, and encoded by a further 8-bit ADC 26 to provide the second input to the adder 18. The amplification applied by the amplifier 25 gives the bits of this signal lower significance (by six binary positions) than the bits of the signal from the delay circuit 16.Thus, the adder 18 receives an 8-bit most significant byte from the delay circuit 16 and an 8-bit least significant byte from the ADC 26, the bytes overlapping by two binary places. These inputs are combined to form a 14-bit output at 28. The overlap in the bits of the bytes allows the least significant byte to take positive or negative values.

When an iterative ADC is used to provide analogue to digital conversion in a telecine projector, before gamma correction, a problem is found to arise. At and near the black level of a signal, the signal level (but not necessarily the voltage level) is zero and small, respectively, and the gradient of the gamma correction power law is extremely high. It is found that if a change in the most significant byte takes place in this region of high gradient, small discrepancies in the gain of the amplifier 25 produce visible and detrimental effects in the final image. The flaws arise because the amplifier 25 will never, in practice, be perfectly linear in its response or have precisely the required gain, so that a small change in the input signal about a threshold of the ADC 14 will not be accurately reflected in the output signal at 28.Discontinuities and discrepancies in the output 28 are amplified by the steep gamma correction characteristic, and hence cause the visible flaws.

It is an object of the present invention to reduce subjective degradation of the final image caused by operation of the iterative ADC.

The present invention provides a clamping circuit for an analogue to digital converter, comprising combining means for combining an input signal and a reference signal to provide an input for the converter, and a negative feedback circuit for biassing the input for the converter, the feedback circuit comprising a comparator for comparing the converter output and a digital reference value to provide'an output whose polarity depends on the result of the comparison, an integrator for integrating the comparator output, and means for biassing the input for the converter according to the level of the integrator output.

The clamping circuit according to the invention can be used in the iterative ADC to clamp the ADC providing the most significant byte (MSB) so that a change in the MSB takes place just below the black level of the input signal. This in turn ensures, as will be described below, that no change in the MSB will take place as signals move up and down the steepest portion of the gamma correction characteristic.

Clamping is applied to the MSB ADC (the ADC 14 of Figure 1) rather than to the output of the ADC 10 for the following reasons. The clamping circuit should have at least 14-bit resolution in order to locate the clamping level accurately, and so one possible arrangement would compare the output 28 with a reference signal and apply feedback to the input 12.

However, the overlap in significance of the bits of the inputs to the adder 18 would make this arrangement unstable. There may be more than one possible set of inputs which give a particular output, and an ADC clamped in this way would have a tendency to oscillate between these alternative solutions, thereby changing the value of the MSB.

Accordingly, it is necessary to use separate clamping circuits for the ADCs 14, 26. A sim ple feedback loop may be applied to ADC 26, whose output has 14-bit resolution, but the output of ADC 14 has 8-bit resolution, which is insufficient for simple feedback to provide sufficiently accurate clamping. A clamping circuit sccording to the invention can clamp the ADC 14 and perform as though it has 14-bit or greater resolution, as will be described below.

The present invention also provides a method of clamping the output of an analogue to digital converter in which a reference signal is combined with the input signal and negative feedback is applied from the converter output to bias the input signal, the output of the converter being compared with a digital reference value to generate a result signal whose polarity depends on the result of the comparison, the result signal being integrated to form an integral signal, and the biassing being set according to the value of the integral signal.

In a second aspect, the invention provides a signal processing circuit for analogue signals having periodic blanking periods during which the signal has a nominally constant voltage, wherein the circuit comprises an analogue to digital converter including clamping means operable to maintain a threshold of the converter at a voltage level relatively slightly displaced in one sense from the nominally constant voltage and to maintain the adjacent corresponding threshold of the converter to be relatively greatly displaced in the opposite sense from the nominally constant voltage, irrespective of the changes in the d.c. level of the signal.

The invention further provides, in its second aspect, a method of processing analogue signals having periodic blanking periods during which the signal has a nominally constant voltage, wherein the signals are converted by means of an analogue to digital converter, and the converter is clamped to maintain a threshold of the converter at a voltage level relatively slightly displaced in one sense from the nominally constant voltage and to maintain the adjacent corresponding threshold relatively greatly displaced in the opposite sense from the nominally constant voltage, irrespective of changes in the d.c. level of the signal.

Preferred features of the circuits and the methods according to the invention are recited in the subsidiary claims set out below and to which reference should now be made.

Embodiments of a clamping circuit according to the present invention, their operation and their application to an iterative ADC will now be described by way of example, and with reference to Figures 2 to 6 of the accompanying drawings in which: Figure 2 is a greatly simplified block diagram of a telecine system incorporating a clamping circuit according to the invention; Figures 3(a), 3(b), 3(c) show the transfer characteristics of the digital corrector and the CRT of Figure 2; Figures 4 & 5 show clamping circuits according to the invention, connected to the ADC 14 of Figure 1; Figure 6 shows the waveform of signals at various points in the circuits when the circuits have stabilised and the ouput is clamped to the desired level; and Figure 7 shows the waveforms at the same points after the input signal levels have drifted up.

Referring to Figure 2, a telecine projector 30 comprises a light source 32. This projects images stored on the film 34 onto a converter 36 which converts the incident light into an electric current. This conversion is substantially linear, and gives rise to an analogue signal which encodes the film images line by line, each line of data being separated by a period in which the signal is "blanked", and takes the value corresponding to a black image.

This value is known as the black level. Between the blanking periods, while the signal is carrying picture information, the signal is always displaced in the same sense with respect to the black level, or at the black level.

The analogue output of the converter 36 is converted to a digital signal by an ADC 38 to which a clamping circuit 54 is connected.

Gamma and aperture correction are applied in a digital corrector circuit 40 and the signal is passed to a transmitter 42. The ADC 38 is an iterative converter like that of Figure 1.

The signal is then transmitted by means of a transmitting antenna 44, a receiving antenna 46 and a receiver 48, to a CRT 50.

The transfer characteristics of the CRT 50 and the corrector 40 are shown, respectively, in Figures 3(a) and 3(b). The light output (y) of the CRT is related to the signal input (x) by the equation y = x25 as can be seen from Figure 3(a). This non-linear characteristic is compensated for by the corrector circuit 40 whose output (y) is related to its input (x) by the equation y = X04 Since 0.4 = 1/2.5, and on the realistic assumption that all other elements of the system are substantially linear, the light output of the CRT is substantially linearly related to the light input to the converter 36.

The transfer characteristic of the corrector 40 is very steep at low input levels, as can be seen from Figure 3(b). The low input signal region of Figure 3(b) indicated by the circle 52 is shown in Figure 3(c) on an enlarged scale.

Figure 3(c) also shows the input signal level 53 which corresponds to the black level, and the 8-bits of the MSB of the ADC 38, for various input signal levels. It can be seen from Figure 3(c) that the MSB changes to 0000,0001 at a signal level just below the black level. Thus the next change in the MSB (to 0000,0010) takes place a relatively long way up the characteristic, when the gradient of the characteristic has reduced. At this latter signal level therefore, there will be less amplification of discontinuities in the output of the ADC 38 caused by changes in the MSB or by inaccuracies in the amplification applied to the output of the ADC's comparator (equivalent to the comparator 22 of Figure 1), so that the image on the CRT is not flawed to an unacceptable degree.

One embodiment of the clamping circuit is shown in more detail in Figure 4. Its purpose is to clamp a change in the MSB of the ADC to a signal level slightly below the black level, so that the situation shown in Figure 3(c) is maintained, and the MSB does not change on the steepest part of the characteristic of the corrector 40. The MSB is provided by the ADC 56.

The circuit 54 receives an input signal at 58 from the converter 36 (Fig.2). An operational amplifier 60 combines the input signal 58 with a reference signal from a generator 62 to provide an input to the ADC 56. The input to the ADC 56 is biassed (that is, its D.C. level is controlled) by a feedback loop comprising a comparator 64 and an integrator 66.

The comparator 64 receives the output of the ADC 56 and a digital reference value, here shown as the value 0000,0001, and provides an output whose polarity depends on the result of the comparison. In this embodiment, a positive current output is provided when the ADC output is equal to or greater than 0000,0001 and a negative current output is provided when the ADC output is less than this value.

The output of the comparator 64 is applied to the input of the integrator 66. The integrator 66 is a simple circuit based on an operational amplifier 66' whose inverting input is fed through a resistor R1 and which has a capacitor C1 connected between this input and its output. The integrator 66 provides a voltage at its output terminal 68 which is the negative integral of the current at its input.

That is, a constant positive input current to the integrator 66 will cause a linear decrease in the voltage at 68.

The output 68 is used to apply d.c. bias to the input terminal 70 of the amplifier 60, and thereby to bias the amplifier output, which is the input of the ADC 56. The integrator output 68 and the generator 62 are connected through respective series resistors R3, R2 to the terminal 70. Thus, if the d.c. level of the generator output remains constant, a change in the integrator output voltage will change the d.c. level at 70 and the d.c. level of the output of the amplifier 60.

The circuit 54 further comprises a switch 72 which makes and breaks the connection between the comparator 64 and the integrator 66, under the control of a control circuit 74.

The circuit 74 opens and closes the switch 72 in response to clamping pulses CL which are received during periods in which the signal input 58 is blanked and at the black level.

When the switch 72 is open, the integrator 66 has no input current, and its output voltage remains constant.

The generator 62 also receives the clamping pulses CL which trigger the generation of a negative-going peak to be described.

Fig. 4 also shows a second clamping circuit 154 connected to clamp the LSB ADC 156.

The clamping circuit 154 is identical in structure and operation to the clamping circuit 1 54 except in one respect, and consequently is not described in detail. The difference is the absence of a signal generator equivalent to the generator 62 of the circuit 54. It is not necessary to generate reference signals in the LSB clamping circuit 154, because signals from the generator 62 can be used in this circuit also, as will be described.

The input to the LSB ADC 156 is the difference between the input signal at 58 and the signal represented by the output of the MSB ADC 56. This input is provided by a comparator 158 which incorporates an amplifier with a gain of x64. The clamping circuit 154 acts by biassing the negative input (which receives the output of the ADC 56 in analogue form) of the amplifier 158, so to bias the input to the ADC 156. The positive input of the amplifier receives the output of the MSB ADC 56, after conversion back to analogue form by the DAC 57.

An alternative embodiment of the clamping circuit is shown in Figure 5. Many elements shown in Fig. 5 correspond to elements shown in Fig. 4, and where this is the case, the same numerals are used in Fig. 5, with the suffix a. The purpose of the circuit 54a is to clamp a change in the MSB of the ADC to a signal level slightly below the black level, so that the situation shown in Figure 3(c) is maintained, and the MSB does not change on the steepest part of the characteristic of the corrector 40. The MSB is provided by the ADC 56a.

The circuit 54a receives an input signal at 58a from the converter 36 (Fig.2). The input signal at 58a is applied to an operational amplifier 60a, which provides an output 61. The low output impedance of the amplifier 60a allows the signal at 61 to be combined (or mixed) with an output signal from a signal generator 62a, by means of resistors R4 and R5, to provide an input to the MSB ADC 56a.

The amplifier 60a also allows the input 58a to be biassed (that is, its DC level to be controlled) by a feedback loop comprising a comparator 64a and an integrator 66a, as will be described. The output 61 is also taken, before the resistor R4, for supply to the LSB ADC, through the delay circuit 24. This output is the biassed input 58a, but the output of the generator 62a is not superimposed on it.

The comparator 64a receives the output of the ADC 56a and a digital reference value, here shown as the value 0000,0001, and provides an output whose polarity depends on the result of the comparison. In the embodiment, a positive current output is provided when the ADC output is equal to or greater than 0000,0001 and a negative current output is provided when the ADC output is less than this value.

The output of the comparator 64a is applied to the input of the integrator 66a. The integrator 66a is a simple circuit based on an operational amplifier 66' a whose inverting input is fed through a resistor R', and which has a capacitor C'1 connected between this input and its output. The integrator 66a provides a voltage at its output terminal 68a which is the negative integral of the current at its input.

That is, a constant positive input current to the integrator 66a will cause a linear decrease in the voltage at 68a.

The output 68a is used to apply d.c. bias to the input terminal 70a of the amplifier 60a, and thereby to bias the amplifier output, and hence the input of the ADC 56a. The integrator output 68a and the input 58a are connected through respective series resistors R'3, R'2 to the terminal 70a. Thus, if the d.c. level of the input at 58a remains constant, a change in the integrator output voltage will change the d.c. level at 70a and the d.c. level of the output of the amplifier 60a.

The circuit 54a further comprises a switch 72a which makes and breaks the connection between the comparator 64a and the integrator 66a, under the control of a control ciruit 74a. The circuit 74a opens and closes the switch 72a in response to clamping pulses CL which are received during periods in which the signal input 58a is blanked and at the black level. When the switch 72a is open, the integrator 66a has no input current, and its output voltage, at 68a, remains constant.

The generator 62a also receives the clamping pulses CL which trigger the generation of a negative-going peak to be described.

Fig. 5 also shows a clamping circuit 154a for the LSB ADC 156a. The circuit 1 54a is identical in structure and function to the clamping circuit 154 of Fig. 4 and so is not described further here.

The operation of the clamping circuits 54, 54a will now be described, with reference to the waveforms shown in the remaining Figures.

Figure 6 shows the signal levels at various points in the circuits 54, 54a, during the blanking period of the input signal 58, 58a when the ADC 56, 56a is clamped and the clamping has stabilised. In each case the vertical axis represents signal level and the three waveforms are plotted on the same, horizontal, time axis, shown at the bottom of the Figure.

The top waveform 76 represents the input of the ADC 56, 56a. Superimposed on the waveform are horizontal, broken lines indicating the signal levels at which the output of the ADC 56, 56a will change to the values indicated.

Initially the input 76 is slightly above the threshold for the output 0000,0001. At a time t, indicated by a broken, vertical line, the output of the generator 62, 62a drops, substantially instantaneously, before rising exponentially to its former value, by a time t2. This causes the input 76 similarly to drop and rise between these times.

These changes in the output of the generator 62, 62a are initiated by the arrival of a pulse CL, CL , shown as the bottom waveform in Figure 6. This pulse also causes the control circuit 74,74a to close the switch 72, 72a.

At time tl, or very shortly thereafter, the input 76 drops below the threshold for an ADC output of 0000,0001. The ADC output changes to 0000,0000. Since this value is less than 0000,0001, the output of the comparator 64, 64a now has a negative polarity.

The polarity of the comparator output is shown by the middle waveform 77 in Figure 5. At time t, the integrator 66, 66a is connected to the comparator 64, 64a and begins to integrate, so that the voltage at 68, 68a begins to rise (since a negative integral of the comparator output current is generated).

Eventually, at time t3 the exponentially rising level of the input 6 again crosses the threshold for an ADC output of 0000,0001. The ADC output changes, the comparator output changes polarity and the integrator output begins to drop. The input 76 remains above the threshold between the times t3 and t2, and so the integrator output continues to drop until the time t2. Then, the clamping pulse CL, CL' ends, the switch 72, 72a opens and the integrator output is locked to the value then obtaining, until the start of the next CL, CL' pulse in the next blanking period.

In the situation indicated in Figure 6, when the clamping circuit has settled down to a steady state, the rising exponential of the input 76 will cross the threshold for 0000,0001 exactly midway between the times t, and t2.

This has two effects. Firstly, the integral of the comparator output between times t1 and t3 will be exactly equal in magnitude but opposite in polarity to the same integral between times t3 and t2. Thus, the output of the integrator 66, 66a is the same at t2 as it was at t1 and the biasing applied has not been changed by the clamping operation. Secondly, because of the nature of the exponential waveform, the level of the signal 76 at time t2, which is equal to the level at time t,. will be only slightly higher than the threshold for the output 0000,0001.Since the signal input at 58, 58a is equal to the black level at times t, and t2, the output of the ADC 56, 56a is therefore clamped so that the threshold for the ADC output 0000,0001 lies a little below the black level of the input signal, and a subsequent increase in the level of the input 58, corresponding to movement of the signal along the steepest part of the gamma correction characteristic, will not change the output of the ADC 56. That is the 0000,0001 threshold is relatively close to and below the black level, and the 0000,0010 level is relatively far from and above the black level.

Figure 7 indicates how the clamping circuits 54, 54a operate to clamp the 0000,0001 threshold back to a level just below the black level, in the event that a drift in d.c. level occurs. The waveforms shown in Figure 7 occur at the same points in the circuits as the corresponding waveforms in Figure 6.

During a line of video information in the input signal 58, 58a that is during the period between clamp pulses, the switch 72, 72a will be open, so that the integrator output will remain constant. This in turn means that a constant bias will be applied to the ADC input. The output of the generator 62, 62a is nominally constant during this period.

If the d.c. level of the output of the generator 62, 62a or the black level of the input signal 58, 58a drifts during a line, for any reason, the input to the ADC 56, 56a will also drift, and accordingly, the separation between the 0000,0001 threshold and the black level will change.

The top waveform in Figure 7 represents the input 76 to the ADC 56, 56a when a drift has occurred during the previous line. The separation between the input 76 and the 0000,0001 threshold is greater than it is just before the time tin Figure 6. At both of these times, the input signal 58, 58a is blanked and at its black level, and so the 0000,0001 threshold is initially lower in relation to the black level in Figure 7 than in Figure 6. This in turn means that the 0000,0010 threshold will have moved down onto a steeper part of the gamma correction characteristic. Unless the drift is corrected, degradation of the image on the CRT is likely to occur.

Correction is performed by the clamping circuit 54, 54a during the clamping pulse which begins at time t4, At t4, the generator 62, 62a is triggered to produce a negative-going peak with a vertical leading edge and exponential trailing edge. This peak is superimposed on the input 58, 58a to give the ADC input 76.

At t4, the output of the ADC,56, 56a changes to 0000,0000 and the output 77 of the comparator 64, 64a consequently has negative polarity, as described above in relation to Figure 5. The integrator output begins to rise.

Eventually, at time t5, the level of the input 76 again crosses the 0000,0001 threshold, the comparator output reverses polarity and the integrator output begins to fall. The input 76 remains above the threshold and the integrator output continues falling from the time t5 until the time t6 when the clamping pulse ends.

Unlike the situation shown in Figure 6, the second crossing of the threshold by the input 76 does not take place midway between the times t4 and t6, because the input 76 is higher at t4 than at t,. The waveform 77 of the comparator output is, therefore, assymmetrical, and does not integrate to zero. The integrator output at time t6 is less than the output at time t4. The biassing applied by the circuit 54, 54a to the input signal 58 has therefore been lowered to compensate for the upward drift of the input signal. This change restores the 0000,0001 threshold of the ADC to the desired position just below the level of the input 76 when the input signal 58, 58a is at black level.

If the level of the input 76 drifted down, it would cross the threshold for the second time relatively late in the duration of the clamping pulse, and the biassing applied would increase, so as to restore the correct relationship.

The LSB clamping circuits 154, 1 54a are set in the same way as has been described with relation to Figs. 6 and 7. In these LSB clamping circuits the digital reference value 1000,0000 is used. This represents the midpoint of the range of possible values provided by the ADC 56, and is used in preference to 0000,0001 because the difference signal from the comparator 158 can be positive or negative. The MSB and LSB clamping circuits are preferably set at different times during the blanking period, by respective clamping pulses, to prevent the operation of one clamp ing circuit (including changing the output of the corresponding ADC) interferring with the operation of the other clamping circuit. For this reason, a reference signal generator is not required in the LSB clamping circuits 154, 154a.Reference signals provided by the generators 62, 62a appear on the output of the DAC 57, 57a. Accordingly, signals from the generators 62, 62c can be used for clamping both the MSB and the LSB ADCs 56, 156, 56a, 156a. When the generators 62, 62a are used in this way, they are supplied with both clamping pulses CL, CL' and generate a reference signal in response to each.

The circuits of Figs. 4 and 5 differ principally in the selection of the point at which the input to the LSB ADC is taken. Taking this input at the output of the comparator 60a, as in Fig. 5, means that the delay circuit 24 does not have to compensate for delays within the comparator 60a. Furthermore, the clamping circuit 54a corrects for drift in the input signal 58a before the signal is diverted to the LSB ADC, so that the clamping circuit 1 54a is only required to compensate for drifts within itself, the LSB ADC or the circuitry between the LSB ADC and the MSB ADC. The circuits of Figs.

4 and 5 also differ in the point of application of the reference signal. In each case this is applied after the signal for the LSB ADC has been taken. This choice also is made to prevent the two clamping circuits interfering with each other.

It can be seen from the above that the clamping circuit provides negative feedback between the ADC output and input to clamp an ADC threshold not to a characteristic level of the input signal, as simple negative feedback would do, but to a level just below this characteristic level. In this sense, the clamping circuit has a resolution higher than the resolution of the ADC 56. The separation of the black level and the clamped threshold is set by the characteristics of the reference waveform and so the accuracy of clamping is determined by the accuracy with which the reference waveform can be generated, and the choice of reference waveform.

The ADC threshold which is clamped is set by the reference input to the comparator 64, since this determines the value of the ADC output at which the comparator output polarity changes. In the embodiment described, the threshold for a low output value is chosen for the MSB, because signals a long way below the black level are not normal.

The bias provided by the integrators could be utilised at various points in the circuits if due regard is had of the polarities of signals and signal changes at these points, so as to ensure that the overall effect is to provide negative feedback between the output and input of the ADC, that is, feedback which acts to change the D.C. level of the input to the ADC in the opposite direction to any drift in the level. Furthermore, the integrators could be used to provide a positive or negative integral, according to the point of the circuit at which the feedback signal is applied and to whether the outputs of the ADCs and the comparators have the same phases or opposite phases as the corresponding inputs.

One alternative arrangement which has been found advantageous uses inverting ADCs, which generate an output 1111,1111 in response to a zero input, and a decreasing output in response to an increasing input. The digital reference values 1111,1101 and 1011,0000 are used for clamping the MSB and LSB respectively. These add to give an input of 11,1111,1111,0000 at black level.

After inversion to restore the original polarity, this output becomes 00,0000,0000,1111, so that a contrast range of approximately 1000:1 is possible in the output signal.

The circuit has been described in use in a telecine projector, but could be used in other television apparatus, such as television cameras. Moreover, the applications of the circuit are not restricted to television systems. The circuit can be used whenever an analogue signal to be converted to a digital signal has regularly occurring constant value plateaux, corresponding to television blanking periods, and there is a requirement to clamp a threshold of the ADC to a slightly different level.

If desired, a threshold could be clamped to a level just above a plateau by, for instance, arranging the generator 62 to produce a positive going spike and the integrator to generate a positive integral.

The exponential trailing edge of the peak generated by the generator 62 could be replaced by another waveform such as a linear trailing edge, giving the generator output a sawtooth waveform. However, the amplitude of the peak would then be much less, in order to provide the same separation between the threshold level and the black level. Decreasing the amplitude of a signal generally leads to increasing difficulty in accurate generation of the signal, and so the use of an exponential or other non-linear trailing edge is preferred.

Claims

1. A clamping circuit for an analogue to digital converter, comprising combining means for combining an input signal and a reference signal to provide an input for the converter, and a negative feedback circuit for biassing the input for the converter, the feedback circuit comprising a comparator for comparing the converter output and a digital reference value to provide an output whose polarity depends on the result of the comparison, an integrator for integrating the comparator output, and means for biassing the input for the converter according to the level of the integrator output.

2. A circuit according to claim 1 for clamp ing a stage of an iterative analogue to digital converter, wherein the circuit provides the input signal as an output for use in a following stage before the input signal is combined with the reference signal.

3. A circuit according to claim 1 or 2, wherein the biassing means bias the input signal before the signals are combined.

4. A circuit according to claims 2 and 3, wherein the output for the following stage is the biassed input signal.

5. A circuit according to claim 1 or 2, wherein the biassing means bias the reference signal before the signals are combined.

6. A circuit according to any preceding claim, in which the comparator output has positive and negative polarity when the converter output is more than and less than the reference value respectively, and the integrator generates a negative integral of its input.

7. A clamping circuit according to any preceding claim, further comprising a switch operable to make or break the connection between the comparator and the integrator.

8. A circuit according to claim 7, comprising means for closing the switch only during periods in which the input signal is blanked.

9. A circuit according to claim 8, further comprising means for supplying a reference signal which is nominally constant except during blanked periods of the input signal.

10. A circuit according to claim 9, in which the reference signal has a negative-going peak during blanked periods.

11. A circuit according to claim 10, in which the negative-going peak has a substantially vertical leading edge, and a substantially exponential trailing edge.

12. A circuit according to any preceding claim, in which the integrator and/or the combining means each comprise an operational amplifier.

13. A method of clamping the output of an analogue to digital converter in which a reference signal is combined with the input signal and negative feedback is applied from the converter output to bias the input signal, the output of the converter being compared with a digital reference value to generate a result signal whose polarity depends on the result of the comparison, the result signal being integrated to form an integral signal, and the biassing being set according to the value of the integral signal.

14. A method of clamping a stage of an iterative analogue to digital converter according to the method of claim 13, including providing the input signal as an output for use in a following stage before the input signal is combined with the reference signal.

15. A method according to claim 13 or 14, including biassing the input signal before the signals are combined.

16. A method according to claims 14 and 15 wherein the output for the following stage is the biassed input signal.

17. A method according to claim 13 or 14, including biassing the reference signal before the signals are combined.

18. A method according to any of claims 13 to 17, in which the result signal has positive and negative polarity when the converter output is more and less, respectively, than the reference value, and a negative integral of the result signal is formed.

19. A method according to any of claims 13 to 18, wherein integration only takes place during blanked periods of the input signal and wherein the biassing level is held at the level obtaining at the end of a blanking period during the succeeding unblanked period.

20. A method according to claim 19, including generating the reference signal to be nominally constant except during blanked periods of the input signal.

21. A method according to claim 20, in which the reference signal has a negative-going peak during blanked periods.

22. A method according to claim 17, in which the negative-going peak has a substantially vertical leading edge and a substantially exponential trailing edge.

23. A signal processing circuit for analogue signals having periodic blanking periods during which the signal has a nominally constant voltage, wherein the circuit comprises an analogue to digital converter including clamping means operable to maintain a threshold of the converter at a voltage level relatively slightly displaced in one sense from the nominally constant voltage and to maintain the adjacent corresponding threshold of the converter to be relatively greatly displaced in the opposite sense from the nominally constant voltage, irrespective of changes in the d.c. level of the signal.

24. A circuit according to claim 23, for analogue television signals, and further comprising a gamma correction circuit for correcting the output of the converter.

25. A circuit according to claim 23 or 24, wherein the maintained threshold is a threshold corresponding to a change in the most significant bit or byte provided by the converter.

26. A circuit according to claim 23, 24 or 25, wherein the converter is an iterative converter.

27. A circuit according to any of claims 23 to 26, wherein the clamping means comprise a clamping circuit according to any of claims 1 to 12.

28. A method of processing analogue signals having periodic blanking periods during which the signal has a nominally constant voltage, wherein the signals are converted by means of an analogue to digital converter, and the converter is clamped to maintain a threshold of the converter at a voltage level relatively slightly displaced in one sense from the nominally constant voltage and to maintain the adjacent corresponding threshold relatively greatly displaced in the opposite sense from the nominally constant voltage, irrespective of changes in the d.c. level of the signal.

29. A method according to claim 28, applied to television signals, in which gamma correction is applied to the output of the converter.

30. A method according to claim 28 or 29, wherein the maintained threshold is a threshold corresponding to a change in the most significant bit or byte provided by the converter.

31. A method according to claims 28, 29 or 30, in which the converter is an iterative converter.

32. A method according to any of claims 28 to 31, in which the converter is clamped by the method of any of claims 13 to 22.

33. A telecine projector comprising an analogue to digital converter for converting video signals generated by scanning a film image, and a clamping circuit according to any of claims 1 to 12, arranged to clamp a transition in the converter output to a signal level just below the black level of the video signal.

34. A clamping circuit for an analogue to digital converter, substantially as described above, with reference to Fig. 4 or Fig. 5 of the accompanying drawings.

35. A method of clamping an analogue to digital converter, substantially as described above, with reference to Figs.4,5,6 and 7 of the accompanying drawings.