JPH05291955A - A/d conversion bit expansion circuit - Google Patents

Abstract

PURPOSE:To provide the A/D conversion bit expansion circuit relating to a device requiring digital processing by adopting the configuration including especially a comparator circuit, a control circuit and an amplifier circuit for the A/D conversion bit expansion circuit. CONSTITUTION:An analog video signal SV from an analog input terminal 10 is fed to a sample-and-hold circuit 1 and its output SVS is fed to an amplifier circuit 4 and a comparator circuit 2. The circuit 2 compares N-kinds of REF signals set to a REF input terminal group 11 with the output SVS from the circuit 1 and outputs the result as an output SEL. The output SEL is fed to a control circuit 3, from which a control signal Ga in response to the output SEL is generated when the N-kinds of the REF signals have a prescribed relation. Then the signal Ga and the output SVS from the circuit 1 are fed to the amplifier circuit 4, in which the signal is amplified based on the level of the signal Ga. Thus, a small level signal is amplified at a higher gain by the circuits 2, 3, 4 when the level is lower, and the bit is shifted and the number of digital signal bits is expanded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD conversion bit expansion circuit, and more particularly to a digital signal for an analog video signal derived from an analog processing section in a video signal processing apparatus or an image pickup section in an image pickup apparatus such as a video camera. The present invention relates to an AD conversion bit expansion circuit for a device that needs to be digitized for the purpose of processing.

[0002]

2. Description of the Related Art In a video signal processing circuit, various kinds of signal processing are usually performed on an analog video signal input. In recent years, digital processing has also been adopted in this video signal processing circuit. For example, an A / D conversion circuit unit as shown in FIG. 6 has been conventionally used for a circuit that digitizes an analog video signal by A / D conversion and realizes signal processing as a digital circuit.

That is, as shown in FIG. 6, the conventional A / D conversion circuit section has an analog input terminal 25 and a gain control circuit 2.
3, an A / D converter 6, a digital processing circuit 24, and a digital output terminal 26. In the conventional A / D conversion circuit unit shown in FIG. 6, for example, the analog video signal Av derived from the analog signal processing unit is supplied to the analog input terminal 25, and further, the gain control circuit 23 is used to perform A / D conversion. Is supplied to the container 6.

Then, in the A / D converter 6, the analog video signal Av is A / D converted to form a digital signal D1. The digital signal DI from the A / D converter 6 is subjected to various processes in the digital processing circuit 24 to be a digital signal D2, which is output through the digital output terminal 26.

[0005]

In the conventional A / D conversion circuit portion for video signal processing, as described above, the analog video signal Av is A / D converted via the gain control circuit 23. It is supplied to the device 6 and converted into a digital signal D1 (see FIG. 6).

The analog video signal Av at that time generally has a relatively wide dynamic range, and because of the need for high S / N due to the increasing demand for high image quality in recent video equipment, an analog video signal is required. The A / D converter 6 for converting the signal Av into the digital signal D1 can cope with a relatively wide dynamic range of the analog video signal Av,
In order to realize high S / N digital signal processing, it is usually necessary to form the digital signal D1 as digital data having a bit number of 8 bits or more.

That is, the A / D converter 6 has a handling bit number of 8 bits or more. Thus, an A / D converter having a handling bit number of 8 bits or more becomes expensive, Moreover, power consumption is also large. Therefore, the conventionally used A / D conversion circuit section as shown in FIG. 6 has problems that the cost is high and the power consumption is disadvantageous.

Therefore, the present invention aims to provide an AD conversion bit expansion circuit that solves the above problems, and more specifically, it is possible to reduce the cost as compared with the conventional A / D conversion circuit section, and An object of the present invention is to provide an AD conversion bit expansion circuit which is advantageous in terms of power consumption.

[0009]

The AD conversion bit expansion circuit of the present invention includes a sample hold circuit, a comparison circuit, a control circuit, an amplification circuit, an A / D converter, a data latch, a shift control circuit, The configuration includes a bit shift circuit, in particular, a configuration including a comparison circuit, a control circuit, and an amplification circuit, thereby providing an AD conversion bit expansion circuit for the above purpose.

That is, the present invention comprises (A) a sample hold circuit for sample-holding an input analog signal, (B) a comparison circuit for comparing a reference level with a sample-hold level of an input signal, and (C) a comparison circuit. A control circuit that generates a control signal for the amplifier circuit according to the output of the circuit, (D) an amplifier circuit that amplifies the input according to the control signal, (E) A / D converter, (F) data latch, (G ) Shift control circuit that generates a shift amount according to the output of the comparison circuit, (H) Bit shift circuit that bit-shifts the input digital signal, (I) Analog input terminal, (J) Reference level input terminal group, (K) It consists of a digital output terminal, and (a) the analog video signal is
The reference signal group supplied to the sample hold circuit via the analog input terminal and (b) the output of the sample hold circuit and the reference level input terminal group is
(C) The output of the comparison circuit is supplied to the control circuit, (d) the output of the control circuit and the output of the sample-hold circuit are supplied to the amplification circuit, and (e) the amplification circuit. The output of the circuit is supplied to the A / D converter, (f) the output of the A / D converter is supplied to the data latch, (g) the output of the comparison circuit is supplied to the shift control circuit, (h) The output of the shift control circuit and the output of the data latch are supplied to a bit shift circuit, and (i) the output of the bit shift circuit is supplied to a digital output terminal. The main point is a decompression circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The AD conversion bit expansion circuit of the present invention will be described in more detail below with reference to the first and second embodiments of the present invention.

(Embodiment 1) A first embodiment (Embodiment 1) of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an AD conversion bit expansion circuit for explaining a first embodiment of the present invention, and FIG. 2 is a block diagram of a comparison circuit in the first embodiment. 3 and 4 are diagrams for explaining the operation of the first embodiment, which is an analog video signal Sv.
3 is a diagram showing waveforms of an output Sx of the amplifier circuit and the amplifier circuit, respectively.

In the first embodiment, as shown in FIG. 1, a sample hold circuit 1, a comparison circuit 2, a control circuit 3, an amplifier circuit 4, an A / D exchanger 6, a data latch 7, a bit shift circuit. 8, shift control circuit 9, analog input terminal 10, reference level input terminal group 11, digital output terminal 1
It is composed of 2. Further, the comparison circuit 2 in the first embodiment has the comparison circuit input terminal 1 as shown in FIG.
It is composed of 4, N comparators 13 (N is a natural number), a reference level input terminal group 11, and a comparison circuit output terminal group 15.

In the first embodiment, as shown in FIG. 1, the analog video signal Sv input to the analog input terminal 10 is supplied to the sample hold circuit 1.
Sampled and held by the clock FS. The output Svs of the sample-hold circuit 1 is supplied to the amplifier circuit 4 and the comparison circuit 2.

In the comparison circuit 2, as shown in FIG. 2, N kinds of reference signals REF1 set in the reference level input terminal group 11 of the comparison circuit 2,
REF2, ... REFN are N comparators 13 each.
Is supplied to one of the input terminals. The output Svs of the sample-hold circuit 1 passes through the comparison circuit input terminal 14 of the comparison circuit 2 and the N comparators 1 as shown in FIG.
3 is supplied to the other input terminal and is compared with each of the N types of reference signals REF1, REF2, ... REFN. The output of the comparator 13 is output via the comparison circuit output terminal group 15.

The output SEL of the comparison circuit 2 is supplied to the control circuit 3 (see FIG. 1). For example, N kinds of reference signals REF1 to REFN input to the reference level input terminal group 11 are REF1 <REF2 <... When the relation is <REFN, the control circuit 3 outputs the output SE of the comparison circuit 2.
A control signal Ga corresponding to L is generated.

Here, the output Ga of the control circuit 3 is controlled when the output Svs of the sample-hold circuit 1 and the reference signals REF1, REF2 ,. When the signal Ga = Ga 0 REF1 <Svs ≦ REF2, the control signal Ga = Ga 1 ········. REFN <Svs, the control signal Ga = Ga N.

The output Ga of the control circuit 3 and the sample ho
The output Svs of the output circuit 1 is supplied to the amplifier circuit 4, and the output Ga of the control circuit 3 is Is amplified to.

For example, the reference level input terminal group 1
When the reference signals REF1 and REF2 are set to 1 (N = 2), the analog video signal Sv changes linearly with time as shown in FIG. Thus, with respect to the analog video signal Sv that linearly changes with time,
This analog video signal Sv is the reference signal RE
During the period from t ₀ to t ₁ which is F1 or less, the amplifier circuit 4 is
The signal S that is 2 ² times the output Svs of the sample-hold circuit 1
4 is output, and Sv is REF1 <Sv ≦ R in the same manner.
During the period from t ₁ to t ₂ which is EF2, the double signal S2 is output, and during the period after t ₂ where Sv is larger than REF2, the single signal S1 is output (see FIG. 6). Note that FIG.
FIG. 4 is a diagram showing a waveform of an output Sx of the amplifier circuit related to the above example.

In the first embodiment, as shown in FIG. 1, the output Sx of the amplifier circuit 4 is A / D-exchanged by the clock FS in the A / D exchanger 6, and M bits (M is a natural number of 2 or more). ) Digital signal is formed and supplied to the data latch 7. The data latch 7 latches the digital conversion signal DX of the output Sx of the amplifier circuit 4 and supplies it to the bit shift circuit 8.

On the other hand, the output SEL of the comparison circuit 2 is supplied to the shift control circuit 9 as shown in FIG. The shift control circuit 9 outputs to the bit shift circuit 8 the bit shift number corresponding to the relationship between the output SEL of the comparison circuit 2, that is, the reference level (REF1, REF2, ... REFN) and the sample hold output Svs.

This bit shift number is a multiplication factor corresponding to the amplification factor of the amplifier circuit 4, and is Svs and REF1 to REF.
The relationship between N, the magnification of the amplifier circuit 4, and the number of bit shifts is as follows: when Svs ≦ REF1, magnification = 2 ^N times, bit shift number 0 When REF1 <Svs ≦ REF2, magnification = 2 ^N−1 times, bit shift number 1 · · · · · · · · · REFN < when Svs, magnification = 2 ⁰ × = 1 times the bit shift number N.

For example, in FIGS. 3 and 4, the output DX of the data latch 7 is equal to or less than the reference signal REF1.
_In the period from ₀ to t ₁ , the shift number is 0, and similarly, REF1
The number of shifts is 1 during the period from t ₁ to t ₂ where <D1 ≦ REF2, and the number of shifts is ₂ during the period after t ₂ where REF2 <D1.
And

The bit shift circuit 8 includes a data latch 7
Of the shift control circuit 9 and the output DX of the shift control circuit 9 are supplied to the output D of the data latch 7 in accordance with the output of the shift control circuit 9.
X is bit-shifted to the upper direction and digital output terminal 1
Output to 2.

In the first embodiment, the comparator circuit 2, the control circuit 3, and the amplifier circuit 4 amplify a small level signal with a higher gain as the level is lower, and after A / D conversion, bit shift according to the gain. Then, the number of bits of the digital signal is expanded. Therefore, in the first embodiment, a simple M + N-bit digital signal can be obtained by the M-bit A / D converter.

That is, according to the first embodiment, an A / D converter having a small number of bits can be used to support a video input signal having a relatively wide dynamic range, and a high S / N ratio can be achieved by simple bit expansion. A digital signal of is obtained. In the first embodiment, the bit shift circuit 8 performs a larger bit shift for a higher level signal. Generally, a high level signal in a video signal is "not required to have an S / N as high as a low level signal". Therefore, the rounding error due to the bit shift does not pose a problem.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of an AD conversion bit expansion circuit for explaining the second embodiment of the present invention.

The AD conversion bit expansion circuit of the second embodiment is
As shown in FIG. 5, it has a configuration including a γ-KNEE correction circuit 22. Except for this, the configuration is the same as that of the first embodiment, and since it is duplicated, its description is omitted. In the second embodiment, the output DV of the bit shift circuit 8 is
This γ-KNE is supplied to the γ-KNE correction circuit 22.
The output of the E correction circuit 22 is output via the digital output terminal 12. The connections other than the above are all the same as those in the first embodiment, and therefore the description thereof is omitted.

Further, in the second embodiment, γ-KNEE is used.
All the components other than the correction circuit 22 operate in the same manner as in the first embodiment. The output DV of the bit shift circuit 8 which is output in the same manner as in the first embodiment is a non-linear level based on the predetermined gamma input / output characteristics and KNEE input / output characteristics for the digital signal in the γ-KNEE correction circuit 22. The correction is performed, and its output is supplied to the digital output terminal 12.

The second embodiment can be suitably applied to the signal processing of the CCD camera, and when the digital signal is the target of γ-KNEE correction as in the second embodiment, the analog input signal Sv is compared. In order to cope with an extremely wide dynamic range and to perform effective γ-KNEE correction, the digital signal DX is usually required to have 10 bits or more. However, an A / D converter of 10 bits or more is extremely expensive and consumes a large amount of power, which is inconvenient for a portable VTR camera or still camera which is powered by a battery. Therefore, by using the second embodiment, it is possible to deal with an analog signal having a relatively wide dynamic range with an A / D converter having a small number of bits and perform appropriate γ-KNEE correction.

[0031]

According to the present invention, a comparator circuit, a control circuit, and an amplifier circuit amplify a small level signal with a higher gain as the level is lower, and after A / D conversion, bit shift according to the gain, Extend the bit number of the digital signal. Therefore, in the present invention, a simple M + N-bit digital signal can be obtained by the M-bit A / D converter.

That is, according to the present invention, A with a small number of bits is used.
By using the / D converter, it is possible to deal with a video input signal having a relatively wide dynamic range, and a high S / N digital signal can be obtained by simple bit expansion.

In the present invention, in the bit shift circuit,
The higher the level of the signal, the greater the bit shift, but in the video signal, the level of the high level signal is generally
Since it is said that "S / N as low as a low level signal is not necessary", the rounding error due to bit shift does not pose a problem. As described above, in the AD conversion bit expansion circuit of the present invention, since it is possible to use an A / D converter having a smaller number of bits than the required number of bits, the cost can be reduced and the consumption can be reduced as compared with the conventional one. It has an effect of being advantageous in terms of electric power.

[Brief description of drawings]

FIG. 1 is a block diagram of an AD conversion bit expansion circuit for explaining a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a comparison circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the first embodiment and is a diagram showing an analog video signal Sv.

FIG. 4 is a diagram for explaining the operation of the first embodiment, showing the waveform of the output Sx of the amplifier circuit.

FIG. 5 is a block diagram of an AD conversion bit expansion circuit for explaining a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional A / D conversion circuit unit.

[Explanation of symbols]

 1 sample hold circuit 2 comparison circuit 3 control circuit 4 amplification circuit 6 A / D converter 7 data latch 8 bit shift circuit 9 shift control circuit 10 analog input terminal 11 reference level input terminal group 12 digital output terminal 13 comparator 14 Comparison circuit input terminal 15 Comparison circuit output terminal group 22 γ-KNEE correction circuit 23 Gain control circuit 24 Digital processing circuit 25 Analog input terminal 26 Digital output terminal

Claims (2)

[Claims] 1. A sample-hold circuit for sample-holding an input analog signal, a comparator circuit for comparing a reference level with a sample-hold level of an input signal, and a control signal for an amplifier circuit according to the output of the comparator circuit. Control circuit, an amplifier circuit for amplifying the input according to the control signal, A /
Consists of a D converter, a data latch, a shift control circuit that generates a shift amount according to the output of a comparison circuit, a bit shift circuit that bit-shifts an input digital signal, an analog input terminal, a reference level input terminal group, and a digital output terminal. The analog video signal is supplied to the sample hold circuit via the analog input terminal, and the output of the sample hold circuit and the reference signal group input to the reference level input terminal group are supplied to the comparison circuit. The output of the comparison circuit is supplied to the control circuit, the output of the control circuit and the output of the sample-hold circuit are supplied to the amplifier circuit, and the output of the amplifier circuit is supplied to the A / D converter. The output of the D converter is supplied to the data latch,
The output of the comparison circuit is supplied to the shift control circuit, the output of the shift control circuit and the output of the data latch are supplied to the bit shift circuit, and the output of the bit shift circuit is
AD characterized by being supplied to a digital output terminal
Conversion bit expansion circuit. 2. A sample-hold circuit comprising: a comparison circuit input terminal, N comparators (N is a natural number), a reference level input terminal group, and a comparison circuit output terminal group. Is supplied to one input of N comparators via a comparison circuit input terminal, and each signal of the reference signal group input via the reference level input terminal group is N comparators. Of the N comparators, the outputs of the N comparators are supplied to the comparison circuit output terminal group, and the comparison circuit output terminal group is supplied to the control circuit and the shift control circuit. Item 1
The AD conversion bit expansion circuit described in 1.