JPH0484520A - A/d converter - Google Patents

Abstract

PURPOSE:To realize high resolution and to reduce power consumption by employing two A/D converters, providing an amplifier to a pre-stage of the one A/D converter so as to improve the resolution equivalently and implementing A/D conversion at an optional level. CONSTITUTION:An input signal from an input terminal 1 is inputted to an A/D converter 2 and an amplifier 3, a signal inputted to the A/D converter 2 is AD-converted in M-bits and the result is fed to an encoder 7. The signal inputted to the amplifier 3 is controlled by a control circuit 6, in which a prescribed DC shift is implemented and inputted to a limiter 4 while being amplified and subjected to amplitude limit at a prescribed dynamic range and fed to an A/D converter 5, in which the signal is A/D converted in N bits and the result is fed to the encoder 7. A K-bit digital signal including DC shift information and amplifier information generated by the control circuit 6 is fed to the encoder 7, in which the signal is converted into an L bit signal and outputted to an output terminal 8. Thus, high resolution is realized and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an AD conversion device used in video equipment such as a digital camera.

2. Description of the Related Art Recently, digital technology has become widely used in video equipment, and imaging devices such as video cameras are also becoming digital. The configuration of a conventional AD conversion device used for this type of digital processing will be explained with reference to the drawings.

FIG. 9 is a block diagram of a conventional AD conversion device. Since digital processing of video signals requires a conversion speed of several milliseconds, a parallel AD converter is generally used.

FIG. 9 is an example. In the figure, reference voltages 21, 2
2. is divided by a reference resistor network 23 consisting of 2N (N is the resolution of the AD converter expressed in focus) equal resistors, and each voltage is applied to a comparator 24 as a reference comparison voltage.

The analog signal voltage at input terminal 20 is applied to all comparators 24 in parallel. The comparator 24 compares the reference comparison voltage and the input analog voltage, detects a reference comparison voltage close to the input voltage, and sends the output of the comparator to the encoder 2.
In addition to 5, a digital signal is output to output terminal 2G. (Reference 2 Edited by Japan Broadcasting Corporation, Broadcasting Technology Book 8, Digital Technology in Broadcasting, published by Japan Broadcasting Publishing Association, 1982, pp.9
5 - Problems to be Solved by the Invention In such a conventional AD converter, if the resolution is N bits, (2N-1) comparators are required.

For example, if the resolution is 10 focus, the number is actually 1023.
This will consume a large amount of power and generate significant heat, so
The drawback was that it could not be integrated into one LSI chip. Therefore, an 8-bit AD converter is usually used.

FIG. 10 is an input/output characteristic diagram of the linear AD converter. To obtain good image quality, a resolution of 10 bits is desired in a video camera. However, as mentioned above, it is difficult to realize this in terms of power consumption.

Therefore, it is necessary to provide analog amplitude compression means in the preprocessing of the AD converter. Furthermore, since gamma correction is applied in a video camera, it is wasteful to quantize the entire amplitude as shown in FIG.

The present invention solves the above problems, and has low power consumption and high resolution in a predetermined signal level region. The purpose is to provide an AD conversion device.

Means for Solving the Problems In order to achieve the above objects, the present invention provides an analog signal input terminal, a first AD converter that converts the input analog signal into a digital signal, and amplifies the input analog signal and shifts the DC level. an amplifier, a limiter that limits the amplified analog signal within a predetermined range, a second AD converter that converts the output of the limiter into a digital signal, a control circuit that controls the gain and DC level of the amplifier; The encoder includes a second AD converter, an encoder connected to the control means, and a digital output terminal thereof.

Then, in order to partially increase the resolution, a digital signal containing the DC shift information and amplification gain information given to the amplifier is applied to the encoder.

Here, in order to prevent overflow of the second AD converter, the limiter output amplitude is limited within the range of the reference voltage of the second AD converter.

The encoder has a bit shifter for the output of the first AD converter, an adder for the output of the second AD converter and the output of the control circuit, a comparator for the upper bits of the bit shifter and the adder, and a digital output of the bit shifter and the adder. A selector is provided as an input and controlled by a comparator, and the selector is arranged to select either the bit shifter or the output of the adder depending on the output of the comparator.

In addition, in order to compensate for the offset of the analog circuit section,
A DA converter connected to the encoder, a subtracter between the input analog signal and the DA converter analog output, and a drive circuit that controls the amplifier by the outputs of the control circuit and the subtracter can be added.

The output of the subtracter is then applied to the drive circuit to adjust the amplifier control signal to control the DC level shift amount and gain of the amplifier.

In order to improve AD conversion accuracy, the difference between the input analog signal and the DA converter analog output is brought close to zero.

In addition, to avoid malfunction of analog offset compensation,
A switch is connected between the subtracter and the drive circuit and controlled by a limiter.

Then, the amplifier is controlled by turning on the female switch during the period when the limiter is not performing amplitude limitation.

Furthermore, in order to improve the S/N ratio, a low-pass filter is provided between the switch and the drive circuit.

Operation The present invention has the above-described configuration, and since the first and second AD converters are effectively arranged, it is compact, consumes little power, and can be operated at high speed and with high precision.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an AD converter according to an embodiment of the present invention. In FIG. 1, an input signal at an input terminal 1 is input to an AD converter 2 and an amplifier 3. The signal input to the AD converter 2 is AD converted into M hits and sent to the encoder 7. The signal input to the amplifier 3 is controlled by the control circuit 6, undergoes a predetermined DC shift, is amplified and input to the limiter 4, and after being amplitude limited to a predetermined dynamic range, the signal is converted into N bits by the AD converter 5. The signal is AD converted and sent to the encoder 7. The focused digital signal containing the DC shift information and amplification information generated in the control circuit 6 is sent to the encoder 7,
The encoder is configured to output it to the output terminal as an L-bit signal. The limiter voltage range of the limiter 4 is set so that the output signal amplitude of the limiter 4 is within the range of the upper reference voltage and the lower reference voltage of the AD converter 5. The encoder 7 can be configured as shown in FIG. 5, for example. In the figure, the M pinto output signal of the AD converter 2 is input to the pinto chic 30, converted to L bits, and input to the selector 32. Further, the upper M bits of the L-pinto output signal of the pinto chic 30 are input to the equal comparator 36.

The N-bit output signal of the AD converter 5 and the bit output signal of the control circuit 60 are input to the adder 31, and input to the selector 32 as an I-bit signal.

The upper M bits of addition 19.3x are input to the equal comparator 36, and the selector 32 selects the output signal of the adder 31 when the output signal of the equal comparator 36 is on, and selects the output signal of the adder 31 when the output signal of the equal comparator 36 is off. The output signal of the bit shifter 30 is selected and sent out as an L bit.

FIG. 3 shows an embodiment of the amplifier 3 of the AD conversion device of the present invention. Here, the voltage gain of the amplifier 3 is assumed to be 4. It is assumed that a waveform as shown in FIG. 4(A) is input to the input terminal 11. The signal sent from the control circuit 6 is applied to the input terminal 18, and is a direct current indicated by a broken line ■ in FIG. 4(A). A resistor 12 with a resistance value of R, a resistor 13 with a resistance value of 4R,
The input signal is amplified four times by the amplifier 14 (Fig. 4 (B)), and the input signal is amplified by a factor of 4 (Fig. 4 (B)), and a resistor 15 with a resistance value R, a resistor 1 with a resistance value R
6. Further inverted by amplifier 17 and output terminal 19
A waveform as shown in FIG. 4(C) appears. This signal is limited by the limiter 4 to a range between the upper reference voltage (2) and the lower reference voltage (3) of the AD converter 5, and is input to the AD converter 5 and subjected to AD conversion.

FIG. 2 is a diagram showing the human output characteristics of the AD conversion device of the present invention. In Figure 2, the 2N-1 step in the center is AD
This is the output of converter 5. The entire area corresponds to the output of the AD converter 2, and has 2M-1 steps. The bit data sent from the control circuit 6 is input to the input terminal 18 of the amplifier 3.
By adding it to the output of the AD converter 5, an offset is given as shown in FIG. can do. M=8. If N-8, the output bin I and accuracy L-IO of the encoder 7 can be set. Further, as shown in FIG. 2, since the resolution of a specific level of the input signal can be increased, efficient quantization can be performed even in nonlinear processing such as the gamma processing characteristics of a video camera.

Furthermore, as shown in FIG. 6, a feed hack loop can be created to compensate for the offset generated in the analog circuit section. In FIG. 6, the I-bit output of adder 31 (FIG. 5) is applied to a DA converter 33. The difference between the output of the DA converter 33 and the input signal of the input terminal 1 is obtained by the subtracter 34 and the difference between the output signal of the control circuit 6 and the input signal of the input terminal 1 is obtained by the subtracter 34.
By manually inputting the output signal of 4 to the drive circuit 35 and driving the control signal to the amplifier 3 so as to compensate with the output signal of the subtracter 34, the analog DC offset generated in the amplifier 3 and limiter 4 is canceled. can.

Furthermore, as shown in FIG. 7, the output signal of the subtracter 34 can be input to the drive circuit 35 via a switch 37. In this case, the switch 37 is controlled by the limiter 4, so that the switch 37 is closed during the period when the amplitude is not limited, and the switch 37 is opened during the period when the amplitude is limited, thereby avoiding malfunction of the analog DC offset compensation.

Furthermore, as shown in FIG. 8, the output of the switch 37 can be inputted to the drive circuit 35 via a low-pass filter (LPF) 38. The low-pass filter 38 removes unnecessary noise components, and the signal-to-noise ratio of the output signal of the encoder 7 is improved.

As described above, according to the AD converter according to the embodiment of the present invention, 2
Each AD converter is equipped with an amplifier in front of it to increase the resolution to any number of songs, and is arranged so that AD conversion can be performed at any level. Although the resolution is low, it is possible to exhibit high resolution overall, and power consumption can be kept low.

In the present invention, M=8. Although an example of N=8 is shown, other values may be used. Further, in the present invention, the case where the output signal of the control circuit 6 is DC level shift information is shown, but it is also possible to include amplification information. Further, the DC level shift amount may take any value within the operating range of the AD converter.

That is, it is possible to increase the resolution of the input signal portion with the lowest level, and it is also possible to increase the resolution of the input signal portion with the highest level.

Effects of the Invention As is clear from the above embodiments, according to the present invention, low-resolution AD converters are arranged in combination so as to interpolate with each other, so that high resolution can be achieved for a set signal level. Accordingly, it is possible to provide an AD converter with low power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an AD converter according to an embodiment of the present invention, FIG. 2 is an input/output characteristic diagram of the AD converter, and FIG.
The figure is a circuit diagram of the amplifier used in the AD converter, Figure 4 is a waveform diagram showing the signal from the input terminal of the AD converter to the second AD converter, and Figure 5 is the encoder in the AD converter. A block diagram showing an example, FIG. 6 is a block diagram of a second embodiment of the same AD conversion device, FIG. 7 is a block diagram of a third embodiment of the same AD conversion device, and FIG. 8 is a block diagram of the third embodiment of the same AD conversion device. FIG. 9 is a block diagram showing a fourth embodiment of the device, FIG. 9 is a block diagram of a conventional AD converter, and FIG. 10 is an input/output characteristic diagram of the conventional AD converter. 1...Input terminal, 2, 5...AD conversion means, 3...Amplifier, 4...Limiter, 6...Control circuit , 7... Encoder, 8... Output terminal. Name of agent: Patent attorney Shigetaka Awano

Claims (10)

[Claims] (1) an analog signal input terminal, a first AD converter that converts the analog signal at the input terminal into a digital signal, an amplifier that can amplify the analog signal at the input terminal and shift the DC level; a limiter that limits an output analog signal to a predetermined dynamic range; a second AD converter that converts the output analog signal of the limiter into a digital signal; a control circuit that controls the gain and DC level of the amplifier; an AD converter, an encoder connected to the first and second AD converters, the control circuit, and a digital output terminal of the encoder;
conversion device. (2) The control circuit inputs a digital signal containing the DC shift information and amplification information given to the amplifier to the encoder,
2. The AD converter according to claim 1, wherein the encoder is arranged so that a digital signal having a resolution higher than that of the first and second AD converters is partially obtained at the output terminal. (3) The AD converter according to claim (1), wherein the limiter is arranged to limit the output signal amplitude within the reference voltage range of the second AD converter. (4) The encoder is a bit shifter that converts the number of bits of the digital output of the first AD converter, an adder between the digital output of the second AD converter and the digital output of the control circuit, and the respective outputs of the bit shifter and the adder. a comparator for the upper bits of the bit shifter and a selector that receives the respective digital outputs of the bit shifter and the adder as input and is controlled by the output signal of the comparator, and the selector selects the bit shifter or the adder according to the output signal of the comparator. 2. The AD converter according to claim 1, wherein one of the digital outputs is selected and displayed on the output terminal. (5) an analog signal input terminal, a first AD converter that converts the analog signal at the input terminal into a digital signal, an amplifier that can amplify the analog signal at the input terminal and shift the DC level; a limiter that limits an output analog signal to a predetermined dynamic range; a second AD converter that converts the output analog signal of the limiter into a digital signal; and a control circuit that generates control signals for the gain and DC level of the amplifier. , said first
and a second AD converter, an encoder connected to the control circuit, a DA converter connected to the encoder, a subtracter between the analog signal of the input terminal and the analog output signal of the DA converter, and the An AD conversion device comprising: a drive circuit that controls the amplifier according to an output signal from a control circuit and the subtracter; and a digital output terminal of the encoder. (6) The output signal of the subtracter is provided to a drive circuit, and an amplifier control signal sent from a control circuit via the drive circuit is adjusted to control the DC level shift amount and gain of the amplifier. (5) AD conversion device described. (7) The AD converter according to claim (5), wherein the AD converter is arranged so that the difference between the analog output signal of the DA converter and the input analog signal of the input terminal approaches zero. (8) an analog signal input terminal, a first AD converter that converts the analog signal at the input terminal into a digital signal, an amplifier that can amplify the analog signal at the input terminal and shift the DC level; a limiter that limits an output analog signal to a predetermined dynamic range; a second AD converter that converts the output analog signal of the limiter into a digital signal; and a control circuit that generates control signals for the gain and DC level of the amplifier. , said first
and a second AD converter and an encoder connected to the control circuit, a DA converter connected to the encoder, and a subtracter between the analog signal of the input terminal and the analog output signal of the DA converter; a drive circuit that controls the amplifier using output signals from the control circuit and the subtracter; a switch connected between the subtracter and the drive circuit and controlled by the limiter; a digital output terminal of the encoder; AD conversion device including. (9) Apply the output signal of the subtracter to the driver via the switch, close the switch only during the period when the limiter is not performing amplitude limiting operation, and output the amplifier control signal sent from the control circuit via the drive circuit. 9. The AD converter according to claim 8, wherein the AD converter is arranged to control the DC level shift amount and gain of the amplifier. (10) The AD converter according to claim (8) or (9), further comprising a low-pass filter disposed between the switch and the drive circuit.