US6952240B2 - Image sampling circuit with a blank reference combined with the video input - Google Patents
Image sampling circuit with a blank reference combined with the video input Download PDFInfo
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- US6952240B2 US6952240B2 US09/860,905 US86090501A US6952240B2 US 6952240 B2 US6952240 B2 US 6952240B2 US 86090501 A US86090501 A US 86090501A US 6952240 B2 US6952240 B2 US 6952240B2
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- 238000005070 sampling Methods 0.000 title description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 57
- 238000012937 correction Methods 0.000 claims description 13
- 238000003384 imaging method Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 15
- 238000012546 transfer Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005267 amalgamation Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45504—Indexing scheme relating to differential amplifiers the CSC comprising more than one switch
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled
Definitions
- the present invention relates to an analog front-end (AFE) for an imaging sensor, and in particular to a correlated double sampler (CDS), programmable gain amplifier (PGA), and sample and hold circuit (S/H) for CCD signal digitization.
- AFE analog front-end
- CDS correlated double sampler
- PGA programmable gain amplifier
- S/H sample and hold circuit
- Imaging systems which may support a CCD sensor or a CMOS sensor typically require an AFE chip which samples the analog signal under control of a timing generator. Typically, a voltage amplifier is used. The sampled signal is then amplified and provided to a separate chip for digitization and subsequent processing.
- the present invention provides a programmable gain amplifier having three separately programmable amplifiers. First, a programmable transconductance amplifier is used. This is followed by a programmable transimpedance amplifier. Finally, a programmable switched capacitor amplifier is used.
- this programmable gain amplifier is implemented in an analog front-end (AFE) circuit.
- AFE analog front-end
- a differential input is provided to a DC restore clamp, then to a black reference level sampler circuit, and then to the programmable gain amplifier.
- transconductance amplifier provides the ability to improve the signal to noise ratio by maximizing the ratio of the signal current to the constant bias current, within the constraints of allowable power dissipation.
- This amplifier is not limited by the supply voltage, as are prior art voltage amplifiers.
- the combination of a transconductance and trans impedance amplifier allows the gain to be changed without adversely affecting the bandwidth.
- Traditional operational amplifiers cannot accommodate a wide bandwidth over a significantly changing range of gains.
- One embodiment of the invention also provides for both coarse and fine offset adjustment, by providing both pre- and post-gain offset adjustments.
- the coarse offset is provided in the black reference level sampler
- the fine offset is provided in the programmable switched capacitor amplifier.
- the voltage reference of the black reference sampler is two separate voltage references. Each of these voltage references can be independently programmed through a digital-to-analog converter (DAC) input from the external digital processing circuitry. This thus allows pre-gain offset correction to be combined with the black reference signal.
- DAC digital-to-analog converter
- the zero level of the video signal is made to correspond to the zero level of an analog to digital converter (ADC) in the switched capacitor amplifier.
- ADC analog to digital converter
- the ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier.
- the invention implements a piece-wise linear approximation of an exponential gain function.
- the transconductance and transimpedance amplifiers are programmed to provide exponential jumps in gain, while the switched capacitor amplifier is programmed to interpolate as needed between the gain levels of the transconductance and transimpedance amplifiers.
- the selection circuitry and resistor values are chosen to enable an even multiple of the gain to be selected by changing only certain most significant bits (MSBs) of the gain control register, simplifying user programmability.
- FIG. 1 is a block diagram of an AFE according to an embodiment of the invention.
- FIG. 2A is a timing diagram illustrating the black reference and video level signals.
- FIG. 2B is a graph illustrating the piece-wise linear approximation of an exponential function, with the power of two gain factors being set by an MSB of the programmable gain input.
- FIG. 3 is a block diagram illustrating the black reference sampler circuit connected to a DC restore clamp.
- FIG. 4 is a diagram of an embodiment of the transconductance amplifier of FIG. 1 .
- FIG. 5 is a diagram of the transimpedance amplifier of FIG. 1 .
- FIG. 6 is a diagram of a switched capacitor amplifier (SCA) used in FIG. 1 .
- SCA switched capacitor amplifier
- FIG. 7 is a high-level block diagram of an embodiment of the switched capacitor amplifier.
- FIGS. 8 , 9 and 10 are diagrams of three embodiments of SCA architectures useful for explaining the operation of the SCA of FIG. 6 .
- FIG. 11 is a timing diagram illustrating the operation of the circuits of FIGS. 6-10 .
- FIG. 12 is a diagram of one embodiment of elements 48 & 50 of FIG. 6 .
- FIG. 1 illustrates an AFE according to the invention.
- a CCD input is provided on a line 12 , with a reference input being provided on a line 14 .
- These are connected through external capacitors 16 and 18 , respectively, to a DC restore clamp 20 .
- the output of DC restore clamp 20 is provided to a black reference sampler circuit 22 according to this invention.
- the output of the black reference sampler circuit is provided to a programmable transconductance amplifier 24 , which is coupled to a programmable transimpedance amplifier 26 , which in turn is coupled to a programmable switched capacitor amplifier 28 .
- the AFE is designed to convert the CCD output signal into a corrected signal for an analog-to-digital converter (ADC) by performing gain, offset correction and elimination of pixel-to-pixel variations.
- ADC analog-to-digital converter
- the gain is programmed by a value input by a user to a programmable gain input register 15 . This value is provided to gain selection logic 17 , which determines the appropriate gain settings for the three amplifiers, and provides appropriate control signals on lines 19 , 21 and 23 . Multiples of the gain are provided by the transconductance amplifier 24 and the transimpedance amplifier 26 . Interpolation between those multiples, as needed, is provided by switched capacitor amplifier 28 .
- the coarse offset correction is controlled by line 25 to black reference sampler 22 , to provide a pre-gain offset correction.
- a fine offset correction is provided post-gain in switched capacitor amplifier 28 by control input 27 .
- the zero level of the video signal at the switched capacitor amplifier 28 is made to correspond to the zero level of an analog to digital converter (ADC) in the switched capacitor amplifier.
- ADC analog to digital converter
- the ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier, using ADC reference input 52 .
- FIG. 2A is a timing diagram illustrating the CCD input signals provided to the circuit of FIG. 1 . Shown first is a reset signal pulse 30 . This is done for each pixel sampled. It is followed by a black reference level signal 32 . Subsequently, the video signal 34 is provided. The value of the video signal is indicated by arrows 36 as the difference between the video level and the black reference level. This series of three levels repeats itself for each pixel. The black reference level corresponds to the pixel information when no light is present. The final (video level) period corresponds to the video signal containing the pixel brightness information.
- FIG. 2B shows an exponential gain curve 29 .
- the gain is set to points corresponding to multiples of 2 (base 2), as illustrated by points 2 ⁇ , 4 ⁇ and 8 ⁇ .
- the switched capacitor gain is set to interpolate, with a piece-wise approximation to the exponential curve indicated by lines 31 , 33 and 35 .
- the number of pieces can be varied according to the desired design.
- the gain can be set to double in response to the change of just one or a few MSBs of the input gain value in the programmable gain input register.
- the DC restore clamp 20 in FIG. 1 is used to provide an offset which is sampled once per line of the CCD.
- FIG. 3 is a diagram of a DC restore clamp and black reference sampler circuits.
- the purpose of the DC restore clamp is to set the common mode voltage at the input of the sampling circuit.
- the CCD signal is a single ended signal with the common mode voltage usually determined by the manufacturer of the CCD. To improve the noise, a differential signal must be created.
- the CCD signal and an external reference (usually ground) are applied through two external capacitors, C 16 and C 18 .
- the clamping circuit consists of a low impedance voltage reference 40 and switches 42 , 44 controlled with external circuitry.
- the Vclamp switches 42 , 44 are closed during a known period of optically black pixels to establish the Vclamp voltage onto the circuit side of the external capacitors.
- the CCD signal is coupled to an internal capacitor C 303 and the other reference input to internal capacitor C 304 , which are then connected to a sampling circuit.
- the purpose of the sampling circuit function is to sample the voltage during the black reference period of the CCD output signal. By closing the sampling switch during this period, the black level voltage is forced onto one side of C 303 and a low impedance source, VB 1 , is forced onto the other side. At the same time, C 304 samples the external reference with respect to another low impedance reference voltage, VB 2 . By controlling (through control line 25 ) the difference between VB 1 and VB 2 , a pre-gain offset can be introduced into the signal path. This offset could be used to correct for the difference between the CCD reference voltage and the CCD optically black output signal or the input referred offset of the PGA amplifier.
- This pre-gain voltage correction is usually supplied by a digital-to-analog (DAC) converter and several control algorithms could be used to determine the amount of correction.
- DAC digital-to-analog
- the black reference sampler also has the means to be bypassed and a differential input to be supplied to the transconductance amplifier.
- FIG. 4 illustrates one embodiment of the transconductance amplifier.
- This first stage of the PGA helps keep the noise on the output low by first converting the signal voltage of the CCD input into a current.
- By maximizing the signal current to the constant bias current we can maximize the signal to noise ratio of the current. This is done by increasing the signal current, compared to the bias current, as much as possible, within the design's power dissipation limits. This minimizes the noise without being limited by the voltage supply level, as in traditional operational amplifiers. This is increasingly important as new designs use lower voltage levels, such as the 3 volt and lower circuit designs.
- the topology used also has the advantage of maintaining a high bandwidth because the voltage gain is constant, independent of the gain selected. As the maximum amplitude of the input signal is decreased a lower gain determining resistor can be selected to maintain the signal current at its maximum value. Two such resistors 29 and 31 are illustrated, but any other number could be used. Since the gain selection switches ( 33 , 35 ) are in series with the output ( 37 , 39 ), and in the feedback loop of the amplifier, the voltage to current gain is primarily determined by the selected resistor. The gain matching is therefore primarily determined by resistor matching. By using exponential ratios for the resistors, the gain will be exponential. By choosing a power of two exponential variation, an exact power of two change in gain can be achieved.
- FIG. 5 shows one embodiment of a transimpedance amplifier 26 .
- the output current of the transconductance amplifier is converted to a voltage by transimpedance amplifier 26 with programmable feedback resistors ( 41 , 43 , 45 , 47 ), to allow for additional gain trimming.
- These programmable resistors are also in exponential ratios, and are programmed using select lines 21 , as described in FIG. 1 . This amplifier will therefore generate a low impedance, high bandwidth output of the original CCD input signal with a low noise content.
- This output signal (on lines 49 , 51 ) is continuous in time, follows the CCD output signal with a gain determined by the selected gains of the transconductance and transimpedance amplifiers and has been corrected for pixel-to-pixel variations of the black reference level and other measurable offsets. This is then sampled by the switched capacitor amplifier 28 .
- the final stage of the AFE is a switched capacitor amplifier (SCA) designed to sum three separate input signals.
- SCA switched capacitor amplifier
- a block diagram of the stage is shown in FIG. 7 and a complete circuit description in FIG. 6 . It performs multiple functions on the CCD signal: programmable gain, sample and hold, level shifting, and offset correction. Each operation is required in order to make the signal suitable for digitization by the ADC.
- the purpose of the SCA is to provide the linear gain control required to complete the piece-wise linear gain transfer function.
- the gain applied to video signals 49 and 51 is programmed by select lines 23 which adjust the capacitance of variable capacitor blocks 48 and 50 (shown in more detail in FIG. 12 ).
- variable capacitors consist of an array of n parallel capacitors n ⁇ 1 of which being switchable to either signal ground or the SCA's video input.
- the video signal has a duty-cycle between 25% and 50%.
- many ADCs require a 50% duty-cycle.
- the sample and holding action of the SCA increases the video signal duty-cycle to 50% or greater.
- the prior AFE stages have converted the single ended CCD signal into a differential video signal, the zero level of the video signal does not correspond with the zero signal level of most fully differential ADC converters which is typically ⁇ 1 ⁇ 2 of the ADC's full scale input range. For this reason a level shift of the zero signal level is required in order to align the AFE's zero signal level with that of the ADC reference.
- This SCA architecture can perform this level shift particularly accurately over process, temperature and supply voltage changes by actually sampling the ADC reference and subtracting it directly from the video signal. This sampling is done by the reference voltage input on lines 52 .
- the architecture allows this level shift to be subtracted without any dependence on the signal gain thus eliminating the need to scale the offset with SCA gain setting.
- FIGS. 8 , 9 and 10 Three simple SCA architectures are shown in FIGS. 8 , 9 and 10 .
- the topologies are very similar in operation, but have slightly different transfer functions.
- the operation of the first two will be described in detail.
- the third will then be shown to be an amalgamation of the first two.
- the operation of the circuit of FIG. 6 will be easily explained as a fully differential implementation of that in FIG. 10 .
- the timing diagram of FIG. 11 applies to FIGS. 6 through 10 and all switches are active high.
- FIG. 8 is a very simple implementation of a sample and hold amplifier.
- a two-phase non-overlapping clock governs all of the switching.
- ⁇ 1 the first phase of the non-overlapping clock, switches S 1 , S 2 , and S 3 are closed.
- the potential difference between voltages vin and vref is applied to capacitor C 1 and a proportional charge stored on the C 1 .
- ⁇ 2 switches S 4 and S 5 are closed.
- the closing of S 5 creates a negative feedback loop around OA 1 and that of S 4 places capacitor C 1 between OA 1 's inverting input, inn, and ground.
- the circuit of FIG. 9 is very similar in operation to that of FIG. 8 .
- the main difference being that the voltage at node Vin during ⁇ 1 is sampled on both C 1 and C 2 .
- the main advantage of this stage over the previous one being that it can create a higher gain with a lower feedback factor which can result in better bandwidth in the correct conditions.
- FIG. 10 In order to create an SCA with multiple inputs, additional voltage sampling capacitors are added between appropriate input voltages and inn in the circuit of FIG. 9 .
- the resulting topology is shown in FIG. 10 .
- the circuit of FIG. 10 can be viewed as a super-position of the circuits of FIGS. 8 and 9 , and will behave as a summing sample and hold amplifier. It samples the voltages at nodes Vin, ADC ref, and offset during ⁇ 1 , scales each voltage either by C 1 /C 2 or (1+C 1 /C 2 ), depending on whether or not the feedback capacitor was used to sample the signal voltage, and produces a voltage equal to the sum of the scaled and sampled voltages at its output.
- the transfer function for the circuit of FIG. 10 is given in equation 1 below.
- the circuit of FIG. 6 is simply a fully differential version of the circuit in FIG. 10 incorporating variable capacitors C 1 (n)-C 2 (n) in order to apply a variable voltage gain to the potential difference between vinp and vinn.
- Differential input voltages vinp-vinn, adcreffn-adcreffp, and offp-offn are sampled across the series connected capacitor pairs C 1 -C 4 , C 5 -C 6 , and C 7 -C 8 , respectively, during ⁇ 1 .
- the charges stored on caps C 1 -C 8 are transferred via negative feedback onto capacitors C 3 -C 4 , creating a differential output voltage proportional to the sum of the differential input voltages.
- equation 2 describes the mechanism by which programmable gain is applied to the video signal.
- the second term shows the summation of the ADC full-scale reference with the video signal in order to align the zero video level and the ADC zero reference level.
- the last term shows the summation of an offset calibration term which could be generated by either a digital or analog offset feedback control loop.
Abstract
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US09/860,905 US6952240B2 (en) | 2001-05-18 | 2001-05-18 | Image sampling circuit with a blank reference combined with the video input |
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Cited By (13)
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US20040252209A1 (en) * | 2003-06-11 | 2004-12-16 | Innovative Technology Licensing,Llc | Digital programmable gain stage with high resolution for CMOS image sensors |
US20050052555A1 (en) * | 2003-09-09 | 2005-03-10 | Yusuke Shirakawa | Signal processing apparatus, signal processing method, program, and storage medium |
US20060033561A1 (en) * | 2004-08-16 | 2006-02-16 | Texas Instruments Incorporated | Reducing Noise and/or Power Consumption in a Switched Capacitor Amplifier Sampling a Reference Voltage |
US20070022466A1 (en) * | 2005-07-22 | 2007-01-25 | Stmicroelectronics S.A. | Automatic adaptation of a video source to a receiver |
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