JPS6228892B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase shift circuit that shifts the phase of an analog signal.

Conventionally, there has been a circuit of this type as shown in FIG. In Figure 1, 1 is an integrator circuit consisting of a coil L and a capacitor C, 2 is an operational amplifier with the integrator circuit 1 connected to its input terminal, 3 is a resistor connected between the input and output terminals of the operational amplifier 2, and 4 is a variable Resistor,
5 is a coil connected in parallel to resistor 3 via variable resistor 4; 6 is a sample-and-hold circuit having an input connected to the output terminal of operational amplifier 2; and 7 is an input connected to the output terminal of sample-and-hold circuit 6. It is an analog-to-digital converter with

Next, the operation will be explained. When the analog signal S shown in FIG. 2 is input to the operational amplifier 2 via the integrating circuit 1 from time t ₀ , the signal 2a of the operational amplifier 2 will have the envelope E ₁ ,
E ₂ , after which it becomes a steady state and becomes a signal with a phase delay (or lead) of an angle Θ relative to the signal S, which is input to the sample-and-hold circuit 6 . The output of the sample hold circuit 6 is supplied to the outside via an analog/digital converter 7.

Since the conventional phase shift circuit is configured as described above, the integrator circuit 1 consisting of the coil L and the capacitor C
When the analog signal S is input to the operational amplifier 2 via the analog signal S, it exhibits a transient response for a considerably long period of time, and therefore has the disadvantage that it is not suitable for phase shifting of a signal having a waveform of a transient phenomenon.

This invention was made to eliminate the above-mentioned drawbacks of the conventional ones. By delaying the signal with a clock-driven sample and hold circuit, it is possible to shift the phase without distorting the signal due to transient response. The purpose of this invention is to provide a phase shift circuit that can perform the following steps.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of the phase shift circuit of the present invention. In Figure 3, 8 connects the analog signal S to the input terminal IN, and the clock signal C ₁ to the clock terminal.
Sample and hold circuit input to CLK, 9 is a clock generator that generates clock signal _C1 , 10
is a shift circuit consisting of a monostable circuit that inputs the clock signal _C1 , adjusts its phase by a variable resistor VR to shift it by Δt, and outputs the clock signal _C2 ; 11 is the signal of the sample and hold circuit 8; A sample hold circuit with 8a inputted to the input terminal IN and clock signal _C2 inputted to the clock terminal CLK,
Reference numeral 12 denotes an analog-to-digital converter that digitally converts the signal 11a of the sample-and-hold circuit 11 and outputs it to the outside.

Next, the operation will be explained with reference to the waveform diagram in FIG. The clock generator 9 sequentially outputs the clock signal _C1 at every time _ts , and the sample and hold circuit 8 samples and holds the analog signal S using the clock signal _C1 to obtain a signal 8a. The sample and hold circuit 11 samples and holds the signal 8a using a clock signal _C2 which is delayed by a time Δt from the clock signal _C1 , thereby obtaining a signal 11a (dotted line shown in FIG. 4). Here, the time Δt may be any time that does not overlap with the timing of the clock signal _C1 output from the sample and hold circuit 9.

The analog/digital conversion circuit 12 receives the signal 11a from the sample and hold circuit 11, converts it into a digital signal, and outputs the digital signal.

Note that in order to avoid overlapping the phase of the clock signal of the sample-and-hold circuit in the previous stage, it is also possible to connect as many sample-and-hold circuits in series as many stages as possible to obtain the desired phase by using a clock signal whose phase has been shifted by a shift circuit. good.

As described above, according to the present invention, at least two stages of sample and hold circuits are connected in series, and an analog signal input to the first stage of sample and hold circuit is sampled and held using a clock signal, and a stepped analog signal is output. At the same time, the step-like analog signal from the sample-and-hold circuit in the previous stage, which is input to the sample-and-hold circuit in the second and subsequent stages, is sampled and held using a clock signal that is shifted by a predetermined phase using a shift circuit. Even if the signal changes drastically, the desired phase shift can be obtained with little signal distortion, and since the operation is controlled by the clock, there is an effect of stabilization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional phase shift circuit, FIG. 2 is a waveform diagram of the phase shift circuit shown in FIG. 1, FIG. 3 is a block diagram of a phase shift circuit according to an embodiment of the present invention, and FIG. is a waveform diagram of the phase shift circuit shown in FIG. 3; 6, 8, 11...sample hold circuit, 7,
12...Analog-digital converter, 9...Clock generation circuit, 10...Shift circuit.

Claims (1)

[Claims] 1. A clock generation circuit that generates a clock signal at a predetermined period, a shift circuit that shifts the clock signal by a predetermined phase, and a first clock generation circuit that samples and holds an analog input signal using the clock signal and outputs a stepped analog signal. and a second sample-and-hold circuit that samples and holds the step-like analog signal that is the output signal of the first sample-and-hold circuit using a clock signal that is shifted in phase by a predetermined phase from the clock signal of the clock generation circuit from the shift circuit. A phase shift circuit with a sample and hold circuit.