JPH02124145A - Ultrasonic diagnostic device - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and to prevent a noise generation due to a control clock from being made into a problem by executing a large delay with a rough time quantization through the use of a first delaying means with a sampling to each reception and, thereafter, phasing and adding a small delay with a small time quantization through the use of a second delaying means. CONSTITUTION:Amplifier outputs 1, 2,-(n) from respective receiving elements are inputted to first delaying means SC-1, SC-2,-SC-n by sampling, respectively. Respective outputs of the first delaying means are current-converted by voltage/ current converters VI-1, VI-2,-VI-n and inputted to a switching means MPX with n-input and N-output. Respective input signals of the switching means are selectively connected to output terminals Q1, Q2,-QN of the switching means so as to execute the small delays corresponding to the delay quantities of respective receiving element by means of a control signal phiX from a control means. The switching means outputs are inputted to respective taps of a second delaying means DL to execute the small delay, current-added and, thereby, outputted to an output terminal Z-1 as a phasing output. As the second delaying means, for example, an analog LC delay line with a tap can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ultrasonic receiving phasing circuit suitable for use in an electronic scanning ultrasonic diagnostic apparatus.

[Prior art] A conventional wave receiving phasing circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-1985.
As described in No. 44, after the received signal 4 from each element is slightly delayed by sampling delay means, the receiving signal is adjusted by selectively inputting it to the second delay means which provides a relatively large delay using the switching means. He was doing phase.

[Problems to be Solved by the Invention] The above-mentioned conventional technology requires minute delay means by sampling for each receiving element, so there is a large number of minute delay means, and the phases are slightly different (for example, 1-
(On, about s) required a large number of control tarocks.

For example, as shown in FIG. 6, when sampling is performed using a sampling clock φS with a sampling period T, the quantization unit of the conventional relatively large second delay means is T (for example, 100 ns), and the ultrasonic beam is designed ”2 If the required quantization value Δ (for example, Ions) is the sampling clock C of the first delay means by sampling,
1, C2°C3 phase difference Δτ], Δτ2. Δτ3 is 1.
It is necessary to control the sampling clock variably from 0 to 90 ns at 0 ns. Therefore, it is necessary to control the sampling clock independently for the minute delay means for each receiving signal 4, which increases the circuit scale due to control wiring. to do and
There is a problem in that noise is generated due to crosstalk between control clocks and signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a receiving phasing circuit which has a small circuit scale and in which noise generation due to a control clock does not pose a problem.

[Means for Solving the Problems] In order to achieve the above object, the present invention first performs a large delay with coarse time quantization on each received signal using a first delay means using sampling, and then Small delays with low time quantization can be achieved using a current addition method, or by phasing and addition using a second delay means such as a C delay line or a sample-and-hold circuit connected in series. This is a phase circuit.

[Operation] The eleventh delay means using sampling performs a large delay with coarse time quantization on each received signal.

The switching means selects an arbitrary input terminal of the second delay means for the plurality of first delay means outputs.

The second delay means is a delay means having a plurality of input terminals whose time quantization unit is smaller than the time quantization unit of the first delay means, and each receiving signal 4 is phased in the second delay means. will be added.

Therefore, in the circuit of the present invention, since it is only necessary to perform minute delay control in the second delay means, the number of control signals is small, the circuit scale is small, and the noise generated by the control clock can be minimized. Can be done.

[Example] Hereinafter, two embodiments of the present invention will be described with reference to FIG.

1.2. ~n is the output terminal of the amplifier rlr from the receiving element, S
C-1, SC-2, ~SC-n are first delay means by sampling, VI-1, VI-2 ~ VI-n are voltage/current converters, and MPX is a switching means with n input and N output. ,
DT is the delay means of the minute delay means 2 having N input terminals, C
ONT is a control means for controlling the sampling delay means and switching means, ROM is a storage means for storing delay data, and 2-1- is a phasing and addition output terminal.

Amplifier outputs 1, 2 . from each receiving element. ~11 are the first delay means 5C-1 and 5C-2 by sampling, respectively.
, ~5C-n. - In the first delay means,
Control signals φ1, φ2 . from the control means C0NT. ~φn, the time quantization unit of delay is the sampling period T, and each control signal has a corresponding delay amount kXT (k=o,
1, 2. =--, j-1, j corresponds to the number of sampling delay elements).

Each output of the first delay means is connected to a voltage/current converter VI-
1, VI-2, to VI-n, and inputted into the switching means MPX with n inputs and N outputs.

Each input signal of the switching means is connected to the output terminals Q1, . Q2. - selectively connected to QN. The output of the switching means is inputted to each tap of the second delay means DL which performs a short delay, and the currents are added together and outputted to the output terminal Z-1 as a phased output.

As the second delay means, for example, a tapped analog LC delay line can be used. The maximum delay amount of the second delay means is within the delay quantization unit T of the first delay means,
The tap interval of the second delay means, that is, the delay quantization unit is the design required value Δ of the ultrasonic beam.

If the total delay amount for the first element's reception signal 4 is D, then D = k + XT + Q + XΔ. Here, k+=o, 1, 2. ...+j+Q,=Q.

1゜ 2゜ L.

LXΔ<T.

The storage means ROM stores ki, 12t as delay data of each receiving number 4 corresponding to each focus of the ultrasonic beam. The control means C0NT reads delay data corresponding to each focus of the ultrasound beam from the storage means, and
and control signals φ1, φ2 . for delaying data corresponding to the delayed data by the second delay means. ~φn and φX are generated.

First delay means 5C-1゜5C- by the above sampling
Various circuits as shown in FIG. 3 can be read as 2, to 5C-n.

(a) is a circuit in which sample and hold circuits (hereinafter abbreviated as SH circuits) are connected in series.

(b) is a switched capacitor circuit that performs writing and reading in series and parallel using multiple capacitor memories (
(hereinafter abbreviated as SC circuit).

(c) is a circuit that selects and outputs the type output of the tapped CCD using a switch MPX.

(d) is a circuit that delays a signal digitized by an A/D converter (A/D) using a line memory or shift register, and then converts it into an analog signal using a D/A converter (D/A). It is.

Furthermore, a combination of the circuits (a) to (d) above can also be used.

The detailed operations of the sH circuit in FIG. 3(a) and the 80 circuit in FIG. 3(b) are as described in Japanese Patent Laid-Open No. 103803/1983.

FIG. 5(a) shows an example of a control clock in the SH circuit of FIG. 3(a).

WlHWz, W3 are switches w,, w2. This is a sampling clock for w, and the period is T.

The amount of delay per stage of each SH circuit corresponds to the phase difference of each sampling clock, that is, the unit of delay quantization.

The maximum T. Here, the example shown in FIG. 5(a) is a case where the amount of delay per one time is T/2.

The variable delay can be realized by turning on any switch, and the delay amount kXT/2 (k=0.1, 2.
..., m-1).

FIG. 5(b) shows an example of the control clock in the SC circuit of FIG. 3(b). φS is a clock indicating the sampling period, xl, x2 are capacitors M
1. Write switch to M2 X□.

The sampling clock for X2, yl, y2 is the readout switch Y1. This is the clock for Y2. When the sampling period is T, the phase difference τ between the write clock Xl and the write clock yI for one capacitor is the amount of delay. The delay quantization unit is the sampling period T, and the variable delay can be realized by making the phase difference between X and yl variable in T units.

In the case of FIG. 5(b), the write clock X is fixed,
Although the read clock yi is variably controlled as shown by the broken line,
A similar variable delay can be realized even if X is made variable and yi is fixed. Therefore, the amount of delay is k X T (k = 0
, 1 , 2 , -- m −1).

Here, FIG. 5(b) is an example in which the number m of capacitors is four.

In addition, as the first delay means, the tapped CC shown in FIG. 3(c) is used.
D, A/D, line memory and D/A in Figure 3 (cl)
It is clear that even when using , the required control clock is a taro clock with a sampling period T and a phase difference of T.

Further, as the second delay means DL for performing a minute delay in FIG. 1, an adder Al as shown in FIG. 4 is used.

A2. It is also possible to use a circuit in which A3 . . . and an SH circuit are connected in series.

Switch W1. W2. W, ... control clock C
Engineering.

C, , C3, . . . , the phase difference changes by a small Δ of the delay quantization unit, similar to the control clog shown in the conventional example in FIG. However, since the control clock in this case is used only in the second delay means, only one wiring for the second delay means is required for n number of receiving signals, and the problems of increase in circuit scale and gross daughter are reduced. become.

FIG. 2 shows an example in which the present invention is implemented in a receiving phasing circuit with a large amount of delay, such as in an electronic sector. 1-1 to M-n are amplifier output terminals from the receiving element, X]- to X-M are basic structural blocks of the present invention shown in FIG.
and S(>(M+1)-5(>K is Fig. 3(a), (
b), (c).

A circuit having the same configuration as the first delay tilting by sampling shown in (d), A-] ~ A-M, A- is an adder, C0
NT-ROM is a control means and a storage means. Z is a phasing addition output terminal.

In the block XX-1-X-, tt is performed for each n of the M x n received signals, and the large delay for each block is transferred to the next delay means 5C-1,
~ Performed with SC-M. Further, the outputs of SC-] to SCM are added two or more times, and the outputs of SC-] to SCM are added to the next delay means SC(M
+1) to 5C-K, the signals are phased and added in adders A-Z which provide a larger delay.

Further, FIG. 7 shows the configuration of an ultrasonic diagnostic apparatus using the receiving phasing circuit according to the present invention.

10 is an array element for transmitting and receiving ultrasonic waves, ]-1 is a wave transmitting means, 1-2 is a receiving amplifier, 1 and 3 are a receiving phasing circuit of the present invention, and 14 is a video signal processing circuit; ], 5 is the image memory (D
SC), 16 is a display, 1 and 7 are wave transmitting means 11.
The phasing circuit 139 is a control means that also controls the image memory 15.

It is clear that the present invention is applicable not only to an ultrasonic diagnostic apparatus but also to an ultrasonic flaw detection apparatus having a configuration similar to that shown in FIG. 7 or an ultrasonic radar system.

[Effects of the Invention] According to the present invention, the clock phase difference of the control signals is sufficiently large and the total number of control signals can be reduced compared to the conventional case where a minute delay is performed first, so the circuit size is small. It is possible to provide a receiving phasing circuit with less cross-steering noise.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
3 is a circuit block diagram showing a sampling delay means, FIG. 4 is a circuit block diagram showing another embodiment of the second delay means, FIG. 5 is an explanatory diagram that does not show the control signal of the sampling delay means, FIG. 6 is an explanatory diagram showing the small delay control signal of the conventional sampling delay means, and FIG. 7 is an ultrasound diagnostic apparatus according to an embodiment of the present invention. FIG. ]~n・Receiver No. 4 adder 111 output terminal, S C-1~
L) First delay means by Cn sampling, VI-
1~Vl-n... Voltage/current exchanger, M P X... Switching means, ■〕■,... Second delay means for small delay, CON'
F. Control means, ROM... Storage means. 1st 2nd figure υl 3rd eye α3 ν3 ↑ ↑ ↑ ↑ ↑ ↑ Rith ward ψβ ←T→ ↑ ↑ ↑ ↑ Moment t ↑ Ten− ↑ ↑ ↑ ↑ ↑

Claims (1)

[Claims] 1. An ultrasonic receiving phasing circuit that has a plurality of elements that transmit and receive ultrasonic waves and generates a phasing signal for obtaining an image based on each received signal from the elements. a plurality of first delay means by sampling that performs a relatively large delay; a plurality of second delay means having a delay quantization unit smaller than a delay quantization unit of the first delay means; a switching means for selectively inputting the outputs of the plurality of first delay means to arbitrary input taps of the second delay means; a control means for controlling the delay amount and the switch of the plurality of first delay means; and a control means for storing delay data. What is claimed is: 1. An ultrasonic diagnostic apparatus comprising: an ultrasonic receiving phasing circuit consisting of a storage means for storing the information; 2. A sample and hold circuit as the first delay means;
Switched capacitor circuit, CCD (Charge coupled device)
2. The ultrasonic diagnostic apparatus according to claim 1, which uses one of a circuit, an analog/digital converter, a line memory, and a digital/analog converter. 3. The ultrasonic diagnostic apparatus according to claim 1, wherein a tapped analog delay line using current addition is used as the second delay means. 4. The ultrasonic diagnostic apparatus according to claim 1, wherein an adder and a sample hold circuit are alternately connected in series as the second delay means. 5. An ultrasonic wave receiving phasing circuit according to claim 1, and a circuit having a large delay by connecting a plurality of the first delay means in a tournament manner. Sonic diagnostic equipment.