JPS59195170A - Beam forming circuit - Google Patents

Abstract

PURPOSE:To obtain a satisfiable beam forming characteristic by deviating the timing in sampling the output signal of each wave receiving sensor by as much as the time corresponding to a time delay, in a basic sampling period. CONSTITUTION:The output from each wave receiving sensor is supplied to a sample holding circuit 1, by which the output is sampled at a timing d'i. The sampled output is multiplexed by a multiplexer circuit 2 and is fed by a delay quantity equivalent to niT in a register circuit 4 after A/D conversion 3, then a beam output is synthesized by an adder 5. The timing d'i indicates the time delay quantity of each wave receiving sensor within the basic sampling period. A timing circuit 6 generates a pulse d'i and the timing of each part associated thereto and the one period of the memory access thereof coincides with the basic sampling period. The memory step thereof is determined by the quantization accuracy of the time delay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a beamforming circuit for synthesizing received beams from receiving sensor play, such as in a sonar device.

This type of beam forming circuit has a receiver f-7
There is a digital time-domain beamforming circuit that sequentially samples the received signal from the ray on the time axis, sequentially stores it in memory, and extracts and synthesizes data from the memory corresponding to the required time delay. In this method, the quantization of time delay is determined by the sampling period of the received signal.

In general, the input signal sampling period for digital signal processing is approximately the Nyquist sampling rate, but in the case of time-domain beamforming, errors due to time delay quantization can cause a drop in the level of the main-axis response or side effects. Since this causes lobe disturbance, it is necessary to set the sampling rate much higher than the Nyquist sampling rate mentioned above. Conventionally, in order to prevent this time delay quantization error, a large capacity memory was installed to increase the sampling period, or the sampling period was kept to about the Nyquist rate, and an interpolation process was used to apparently increase the sampling period. Measures were taken to obtain the same effect as the previous one.

In the present invention, the sampling period of the receiving sensor signal is about the Nyquist rate, and the quantization of the time delay during beamforming is a digital method that can obtain sufficient accuracy even if special processing such as interpolation is performed. It provides a beamforming circuit.

The beamforming circuit of the present invention further divides the basic sampling period of the delivery sensor signal into smaller time segments,
By shifting the sample timing of each receiving sensor output signal used for beamforming within one basic sampling period by an amount equivalent to the time delay, the time delay is equivalent to making the sampling period sufficiently high relative to the input signal frequency. It is characterized by obtaining precision.

Next, embodiments of the present invention will be described with reference to the drawings.

Considering beamforming in the ← direction with a group of receiving sensors arranged on a cylinder as shown in Figure 1, the acoustic signal reaching each receiving sensor is d with respect to sensor 4.
Since a time delay of L d2, d:3 occurs, the beamforming circuit electrically corrects the time delay of each received sensor signal, matches the phases, and synthesizes the signals. In order to obtain the desired time delay, the digital beamforming circuit extracts sample data corresponding to the time delay from among the data group that sequentially samples each received sensor signal on the time axis and A/D converts it. and synthesize. At this time, if each receiving sensor signal is sampled at the same time, the accuracy of the time delay will be determined by the sampling period.

Therefore, by adjusting the sampling time of each receiving sensor signal by the amount of time delay within one pull cycle, it is possible to prevent the accuracy of time delay from being affected by the sampling cycle. The quantization error of is negligible. This will be explained using the time chart shown in FIG. Based on the wave receiving sensor 4 in FIG. 1, the time delay amount of each delivery sensor is expressed as follows.

dl = n I T + d’1 d2=n2T+d'2 d3-H3T-+ (1'3 dn-nnT1d'.

Here, di (i = 1 to n); time delay amount T from the reference sensor; basic sampling period nl (i = 1 to n); positive integer d' of 0.1.2, ... 1 (i=l to n); Amount of time delay within the basic sampling period d'i in the above equation represents the amount of time delay of each wave receiving sensor within the basic sampling period.

Therefore, the timing of d'i is created by dividing one sampling period to such an extent that the quantization error of time delay can be ignored, and each receiving sensor signal is sampled at this timing. Furthermore, in order to obtain the true time delay di, each receiving sensor signal is
Give a time delay corresponding to iT. This can be realized with nl stages of registers. Generally, ni is on the order of several stages.

In the time chart of FIG. 2, (a) represents a basic sample signal, which is used for sampling the signals of the desk and four wave receiving sensors of FIG. Similarly, (b) is No, 3 and No, 5
(C) is used to sample the No, 2, and No. 6 reception sensor signals; (d) is the No., 'l, and No. 7 reception sensor signal. used for sampling.

FIG. 3 is a block diagram of an embodiment of the present invention. In the figure, the output of the receiving sensor is sample-and-hold circuit 1.
Each received sensor signal is sampled at dti timing, multiplexed by a multiplexer circuit 2, and converted into a digital signal by an A/D converter 3. Each converted sensor signal is given a delay amount corresponding to the above-mentioned niT in a register circuit 4, and a beam output is combined in an adder 5. The timing circuit 6 is a timing generating circuit for the sampling pulse d'i and various parts related thereto, and is composed of a memory.

One period of memory access coincides with the basic sampling period, and its memory steps are determined by the quantization precision of the time delay.

As described above, in the present invention, the quantization accuracy of the time delay for beamforming does not depend on the sampling period, so even if the sampling period is reduced to near the Nyquist sampling rate, sufficient beamforming characteristics can be obtained. For example, if an N-word memory is used in the timing circuit, and the access time for one round of this memory is taken as the sampling period T, this is equivalent to increasing the time delay quantization accuracy of beamforming by N times. A normal beamforming circuit requires a sampling rate several tens of times higher than the input signal, but in this case, the memory described above can be realized with a very small amount of about several tens of words. Furthermore, if the memory is configured with a RAM, by changing the contents of the memory from the outside, it is possible to dynamically realize, for example, sound velocity correction for beamforming, and optimal beamforming control can be performed.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining the present invention in detail, and FIG. 3 is a block diagram of a beamforming circuit showing one embodiment of the present invention. 1...Sample and hold circuit, 2...
...multiplexer circuit, 3...A/D converter, 4...register circuit, 5...addition circuit, 6...timing circuit. Agent: Susumu Uchihara, patent attorney.゛、-7-ノ

Claims (1)

[Claims] In a beamforming circuit that synthesizes a reception beam by giving a predetermined time delay to each of the signals from n reception sensor arrays (n is a positive integer), the signal from the reception sensor array is sampled. A sample-and-hold circuit, a multiplexer circuit that multiplexes this sampled signal, and an A/D that converts the output analog signal from this multiplexer circuit into a digital signal.
A converter, a register circuit for holding A/D converted data for a certain period of time, an addition circuit for adding n pieces of A/D converted data, and a sample timing of the n pieces of reception sensor signals. What is claimed is: 1. A beamforming circuit comprising: a beamforming circuit for adjusting a beamforming circuit, and thereby obtaining sufficient time delay accuracy for an input signal frequency regardless of a sampling frequency.