JPH1033534A - Ultrasonic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ultrasonic device with which received focus data to be used for forming digitized received beams are reduced. SOLUTION: This ultrasonic device has an ultrasonic vibrator 1, converting means for converting an ultrasonic signal to a digital signal, received data storage means for storing outputs, signal adding means 5 for adding the received data, output control means for outputting signals in the prescribed order, and display means 7 for displaying the ultrasonic image of output signals. In this case, this device is provided with an initial address storage means for storing the address value of received signal data to be first read out among received signal data, differential value storage means for storing the differential value of address values for each focus step and address adding means for adding the address value to be first read out or the address value on the preceding stage with the differential value and based on the address value stored in the initial address storage means and the differential value, the received signal data are read out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic apparatus, and more particularly, to an apparatus for non-destructively inspecting an object using ultrasonic waves or a digital signal processing apparatus such as an ultrasonic diagnostic apparatus used for medical diagnosis. And effective technology.

[0002]

2. Description of the Related Art As shown in FIG. 11, a conventional ultrasonic apparatus has an ultrasonic probe 1 in which a plurality of rectangular ultrasonic transducers for transmitting and receiving ultrasonic waves to a subject are arranged. An analog transmission / reception switching circuit 2 for switching between transmission and reception of ultrasonic waves, a transmission circuit 3 for driving each ultrasonic transducer, and a reception signal received by each ultrasonic transducer. The m received signal processing means 4 for correcting the arrival time to the focus point (received wave focus point) between the ultrasonic transducers, and the outputs of the respective received wave processing means are added and combined into one signal. Addition means 5 and signal processing means 6 for performing signal processing such as filtering, compression, edge enhancement, time variable amplification, scan conversion, etc.
And display means 7 for displaying the processed signal as image information
And was composed of

The above-mentioned m received signal processing means 4
Had one ultrasonic transducer connected to each.

The ultrasonic vibrator driven by the wave transmitting circuit 3
The position of the transmission focus point and the transmission direction (beam direction) determined by the delay time set for each ultrasonic transducer
Then, an ultrasonic wave is transmitted.

On the other hand, the ultrasonic waves reflected in the living body of the subject are received by each of the ultrasonic transducers provided in the ultrasonic probe 1, and then each of the ultrasonic waves is transmitted by the analog transmission / reception switching circuit 2. It is guided to the received signal processing means 4 connected to the vibrator.

The received signal processing means 4 corresponding to each ultrasonic transducer has a delay means having a predetermined amount of delay time. When the received signal is processed as an analog signal, an analog delay is used. By selecting the tap of the line, a delay from the reference ultrasonic transducer is performed. The delay data at this time was tap selection data.

On the other hand, when digitally processing a received signal, the received signal is first sampled by an A / D converter (A / D conversion), and then the digital signal is written to a memory and read from the memory. However, the delay is performed by changing the address between the received signal processing means.

Incidentally, the delay data at this time was a read address of the memory.

Next, the delayed received signals are adjusted in phase and then added by the adding means 5 to form a received ultrasonic beam.

Thereafter, the received signal subjected to the phasing addition is subjected to signal processing such as filtering, compression, edge enhancement, time variable amplification, and scan conversion by the signal processing means 6 described above.

By performing the above operation while sequentially shifting the direction of the ultrasonic beam, a tomographic image is displayed on the display means 7.

However, the above-described units are controlled by the overall control unit 29.

In the conventional ultrasonic apparatus for performing digital processing, attempts have been made to eliminate problems that cannot be avoided in analog circuits, such as variations in constants of circuit components, temperature drifts in constants of circuit components, and saturation of active circuit components. I have.

However, when the signal processing is simply digitized, a high-speed ADC of 100 MHz or more is required to realize the phasing accuracy (delay accuracy) of 10 ns or more, similarly to the ultrasonic device using the conventional analog circuit. (Analog-digital converter, A / D converter) is required.

Therefore, there is known a method of digitizing with a low-speed ADC and achieving high-precision phasing by signal processing (interpolation processing).

In this method, basically, sampled data is stored in a memory, and a received signal is delayed in a sampling unit according to a read or write address.

However, if the precision of the delay cannot be obtained in this sampling cycle, the received signal is slightly delayed by various interpolation processes. Alternatively, there is known a wavefront synchronization (concave) sampling technique in which a sampling clock is multi-layered, a minute delay is performed based on a time difference between the multi-layer clocks, and a received signal is stored in a memory and delayed in a sampling unit.

In the case of using the above-mentioned method, conventionally, the read address of the memory is directly provided from the outside according to the focus switching of the received signal.

FIG. 12 is a block diagram showing a schematic structure of a wave receiving means of a conventional ultrasonic apparatus, and a method of specifying a memory read address will be described. Note that the wave reception processing means shown in FIG. 12 is configured to perform a minute delay by interpolation.

In the reception processing means shown in FIG. 12, the reception signal is quantized (sampled) by the ADC 9 and written into the delay memory 10. At this time, the delay memory 1
The address written to 0 is the memory address setting unit 1
3 was set. Similarly, the read address has also been separately set by the memory address setting unit 13.

For example, when a delay is given to a received signal at the time of reading, first, a read address for giving a delay is
The address is read from the received wave focus data memory 32 and the address of the delay memory 10 is set.

Next, the read address of the delay memory 10 is sequentially counted up from this address, and the received data is sequentially read from the delay memory 10. When the reception focus is switched, the read address of the delay memory 10 is similarly read from the reception focus data memory 32 again.

On the other hand, the interpolation means 11 stores the interpolation coefficient memory 1
6 based on the various coefficients read from the delay memory 1
By performing interpolation processing on the received data read from 0, highly accurate phasing is obtained from received data digitized by a low-speed ADC.

Next, the procedure for reading the interpolation coefficients from the interpolation coefficient memory 16 will be described with reference to FIG.
From the reception focus data memory 32 to the interpolation coefficient memory 1
6 are read out.

Next, based on this address, an interpolation coefficient is read out from the interpolation coefficient memory 16, and this interpolation coefficient is output to the interpolation means 11. The interpolation means 11 performs an interpolation operation based on the input interpolation coefficient to output a received signal with a minute delay corrected.

At this time, for example, the sample clock of the ADC is high-speed, or A /
When the delay quantization unit in the delay memory 10 satisfies the desired precision of the minute delay, such as when the difference between DC sample clocks is small, the interpolation means 11 and its control system become unnecessary. .

[0027]

SUMMARY OF THE INVENTION As a result of studying the above prior art, the present inventor has found the following problems.

In the conventional ultrasonic apparatus, the sample clock of the ADC is slow, so that when an ultrasonic image is generated from the measured value, that is, the measurement data stored in the delay memory 10, the measurement read out from the delay memory 10 is performed. Interpolation means 11 for interpolating data and means for giving the interpolation coefficient necessary for interpolation to the interpolation means 11 are required.

On the other hand, in the conventional ultrasonic apparatus, as shown in FIG. 12, the addresses of the delay memory 10 and the interpolation coefficient memory 16 are all stored in the reception focus data memory 32 as reception focus data. When the capacity of the delay memory 10 is 8 k words, 13 bits
Address data is required.

Therefore, the reception focus data for delaying the reception signal is required as many times as the product of the number of focus stages and the number of rasters, so that the capacity of the reception focus data memory 32 becomes large. there were.

Further, since the capacity of the reception wave focus data memory 32 becomes large, there is a problem that an area occupied by a circuit constituting the wave reception processing means becomes large.

A first object of the present invention is to provide an ultrasonic apparatus in which reception focus data used for forming a digitized reception beam is reduced.

A second object of the present invention is to provide an ultrasonic apparatus having a small area of a circuit constituting a received signal processing means.

A third object of the present invention is to provide an ultrasonic apparatus which corrects a time variation peculiar to each ultrasonic diagnostic apparatus in each processing means.

A fourth object of the present invention is to provide an ultrasonic apparatus capable of correcting a delay error caused by a difference in sound velocity distribution in each part in a subject.

A fifth object of the present invention is to provide an ultrasonic apparatus having a small storage capacity of the delay memory.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0038]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, a plurality of conversion means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, respectively, A plurality of received data storage means for storing an output of the means;
A signal adding means for reading and receiving the received data stored in the received data storage means, an output control means for outputting the added signals in a predetermined order, and displaying an ultrasonic image based on the output signals An initial address storage means for storing an address value of received signal data to be read first among received signal data stored in the received data storage means, A difference value storage means for storing a difference value of an address value for each focus stage, and an address addition means for adding the difference value to the first read address value or the previous stage address value; At the time of reading the signal data, the address value stored in the initial address storage unit or the address value of the stage before the focus and the difference value stored in the difference value storage unit are stored. Zui and sequentially reads delay treating received signal data corresponding to the focus stage.

(2) A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, conversion means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, and outputs of the conversion means Storage means for storing the received signal, an interpolation processing means for reading out and delaying the received signal stored in the storage means, and interpolating the delayed received signal, and a plurality of received signals after the interpolation processing. An ultrasonic apparatus comprising: signal addition means for adding, output control means for outputting the added signal in a predetermined order, and display means for displaying an ultrasonic image based on the output signal, wherein an interpolation coefficient is Interpolation coefficient storage means for storing, initial interpolation coefficient address storage means for storing an interpolation coefficient address value to be read first among the interpolation coefficients stored in the interpolation coefficient storage means, and an interpolation coefficient address value for each focus stage Store the difference value of Interpolation coefficient difference value storage means, and an interpolation coefficient address addition means for adding the difference value to the address value of the interpolation coefficient to be read first or the address value of the interpolation coefficient of the preceding stage. An interpolation coefficient corresponding to the focus stage is read based on an interpolation coefficient address value or a previous stage address value stored in the initial interpolation coefficient address storage unit and a difference value stored in the interpolation coefficient difference value storage unit. ,
The received signal read from the storage means is subjected to interpolation processing.

(3) A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, conversion means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, and outputs of the conversion means Storage means for storing the received signals, interpolation processing means for performing interpolation processing of the received signals stored in the storage means in the reading order, signal addition means for adding a plurality of received signals after the interpolation processing, What is claimed is: 1. An ultrasonic apparatus comprising: output control means for outputting signals in a predetermined order; and display means for displaying an ultrasonic image based on said output signals, wherein said reception signal is stored in said reception data storage means. Initial address storage means for storing the address value of the received signal data to be read first among the data, difference value storage means for storing the difference value of the address value for each focus stage, and the address value to be read first Or before Address adding means for adding the address value and the difference value, an interpolation coefficient storing means for storing interpolation coefficients, and an interpolation coefficient address value to be read first among the interpolation coefficients stored in the interpolation coefficient storage means. Initial interpolation coefficient address storage means for storing, interpolation coefficient difference value storage means for storing the difference value of the interpolation coefficient address value for each focus stage, and the address value of the interpolation coefficient to be read first or the address of the interpolation coefficient of the preceding stage Interpolating coefficient address adding means for adding the difference value and the difference value, wherein at the time of receiving the received signal data, the address value stored in the initial address storage means or the address value of the pre-focus stage and the difference value storage The received signal data corresponding to the focus stage is sequentially read out based on the difference value stored in the means. An interpolation coefficient corresponding to the focus stage is read out based on an interpolation coefficient address value or a preceding stage address value stored in an interpolation coefficient address storage unit and a difference value stored in the interpolation coefficient difference value storage unit, The received signal read from the storage means is subjected to interpolation processing.

(4) In the ultrasonic apparatus according to any one of the above (1) to (3), each of the ultrasonic signals in the reception signals obtained by delaying the reception signals received by the plurality of ultrasonic transducers and adjusting the phases thereof are adjusted. Phase shift detecting means for detecting a phase shift of the reception signal between the acoustic transducers, and a correction address calculating means for calculating an address value corresponding to a phase shift correction value based on an output value of the phase shift detecting means; A phase shift address value storing means for storing the correction address value, and a means for correcting a difference value inputted to the address adding means and the interpolation coefficient address adding means based on the phase shift address value.

(5) In the ultrasonic device according to any one of the above (1) to (4), ultrasonic measurement characteristics based on individual differences for each device are measured in advance and calculated based on the measured values. A variation value address storage unit that stores an address value corresponding to a correction value; and a unit that corrects the initial address value and the initial interpolation coefficient address value based on the address value of the variation value address storage unit.

(6) In the ultrasonic apparatus according to any one of the above (1) to (5), the reception data storage means converts the ultrasonic signal converted into a digital signal by the conversion means into a predetermined capacity. When the converted ultrasonic signal exceeds the capacity of the reception data storage means, the ultrasonic signal corresponding to the capacity exceeding the capacity from the head of the reception data storage means is stored. Means.

(7) In the ultrasonic apparatus according to the above (6), the address value output from the address addition means is compared with the capacity of the received data storage means, and the address output from the address addition means is compared. When the value becomes an address value exceeding the capacity of the received data storage means, an address value corresponding to the capacity of the received data storage means is subtracted from the exceeded address value, and the focus value is determined based on the address value. A read address setting means for sequentially reading the received signal data corresponding to the stage is provided.

According to the above-mentioned means (1), the address value of the first received signal data stored in the initial address storage means, that is, the received signal data stored in the received data storage means The output value of the address adding means for adding the address value of the received signal data to be read first and the difference value of the address value for each focus stage stored in the difference storage means is stored in the received data storage means. First, the received signal data corresponding to the first focus stage is read from the received data storage means, and thereafter, the received focus signal of the immediately preceding focus stage output by the address adding means is read out. Since the sum of the read address and the difference value is used as the address value for reading the received signal data from the received data storage means, each focus stage is read. Since 100 requires no means for storing all because of address values, digitized reception bi - in the reception focus data used for forming the beam,
The capacity of the means for storing the read address value can be reduced.

Therefore, the circuit constituting the reception signal processing means comprising the conversion means, the reception data storage means, and the means for specifying the address value for reading the reception data from the reception data storage means. Area can be reduced.

According to the above-mentioned means (2), the address value of the interpolation coefficient which is stored in the initial interpolation coefficient address storage means and which is to be read first, and which is stored in the interpolation coefficient difference value storage means. By using the output value of the interpolation coefficient address adding means for adding the interpolation coefficient address value of each focus stage as the read address to be input to the interpolation coefficient storage unit, first, the interpolation coefficient storage unit corresponds to the first focus stage. After that, the addition value of the readout address of the focus stage immediately before and the difference value output by the interpolation coefficient address addition means and the address value when the interpolation coefficient is read from the interpolation coefficient storage means are read out. Therefore, means for storing all the interpolation coefficient address values for reading out each focus stage is not required, so that a low-speed A / A Even in the case of using a transducer,
The capacity of the means for storing the read address value of the interpolation coefficient out of the reception focus data used to form the digitized reception beam can be reduced.

Therefore, a reception signal processing means comprising a conversion means, an interpolation means, an interpolation coefficient storage means, and a means for designating an address value for reading out an interpolation coefficient from the interpolation coefficient storage means is constituted. The area of the circuit can be reduced.

According to the above-mentioned means (3), the address value of the first received signal data stored in the initial address storage means, that is, the received signal data stored in the received data storage means The output value of the address adding means for adding the address value of the received signal data to be read first and the difference value of the address value for each focus stage stored in the difference storage means is stored in the received data storage means. First, the received signal data corresponding to the first focus stage is read from the received data storage means, and thereafter, the received focus signal of the immediately preceding focus stage output by the address adding means is read out. Since the sum of the read address and the difference value is used as the address value for reading the received signal data from the received data storage means, each focus stage is read. Since 100 requires no means for storing all because of address values, digitized reception bi - in the reception focus data used for forming the beam,
The capacity of the means for storing the read address value can be reduced.

The interpolation coefficient address value stored in the initial interpolation coefficient address storage means and read out first, and the interpolation coefficient address value for each focus stage stored in the interpolation coefficient difference value storage means are stored. Is used as a read address input to the interpolation coefficient storage means, first, the interpolation coefficient corresponding to the first focus stage is read from the interpolation coefficient storage means, and thereafter, Since the addition value of the readout address of the previous focus stage output by the interpolation coefficient address addition means and the difference value is used as the address value when the interpolation coefficient is read from the interpolation coefficient storage means, the respective focus stages are read. Therefore, means for storing all the interpolation coefficient address values is not necessary, so that a low-speed A / D converter is used. Even, digitized reception bi -
The capacity of the means for storing the read address value of the interpolation coefficient out of the received focus data used for forming the system can be reduced.

Therefore, the conversion means, the reception data storage means, the means for specifying the address value for reading the reception data from the reception data storage means, the interpolation means, the interpolation coefficient storage means, It is possible to reduce the area of a circuit constituting the received signal processing means including means for designating an address value for reading an interpolation coefficient from the coefficient storage means.

According to the above-mentioned means (4), in addition to the above-mentioned effects, the correction address calculating means calculates on the basis of the output value of the phase shift detecting means for detecting the phase shift between the ultrasonic transducers. A means for correcting a difference value input to the address adding means and the interpolation coefficient address adding means based on the phase shift address value stored in the phase shift address value storage means for storing an address value corresponding to the phase shift correction value. Since the difference values input to the address adding means and the interpolation coefficient address adding means are respectively corrected, it is possible to correct a delay error caused by a difference in sound velocity distribution in each part in the subject.

According to the above-mentioned means (5), for example, the address value for correcting the ultrasonic measurement characteristic based on the individual difference of each apparatus measured beforehand such as before shipment of the apparatus is stored in the variation value address storage means. A means for correcting the initial address value and the initial interpolation coefficient address value when the apparatus is used, corrects the initial address value and the initial interpolation coefficient address value based on the address value of the variation value address storage means. Therefore, it is possible to correct a time variation peculiar to each ultrasonic diagnostic apparatus in each processing unit.

At this time, the above-mentioned effect is also obtained.

According to the above-mentioned means (6) and (7), the reception data storage means stores the ultrasonic signals converted into digital signals by the conversion means in order within a predetermined capacity, and performs the conversion. When the subsequent ultrasonic signal exceeds the capacity of the received data storage means, the ultrasonic signal is a means for storing the ultrasonic signal exceeding the capacity from the head of the received data storage means, and at this time, read address setting means Compares the address value output by the address addition means with the capacity of the received data storage means, and when the address value output by the address addition means becomes an address value exceeding the capacity of the received data storage means,
The received signal data corresponding to the focus stage is sequentially read out based on the address value by subtracting the address value corresponding to the capacity of the received data storage means from the exceeded address value. The storage capacity can be reduced.

At this time, the above-mentioned effect is also obtained.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0059]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments (examples) of the invention.

In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of an ultrasonic apparatus according to Embodiment 1 of the present invention.
1 is an ultrasonic probe, 2 is an analog transmission / reception switching circuit, 3
Is a transmission circuit, 4 is a reception signal processing means, 5 is an addition means (signal addition means), 6 is a signal processing means (output control means), 7
Indicates a display means, and 29 indicates an overall control means.

In FIG. 1, an ultrasonic probe 1 is a well-known ultrasonic probe, and is composed of a plurality of rectangular ultrasonic transducers. The ultrasonic transducer generates an ultrasonic wave corresponding to a drive signal supplied from the wave transmitting circuit 3 via the analog transmission / reception switching circuit 2 and transmits the ultrasonic wave to a subject (not shown). Also, the ultrasonic wave reflected inside the subject, that is, inside the living body, is converted into an electric signal.

The analog transmission / reception switching circuit 2 is a well-known switching circuit, and the control output (instruction) of the overall control means 29
And a system for transmitting a drive signal output from the transmission circuit 3 to each ultrasonic transducer of the ultrasonic probe, and processing an analog received signal output from the ultrasonic transducer based on the received signal processing. Switch the system to transmit to the means.

Based on the control output of the overall control means 29, the transmitting circuit 3 calculates each ultrasonic wave of the ultrasonic probe 1 with a delay time difference for correcting the arrival time difference between the transducers up to the transmitting focus point. This is a known wave transmission circuit that generates and outputs a drive signal for driving a vibrator.

The received signal processing means 4 is connected to each ultrasonic transducer one by one, and converts an analog received signal received by each ultrasonic transducer into a digital received signal (hereinafter, referred to as a digital received signal).
Received signal is abbreviated), that is, after conversion into digital data, the arrival time of the received signal received by each ultrasonic transducer to the reception focus point between each element (between the ultrasonic transducers) is corrected. This is a means for performing a delay process for performing the conversion, and then performing an interpolation process for a missing signal accompanying the conversion by the low-speed ADC, which will be described in detail later.

The addition means 5 is means for adding, based on the control output of the overall control means 29, the reception signals after the interpolation processing output from the m reception signal processing means 4, and the present embodiment. The first embodiment is realized by a program executed on an information processing device (not shown).

The adding means 5 performs the phasing addition of the interpolated and phase-aligned received signals output from the received signal processing means 4, and then converts the interpolated received signal from the received ultrasonic beam. Create

The signal processing means 6 performs image correction processing such as filtering, compression, edge enhancement, time variable amplification, and scan conversion, and then outputs a video signal for outputting the received signal after the correction processing to the display means. It is a means to convert to. In the first embodiment, the signal processing means 6
The above-described image correction processing is realized by a program executed on an information processing device (not shown), and the processing of converting the received signal after the image correction processing into a video signal is realized by a well-known conversion unit.

The display means 7 is a well-known display means, for example, a so-called color CRT display device using a CRT (Cathode Ray Tube).

The overall control means 29 controls the operation of the analog transmission / reception switching circuit 2, the transmission circuit 3, the reception signal processing means 4, the addition means 5, the signal processing means 6 and the display means 7. In the first embodiment, for example, in a program executed on the information processing device, a means for controlling the analog transmission / reception switching circuit 2 and the wave transmission circuit 3, which are external devices connected to the information processing device, is used. is there.

Next, the operation of the ultrasonic apparatus according to the first embodiment will be described with reference to FIG. 1. First, the wave transmitting circuit 3 transmits each ultrasonic vibrator to the ultrasonic wave transmitting focus point. The ultrasonic transducers of the ultrasonic probe 1 are driven by the delay time difference for correcting the arrival time difference between the children, and the ultrasonic wave is transmitted to the subject (not shown). At this time, the transmission circuit 3 also controls the direction of the ultrasonic beam.

The reflected signal from the subject is transmitted to the ultrasonic probe 1
And is guided to the received signal processing means 4 via the analog transmission / reception switching circuit 2.

The received signal processing means 4 first converts the received analog signal, which is an analog signal, into a digital signal by an ADC (not shown). Next, a received signal converted into a digital signal (hereinafter, unless otherwise specified, a received signal converted into a digital signal is simply referred to as a received signal)
Is corrected by a delay in the arrival time difference of each ultrasonic transducer to the focus point, and a minute delay equal to or shorter than the sampling interval is performed by interpolation processing, and then output to the adding means 5.

The received signal input to the addition means 5 is subjected to so-called phasing addition by the addition means 5 and then subjected to image processing such as filtering, compression, edge emphasis, time variable amplification and scan conversion by the next signal processing means 6. The correction process is performed, and then the video signal is converted into a video signal and displayed on the display unit 7.

At this time, the tomographic image is displayed on the display means 7 by scanning the ultrasonic beam phase-added by the adding means 5 while sequentially shifting its direction, for example.

FIGS. 2 and 3 are block diagrams showing a schematic configuration of one channel of the received signal processing means according to the first embodiment of the present invention. In particular, FIG. FIG. 3 is a block diagram illustrating a schematic configuration of a received signal processing unit according to the first embodiment.

In FIGS. 2 and 3, reference numeral 9 denotes an analog
Digital converter (ADC, A / D converter, conversion means), 10 is a delay memory (received data storage means), 11
Denotes interpolation means, 12 denotes first initial value storage means (initial address storage means), 13 denotes memory address setting means (read address setting means), 14 denotes address addition means, 15
Is the first difference data providing means (difference value storage means), 16
Is an interpolation coefficient memory (interpolation coefficient storage means), 17 is an interpolation data address addition means (interpolation coefficient address addition means),
18 is a second difference data providing means (interpolation coefficient difference value storage means), 19 is a second initial value storage means (initial interpolation coefficient address storage means), 24 is a first selector, and 25 is a second selector.
And 28, a differential reception focus data means.

The ADC 9 in FIGS. 2 and 3 is a well-known A / D converter. In the first embodiment, a low-speed A / D converter is used.

The delay memory 10 is a well-known memory for storing a received signal converted into a digital signal. For example, a well-known semiconductor memory that is readable and writable is used.

The interpolation means 11 is a means for performing a minute delay with respect to the received signal read from the delay memory based on the interpolation coefficient read from the interpolation coefficient memory 16.
For example, it can be realized by a program executed by the information processing device.

The first initial value storage means 12 is a means for storing in advance the read start address of the delay memory 10 when the raster is switched and the reading of the received wave is started. An address value calculated based on a difference in arrival time (delay amount) from the reference element to one reception focus point is stored.

The memory address setting means 13 is a means for setting a read address of a received signal stored in the delay memory 10, and includes, for example, a well-known latch circuit and a well-known counter circuit.

The memory address setting means 13
Updates the output value in synchronization with a sampling clock described later.

The address adder 14 receives the data stored in the delay memory 10 based on the address value output from the first selector 24 and the difference data (address value) provided by the difference data provider 15. This is means for calculating the read address value of the wave signal, and is constituted by, for example, a well-known adder.

The first difference data providing unit 15 is configured to output the difference data output from the difference reception focus data means 28,
That is, this is a means for outputting a difference value from the previous data to the address adding means 14, and is realized by a known latch circuit in the first embodiment.

The interpolation coefficient memory 16 is a memory in which predetermined interpolation coefficients (interpolation data) are stored, and is realized by using, for example, a readable and writable semiconductor memory.

The interpolation data address adding means 17 is a means for setting a read address when reading interpolation data from the interpolation coefficient memory 16. In the first embodiment, the data output from the second selector 25 is , And the data output from the second difference data providing means 18 to obtain address data.

The second difference data providing means 18 sends the difference data of the interpolation coefficient output from the difference reception focus data means 28, that is, the difference value from the previous data to the interpolation data address adding means 17. This is a means for outputting, and in the first embodiment is realized by a well-known readable and writable latch circuit.

The second initial value storage means 19 is means for storing in advance the read start address of the interpolation coefficient memory 16 when the raster is switched and the reception of the received wave is started. The address value of the coefficient required for the interpolation operation to be realized is stored.

The difference reception focus data means 28 sends the difference data of the read address of the delay memory and the difference data of the read address of the interpolation memory to the first difference data giving means 15 and the second difference data giving means 18, respectively. Output means.

However, the difference data of the read address of the delay memory and the difference data of the read address of the interpolation memory are stored in a focus data memory (not shown), which will be described later, or are calculated by a calculation unit (not shown).

The first selector 24 is a well-known means for switching an address value input to the address adding means 14, and includes an initial value of a read address stored in the first initial value storage means 12, and a memory address setting means. 13 and the address value output from the address selector 13 and input to the address adder 14.

At this time, the first selector 24 selects the initial value of the read address stored in the first initial value storage means 12 when the raster is switched and the reading of the received wave is started, and thereafter. Memory address setting means 13
Select the address value output from.

The second selector 25 is a well-known means for switching the address value input to the interpolation data address adding means 17. The second selector 25 stores the initial value of the interpolation data address stored in the second initial value storage means 19 and the interpolation value. An address value output from the coefficient memory 16 is selected and input to the interpolation data address adding means 17.

At this time, the second selector 25 selects the initial value of the read address of the interpolation data stored in the second initial value storage means 19 when the raster is switched and the reception of the received wave is started. Thereafter, the address value output from the interpolation coefficient memory 16 is selected.

Next, FIG. 8 is a diagram for explaining the operation of the received signal processing means of the first embodiment. Hereinafter, based on FIG. 8, the received signal processing means of the first embodiment will be described. First, the received signal is quantized by the ADC 9 and written into the delay memory 10.

The write address at this time is set by the memory address setting section 13. The read address is also set by the memory address setting unit 13.

For example, as shown in FIG. 8, when a received signal between channels is delayed by a read address of the delay memory 10, when the focus of the received beam is switched, the reading of the next received focus stage to be switched is started. The address A111 is provided as an output of the address adding unit 14, and the delay memory 1 is synchronized with the switching pulse.
The data stored in the address A111 of 0 is read.

In the above-mentioned address A111, the subscripts indicate the channel number,
Indicates the raster number and focus stage number.

That is, the first selector 24 inputs the address value stored in the first initial value storage means to the address addition means 14, and the difference reception focus data means sends the address value to the first difference data provision means 15. Output difference data.

Next, the memory address setting means 13
The DC9 sampling clock or data read clock is counted, and the read address A111 is set to A11.
.. Are updated in the order of 1 + 1, A111 + 2,... And output to the delay memory 10 so that the received wave data is read out and sequentially input to the interpolation means 11.

When shifting to the next wave receiving focus stage, the read start address A1 of the delay memory 10 is similarly set.
12 is provided as an output of the address adder 14, and the delay memory 1 is synchronized with the reception focus switching pulse.
Reading is started from address A112 of 0.

During this time, it goes without saying that the timing is set so that the reception focus data is not lost due to the switching of the reception focus.

Conventionally, the start address associated with the switching of the reception focus is stored as address data in the reception focus data memory 32 as shown in FIG.

On the other hand, in the first embodiment, the read start address when the raster is switched and the reading of the received wave is started is stored in the initial value storage units 12 and 19 in advance.

That is, the difference between the read addresses with respect to the ultrasonic transducer as a reference for calculating the delay of the reception focus, for example, 256 is the initial value, and the second stage of the reception focus of the reception signal is the reference channel. On the other hand, when the address difference is, for example, 240 and the sampling period of the received signal is T (ns) (where ns indicates 10 to ⁹ seconds), the delay amount of the first received focus is 256 × T ( n
s) The second stage is 240 × T (ns).

Therefore, in the first embodiment, 256
Is stored in the first initial value storage means 12 as an initial value, and the difference value between the first-stage address 256 and the second-stage delay amount 240 at the time of the second-stage reception focus switching is referred to as a difference data providing unit. 15 to the address adding means 14.

Receiving focus 2 given to delay memory 10
The received wave focus data at the second stage, 16 which is the difference between 256 and 240, is provided from the first difference data providing means 15 to the address adding means 14. Further, the address of the delay memory 10 at the time of switching the reception focus is selected by the first selector 24, applied to the address addition, the address given to the delay memory is calculated, and given to the delay memory 10 by the memory address setting means 13. Can be

As a result, 8-bit address data was necessary to represent 240 as a delay memory address in a binary number, but 4-bit address data to represent a read address difference of 16 in a binary number. Therefore, the number of data can be reduced.

Next, the first channel when the received signal processing means 4 is the h channel, the number of rasters is M, and the number of received focus stages is n will be described.

First, the delay memory reading start address for the first received focus data of the first raster is input from the overall control means 29 in advance and stored in the first initial value storage means 12.

When the power is turned on, the ultrasonic probe is determined and transferred from a ROM (not shown) in the overall control means 29.

Note that the first initial value storage means 12 and the second initial value storage means 19 may store the initial values of each received focus data of all rasters.

Further, the information may be provided by an arithmetic unit (CPU, DSP) of the information processing apparatus (not shown) from the data such as the frequency, the transducer pitch, and the scanning type related to the ultrasonic probe data.

In this case, the received focus data at the first stage of the received focus of the first raster is the delay memory 10.
Is read out from the first initial value storage means 12 and input to the address addition means 14.

On the other hand, the difference data ΔA111 is inputted from the difference reception focus data section 28 to the first difference data provision means 15, and the difference data ΔA111 is inputted from the first difference data provision means 15 to the address addition means 14. A111 output from the memory address setting means 13
ΔA111 which is the output of the first difference data providing means
Are added. At this time, the number of reception focus stages is 1
Therefore, ΔA111 is naturally 0.

Therefore, the received signal stored at the address A111 is read from the delay memory 10 in synchronization with the read start clock.

On the other hand, the interpolation means 11 is the same as the control of the delay memory 10, but generally, it is necessary to set various coefficients in the interpolation, so that until the reception focus position changes, that is, the reception focus is changed. Until the number of stages changes, the interpolation coefficient memory 1 in which the previous coefficients are stored
The address of No. 6 is constant. However, in the case of a delay memory, similarly, one reception focus data is given at the start of switching, but the read address of the delay memory 10 is basically counted up by the sampling clock.

The second initial value storage means 19 stores the interpolation coefficient B111, which is the first-stage reception focus data of the reception focus of the first raster, and the read data is added to the interpolation data address. Input to means 17,
The difference data ΔB111 is inputted from the difference reception focus data means 28 to the second difference data provision means 18, and the difference data ΔB111 is inputted from the second difference data provision means 18 to the interpolation address addition means 17; B111, which is the output of the selector 25, and ΔB111, which is the output of the second difference data providing means, are added.

At this time, since the number of stages of the reception focus is 1, ΔB111 is naturally 0. Therefore, the interpolation data stored at the address B111 of the interpolation coefficient memory 16 is set in the interpolation means 11 in synchronization with the read start clock, and the interpolation processing is performed.

The interpolation data differs depending on the interpolation method, and may be one or plural.

Next, the reception focus stage is advanced by 1
The case of the stage will be described with reference to FIGS.

Assuming that the read address of the delay storage unit 10 processes k reception signals before the next reception focus switch, the read address of the delay storage unit 10 at the time of switching is A111 + k.

The differential reception focus data at the second stage is ΔA
If it is 112, it is necessary to use A111 + k as a reference for the difference. That is, the address actually required for reading the delay memory 10 is A111 + k + ΔA112.

Therefore, the output of the memory address setting means 13, which is the address of the delay storage unit 10, is input to the first selector 24, and the initial value is selected only for the first receiving focus, and the next receiving focus is selected. Is a delay storage unit 10
By selecting the address, the delay address to be given to the delay memory 10 is realized.

If the delay memory 10 is a memory having a slightly larger number of words than the number of words for realizing the maximum delay time required for receiving beam forming, the address addition means 14 and the interpolation address addition When the output of the means 17 exceeds the maximum number of words (maximum number of addresses) of the delay memory 10, the excess address is given as data as an address of the memory address setting means 13 or the interpolation coefficient memory. The capacity of the delay memory 10 can be reduced.

At this time, when the received data is written into the delay memory, the address returns to the first 0 address if the maximum address is exceeded.

The interpolation means 11 operates in the same manner as the control of the delay memory, and as shown in FIG.
Is fed back by the second selector 25.

In the first embodiment, when a plurality of received beams are formed at the same time, the received signal processing means 4 and the adding means 5 configured as described above are provided in parallel for a plurality of beams, and each of them is provided in parallel. The reception focus data can be reduced by providing the delay memory 10 and the interpolation means 11 with the reception focus data in the same manner as in the case of not using the multiple beams.

When the reception data processing is performed by time-division processing using one circuit of the reception signal processing means 4, the initial value of reception focus data at the start of reception is simultaneously set. First initial value storage means 1 by the number of beams to be formed
2 and the second initial value storage means 19, and the control by the delay control means 10 and the interpolation means 11 (the control at this time is the control of the address and the reading of the interpolation coefficient) is performed in a time-division manner. I do.

FIG. 10 shows an example of the memory configuration of the focus data memory used in the first embodiment.
0, the schematic configuration of the focus data memory will be described.

The focus data memory shown in FIG. 10 is, for example, a memory in which one word has 8 bits.
The address initial value stored in the first and second initial value storage means 12 and 19 is 8 bits, and the difference stored in the first and second difference data providing means 15 and 18 is 4 bits.

At the address 0 (zero) of the focus data memory, the read address initial value A111 of the delay memory 10 of the first raster, the interpolation coefficient memory address B111 at the address 1, the read address ΔA111 of the delay memory 10 at the address 2 , Interpolation coefficient memory address Δ
At B111, address 3, there is also difference data of the second raster in the focus of the first raster.

When the number of focus stages is n, the data of the second raster enters the same order as the first raster at the memory address n + 2.

When the number of rasters is M,
This is repeated M times.

As shown in FIG. 10, in the first embodiment, the address information stored in the focus data memory has the same number of first and second initial value storage means 12 and 19 as the number of rasters. Is 8 bits, and the other difference is 4 bits, so that the focus data memory can be reduced.

Therefore, the circuit scale of the received signal processing means can be reduced.

(Embodiment 2) FIG. 4 is a block diagram showing a schematic configuration for one channel of a received signal processing unit according to Embodiment 2 of the present invention. Reference numeral 20 denotes a first detection time error providing unit ( Phase shift address value storage means) and 21 are second detection time error giving means (phase shift address value storage means).

In FIG. 4, a first detection time error giving means 20 is a means for storing an address value for correcting a blur of a received wave focus caused by a non-uniform sound velocity in a living body. The address value corresponding to the error of the detection time between adjacent channels when the received signal stored in the received signal is read is stored.

The second detection time error giving means 21 is a means for storing an address value for correcting the blur of the reception focus caused by the unevenness of the sound speed in the living body.
An address value corresponding to an error in detection time between adjacent channels when selecting interpolation data to be given to the interpolation means 11 is stored.

Note that the first detection time error providing means 20 and the second detection time error providing means 21 of the second embodiment are used.
The method of calculating the address value to be stored in is described later.

FIG. 5 is a block diagram showing a schematic configuration of an example of a means for obtaining an address value corresponding to an error in the detection time between adjacent channels. Reference numeral 22 denotes a correlator (phase shift detecting means), and reference numeral 23 denotes a phase shifter. 7 shows reception wave focus data conversion means (correction address calculation means).

In FIG. 5, a correlator 22 is a well-known correlator for calculating a phase difference between delayed signals of adjacent channels. In the present embodiment, a received signal connected to an adjacent ultrasonic transducer is used. Based on the output of the processing means 4, the phase difference between the delayed signals of adjacent channels is obtained. The output is connected to the received wave focus data conversion means 23.

The received wave focus data conversion means 23 is means for obtaining an address value corresponding to the time difference and the interpolation coefficient based on the phase difference output of the correlator 22, and includes, for example, a program executed by the information processing device, or ,
ROM (Read Only Memory) known in advance
This can be realized by reading data stored in the.

Next, the operation of the reception signal processing means 4 according to the second embodiment will be described with reference to FIGS. 4 and 5. The reception focus data is based on the assumed sound velocity in which the sound velocity in the living body is regarded as uniform. Thus, the delay time due to the difference in distance to the reception focus point is calculated and given to the reception signal received by each transducer, thereby realizing reception focus. At this time, the same applies to the transmission.

However, it is well known that, in practice, due to the non-uniformity of the sound velocity in the living body, an error occurs in the delay time and the ultrasonic beam is not correctly received and focused. After the delay, a phase difference between adjacent ultrasonic transducers is detected (the phase difference is 0 if the delay time is correct), and a method of correcting the delay time obtained from the assumed sound speed is applied.

Therefore, as shown in FIG.
First, the phase difference between the delayed signals of the adjacent channels by the received signal processing means 4 is obtained by the received signal processing means 4, and the phase difference is converted into a time difference and an interpolation coefficient by the received focus data converting means 23. Find each address value.

The time difference at this time is quantized by the sampling time, and can be used as an address increase / decrease value of the delay memory 10. Further, the interpolation coefficient value is also quantized in the quantization unit of the coefficient value of the interpolation coefficient memory 16, and the value is used as an increase / decrease value of the address of the interpolation coefficient memory.

The address values of the increment / decrement value obtained as described above are held in the first and second detection time error giving means 20 and 21 shown in FIG.

Next, the difference values given by the first and second difference data providing means 15 and 18 of the received focus data described in the first embodiment and the first and second selectors 24 and 25 will be described. The adder, that is, the address adder 14 and the interpolation data address adder 17 add the receive focus start address selected in the above step to correct the shift of the receive focus data due to the non-uniformity of the living body.

At this time, for example, the first received signal processing means 4 and the second received signal processing means 4 convert the error of the delay time by ΔC and the error of the interpolation coefficient by address conversion to obtain ΔD, When each is detected, the reception focus of the second stage in the first raster of the channel 2, that is, the second reception signal processing means 4 is as follows.

Assuming that k reception signals are processed before the next reception focus switching, the read address of the delay memory 10 at the time of switching is A211 + k.

The differential reception focus data at the second stage is ΔA
If the address is 212, the required address is A211 + k + Δ
A212 + ΔC, while the address of the interpolation coefficient memory 16 is B211 + ΔB212 + ΔD.

That is, the first detection time error giving means 2
0 is ΔC, and the second detection time error applying means 21 is ΔC.
D is stored and output to the address adding means 14 and the interpolation data address adding means 17 together with the difference data.

Therefore, the received signal read from the delay memory 10 and the received focus data due to the non-uniformity of the living body included in the interpolation coefficient read from the interpolation coefficient memory 16 for performing interpolation on the received signal. Can be corrected with a smaller amount of memory.

(Embodiment 3) FIG. 6 is a block diagram showing a schematic configuration for one channel of a received signal processing unit according to Embodiment 3 of the present invention. (Variation value address storage means);
2 shows an initial processing variation assigning means (variation value address storage means).

In FIG. 6, the first initial processing variation imparting means 26 is unique to each ultrasonic diagnostic apparatus at the initial point in time of a received signal from each ultrasonic transducer to each received signal processing means 4. This is a means for storing a constant for correcting an error of the ultrasonic diagnostic apparatus. In particular, a constant for correcting an error peculiar to each ultrasonic diagnostic apparatus when reading a received signal stored in the delay memory 10 is stored. I do.

The second initial processing variation imparting means 27
A means for storing a constant for correcting an error unique to each ultrasonic diagnostic apparatus at an initial point in time of a received signal from each ultrasonic transducer to each received signal processing means 4, particularly And a constant for correcting an error unique to each ultrasonic diagnostic apparatus when the interpolation coefficient stored in the interpolation coefficient memory 16 is read.

In the third embodiment, the first initial processing variation applying means 26 and the second initial processing variation applying means 27 correct the read address values of the delay memory 10 and the interpolation coefficient memory 16. Is stored in a storage unit (not shown) of the overall control unit 29, and is read out on the main memory when the power of the ultrasonic apparatus is turned on.

The data of the first and second initial processing variation means 26 and 27 are added as offsets to the first and second initial value storage means 12 and 19 by an adder (not shown). is there.

Next, the operation of the reception signal processing means 4 of the third embodiment will be described with reference to FIG. 6. First, reception from each ultrasonic transducer to each reception signal processing means 4 will be described. Errors inherent in the ultrasound diagnostic device at the early time of the wave signal,
That is, the correction of the initial processing variation of the received signal in the receiving circuit will be described.

Various methods are conceivable to detect the initial processing variation, that is, the error of the receiving circuit. In the third embodiment, for example, the detection means for detecting the nonuniformity of the sound velocity in the living body is used. The correlation processing shown in FIG.

That is, the inspection at the time of shipping the ultrasonic device,
It measures the phase difference between adjacent ultrasonic transducers when the power of the ultrasonic device is turned on.

In the former case, for example, the ultrasonic probe 1 is set in a water tank, and then a flat plate target is set in parallel with the ultrasonic probe 1, and then ultrasonic waves are transmitted and received. At this time, by aging the ultrasonic device to some extent, it is possible to prevent the influence of the characteristic change due to the temperature difference of the analog circuit portion for receiving the wave, that is, to wait for the temperature of the entire ultrasonic device to calm down, The phase difference between the ultrasonic transducers to be measured is measured.

At this time, with a specific raster set in advance,
The phase difference measured by the correlator 22 shown in FIG. 5 is a value of the delay time variation peculiar to the ultrasonic device.

The value of the variation is converted by the reception focus data means 23 into an error address of the reception focus data. As described above, for example, the converted error address value is stored in a storage unit (not shown) of the overall control unit 29, and the value is read out when the ultrasonic apparatus is used, and the first and second initial processings are performed. Variation imparting means 2
Set to 6, 27.

That is, with respect to all the ultrasonic probes connected to the ultrasonic device according to the third embodiment, the dispersion of the delay time peculiar to each device was measured in advance at the stage before the device was shipped. The variation in the delay time is stored in, for example, an external storage device in the apparatus.

When the ultrasonic apparatus is used, for example, the selecting means (not shown) of the overall control means 29 recognizes the ultrasonic probe 1 to be connected, and applies a corresponding delay when the ultrasonic probe 1 is connected. By selecting the time variation data and setting the delay time variation data when the selected ultrasonic probe 1 is connected to the first and second initial processing variation imparting means 26 and 27, a unique ultrasonic device is set. Variation in delay time can be corrected.

However, the delay time variation data is considered to be constant irrespective of the raster because the passage of the received signal from the ultrasonic transducer is constant since the aperture does not move during sector scanning, and the delay time variation data is determined at the start of diagnosis. It is stored once in the first and second initial processing variation giving means 26, 27.

On the other hand, when the ultrasonic probe 1 having a moving diameter such as a linear one is used, the path to each of the received signal processing stages 4 is different. 2 are stored in the initial processing variation imparting means 26 and 27.

When the first and second initial processing variation giving means 26 and 27 at the start of the diagnosis are considered to have a small delay time error due to the difference in the path due to the aperture movement,
As in the case of the sector scanning, only one variation data of the delay time peculiar to the ultrasonic apparatus may be used. Further, the correction address at this time may be incorporated into the initial value in the overall control means 29 and then transferred to the first and second initial value storage means 12 and 19 of each received signal processing means 4. Needless to say.

(Embodiment 4) FIG. 7 is a diagram for explaining the operation for one channel of the received signal processing means according to Embodiment 4 of the present invention, and FIG. FIG. 7B is a block diagram showing a schematic configuration of one channel of the means, and FIG. 7B is a diagram for explaining a method of selecting a multilayer sampling clock.

In FIG. 7, reference numeral 31 denotes a multilayer sampling clock generating means, and 33 denotes an error correction applying means.
The multilayer sampling clock generator 31 is a well-known multilayer clock generator.

The error correction applying means 33 is a means for selecting a sampling clock having a delay time necessary for correcting a characteristic variation inherent in the ultrasonic apparatus and a delay time error due to a non-uniform sound speed of a living body. It will be described later.

The received signal processing means of the fourth embodiment has a multi-layered sampling clock, which is a well-known technique, instead of interpolation processing for a minute delay, and uses the ADC sampling clock of the received signal processing means 4 as a reference. By selecting a clock shifted by a predetermined minute time and sampling the received signal with this clock, a minute delay smaller than the sampling time interval between the reference ultrasonic transducer and the sampling time is realized, and the sampled signal is sampled. A well-known wavefront synchronization sample (concave sample) that stores a received signal in the delay memory 10 and delays the received signal at sampling intervals.
This is an embodiment when the present invention is applied.

However, in the fourth embodiment, AD
The sampling clock of C9 is provided by the sampling clock generating means 31.

Next, Embodiment 4 will be described with reference to FIG.
The operation of the received signal processing means is described as follows. As shown in this figure, the cycle of the sampling clock is T, and ΔT
It has multiple sampling clocks shifted in time units.

In the fourth embodiment, the sampling clock has four layers.

The ADC 9 of each received signal processing means 4 selects one of the sampling clocks of the four layers. To select the sampling clock of the four layers, 2b
It requires a control signal of it. The selected data of the sampling clock is one of the received wave focus data.

Further, the delay at the sampling interval is
This is the same as the above-mentioned case, and the first initial value storage means 12,
First difference data providing means 15, address adding means 14
And memory address setting means 13.

As described above, the sampling clock generating means 31 corrects the selection data for selecting the sampling clocks of the four layers, in the same manner as described above, for the characteristic variation inherent in the ultrasonic apparatus and the delay time error due to the nonuniform sound speed of the living body. , And the remainder quantized by the sampling period is further quantized by the difference ΔT between the multilayer sampling clocks,
The data for correcting (selecting) the sampling clock with the latter value is added to the reception focus data conversion means 23.
To convert.

The reception focus data conversion means 23 supplies the converted sampling clock selection data to the difference correction giving section 33.

For example, if the sampling interval is 40 ns, the difference ΔT between the multi-layer clocks is ΔT = 10 ns, and the difference delay amount due to the assumed sound speed is 220 ns, the address becomes 5 and the remainder becomes 20 ns due to quantization at T. The delay is 20 ns.

At this time, the delay amount of the delay memory 10 is 20
0 ns.

When the minute delay clock selection data is 2
(The clock difference from the reference channel is 10 ns and 20 ns respectively when the minute delay clock selection data = 1, 2, and 3)
s, 30 ns), and the difference address of the delay memory 10 is 200 ns / 40 ns = 5.

If the sum of the various errors is +90 ns, a correction of -90 ns is required.

Therefore, 90/40 = 2 remainder 10 ns
Therefore, -1 is given to the minute delay clock selection data given to the sampling clock generation means 31, and 2-1 =
1 and a sampling clock shifted by 10 ns is selected.

Further, -2 is input to the detection time error of the delay memory 10.

As a result, 5-2 = 3 becomes difference data, and correction is performed.

In the first to fourth embodiments described above, it is needless to say that the ultrasonic diagnostic apparatus can be reduced in size and cost by integrating one or more channels of each received signal processing means 4.

This integrated ASIC has a CPU (Central Processing) as a control means.
Unit, central processing unit) or DSP (Dig)
It integrates arithmetic means such as ital Signal Processor,), and performs calculation of received focus data and detection of non-uniformity of sound speed in a living body.
It goes without saying that the overall control of the reception focus of the ultrasonic diagnostic apparatus can be reduced.

Furthermore, CPU control may be performed for each substrate and for the entire ultrasonic apparatus.

Further, in the present embodiment, the operation has been described assuming that the sampling clock of ADC 9 and the clock of the receiving process at the subsequent stage are the same. For example, as shown in FIG. Mixing means 34
Is provided, a complex signal is formed by this output, and oversampling is realized by moving to a low frequency (or zero frequency). After moving to a low frequency and extracting the component with the filter 35, the signal is decimated and the number of signals is reduced. Reduce
Thereafter, the clocks of the delay memory 10 and the interpolating means 11 can be delayed.

At this time, it goes without saying that the clock may be used as it is.

Further, the received signal shifted to the zero frequency is shifted to the delay memory 10 and read out to delay the sampling interval in the same manner as described above, and the complex signal is processed by the interpolation means 11. This process is a process of rotating the phase.

The ultrasonic apparatus according to the present embodiment is a sector scanning type ultrasonic apparatus. However, the ultrasonic apparatus according to the present embodiment can be applied to other types of ultrasonic apparatuses, such as a linear moving type and a convex moving type. Needless to say.

Also, according to the present invention, the sampling period of a low-speed ADC is, for example, from 20 MHz to 60 MHz.
In particular, the above-mentioned effect is remarkable for the frequency of MHz.

As described above, the invention made by the present inventors is described below.
Although specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the gist of the present invention. .

[0199]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In an ultrasonic apparatus, reception focus data used for forming a digitized reception beam can be reduced.

(2) In the ultrasonic apparatus, the area of the circuit constituting the received signal processing means can be reduced.

(3) In the ultrasonic apparatus, it is possible to correct a time variation peculiar to each ultrasonic diagnostic apparatus in each processing means.

(4) In the ultrasonic apparatus, it is possible to correct a delay error caused by a difference in sound velocity distribution in each part in the subject.

(5) In the ultrasonic device, the storage capacity of the delay memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an ultrasonic apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram for explaining a basic configuration for one channel of a received signal processing unit according to the first embodiment.

FIG. 3 is a block diagram illustrating a schematic configuration of a received signal processing unit according to the first embodiment.

FIG. 4 shows one of received signal processing means according to the second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a schematic configuration for channels.

FIG. 5 is a block diagram showing a schematic configuration of an example of a means for obtaining an address value corresponding to an error in detection time between adjacent channels.

FIG. 6 shows one of received wave signal processing means according to the third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a schematic configuration for channels.

FIG. 7 shows one of the received signal processing means according to the fourth embodiment of the present invention.
FIG. 3 is a diagram for explaining operations for channels.

FIG. 8 is a diagram for explaining the operation of the received signal processing means of the first embodiment.

FIG. 9 is a block diagram illustrating a schematic configuration of an ultrasonic apparatus in which a sampling clock of an ADC is different from a clock of a received signal processing unit in a subsequent stage.

FIG. 10 is a diagram illustrating an example of a memory configuration of a focus data memory according to the first embodiment;

FIG. 11 is a block diagram illustrating a schematic configuration of a conventional ultrasonic device.

FIG. 12 is a block diagram illustrating a schematic configuration of a wave reception processing unit of a conventional ultrasonic device.

[Explanation of symbols]

1. Ultrasonic probe, 2. Analog transmission / reception switching circuit, 3.
... wave transmission circuit, 4 ... reception signal processing means, 5 ... addition means, 6
... Signal processing means, 7 ... Display means, 9 ... Analog-digital converter, 10 ... Delay memory, 11 ... Interpolation means, 12
... first initial value storage means, 13 ... memory address setting means, 14 ... address addition means, 15 ... first difference data adding means, 16 ... interpolation coefficient memory, 17 ... interpolation data address addition means, 18 ... second Differential data adding means, 1
9: second initial value storage means, 20: first detection time error providing means, 21: second detection time error providing means, 22 ...
Correlator, 23 ... received wave focus data conversion means, 24 ...
A first selector, 25... A second selector, 26... A first initial processing variation providing means, 27. A second initial processing variation providing means, 28.
29: Overall control means, 31: Multi-layer sampling clock generating means, 32: Receiving focus data memory, 33 ...
Error correction giving means, 34 ... complex mixing means, 35 ...
filter.

Claims (7)

[Claims] 1. A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, a plurality of converting means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, respectively, and the converting means A plurality of received data storage means for storing the output of the received data, signal adding means for reading and adding the received data stored in the received data storage means, and output control for outputting the added signals in a predetermined order And a display unit for displaying an ultrasonic image based on the output signal, wherein the first one of the reception signal data stored in the reception data storage unit is read out. Initial address storage means for storing the address value of the signal data, difference value storage means for storing the difference value of the address value for each focus stage, and the difference between the first read address value or the previous stage address value and the difference value Comprising an address adding means for adding,
At the time of reading the received signal data, the reception level corresponding to the focus stage is determined based on the address value stored in the initial address storage unit or the address value of the stage before the focus and the difference value stored in the difference value storage unit. An ultrasonic apparatus which sequentially reads out wave signal data and performs a delay treatment. 2. A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, conversion means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, and an output of the conversion means. Storage means for storing, a received signal stored in the storage means for reading and delaying, an interpolation processing means for performing interpolation processing on the delayed received signal, and adding a plurality of received signals after the interpolation processing And an output control means for outputting the added signal in a predetermined order, and a display means for displaying an ultrasonic image based on the output signal. Interpolation coefficient storage means, an interpolation coefficient address storage means for storing an interpolation coefficient address value to be read first among interpolation coefficients stored in the interpolation coefficient storage means, and an interpolation coefficient address value for each focus stage. Store the difference value Interpolating coefficient difference value storing means, and interpolating coefficient address adding means for adding the address value of the interpolation coefficient to be read first or the address value of the preceding interpolating coefficient and the difference value. Based on the interpolation coefficient address value or the previous stage address value stored in the initial interpolation coefficient address storage means and the difference value stored in the interpolation coefficient difference value storage means, read out the interpolation coefficient corresponding to the focus stage, An ultrasonic apparatus, which performs an interpolation process on a received signal read from the storage unit. 3. A plurality of ultrasonic transducers for transmitting and receiving ultrasonic waves, conversion means for converting ultrasonic signals received by the ultrasonic transducers into digital signals, and an output of the conversion means. Storing means for storing, interpolating means for interpolating the received signals stored in the storing means in reading order, signal adding means for adding a plurality of received signals after the interpolation processing, and the added signal Output control means for outputting in a predetermined order,
Display means for displaying an ultrasonic image based on the output signal, wherein the received signal data to be read first among the received signal data stored in the received data storage means. Initial address storage means for storing an address value; difference value storage means for storing a difference value of the address value for each focus stage; and adding the first read address value or the previous stage address value to the difference value. Address addition means, interpolation coefficient storage means for storing interpolation coefficients, initial interpolation coefficient address storage means for storing first interpolation coefficient address values to be read out of interpolation coefficients stored in the interpolation coefficient storage means,
Interpolation coefficient difference value storage means for storing a difference value of an interpolation coefficient address value for each focus stage, and interpolation for adding the difference value to the address value of the interpolation coefficient to be read first or the interpolation coefficient address value of the preceding stage. A coefficient address adding unit, wherein at the time of reading the received signal data, based on the address value stored in the initial address storage unit or the address value of the stage before the focus and the difference value stored in the difference value storage unit. The received signal data corresponding to the focus stage is sequentially read out, and the interpolation coefficient address value or the previous stage address value stored in the initial interpolation coefficient address storage unit and the interpolation coefficient difference value storage unit are stored. An interpolation coefficient corresponding to the focus stage is read based on the difference value, and the interpolation coefficient is read from the storage unit. Ultrasonic apparatus characterized by interpolating wave signals. 4. A phase shift detecting means for detecting a phase shift of the received signal between each of the ultrasonic transducers in a received signal obtained by delaying a received signal received by a plurality of ultrasonic transducers and adjusting a phase of the received signal. Correction address calculation means for calculating an address value corresponding to a phase shift correction value based on the output value of the phase shift detection means; phase shift address value storage means for storing the correction address value; 4. The ultrasonic apparatus according to claim 1, further comprising: a unit that corrects a difference value input to the address adding unit and the interpolation coefficient address adding unit based on the following equation. 5. A variation value address storage means for measuring an ultrasonic measurement characteristic based on an individual difference for each apparatus in advance and storing an address value corresponding to a correction value calculated based on the measurement value, and a variation value address. 5. The ultrasonic apparatus according to claim 1, further comprising: a unit that corrects the initial address value and the initial interpolation coefficient address value based on an address value of a storage unit. 6. The reception data storage means stores the ultrasonic signals converted into digital signals by the conversion means in order within a predetermined capacity, and stores the converted ultrasonic signals in the reception data storage means. 6. The apparatus according to claim 1, wherein when the capacity exceeds the capacity of the means, the means for storing an ultrasonic signal exceeding the capacity from the head of the reception data storage means. Ultrasound device. 7. An address value output from said address addition means is compared with a capacity of said reception data storage means, and an address value output from said address addition means exceeds a capacity of said reception data storage means. When the value becomes, the address value corresponding to the capacity of the received data storage means is subtracted from the exceeded address value, and based on the address value, the read address setting for sequentially reading the received signal data corresponding to the focus stage. 7. The ultrasonic apparatus according to claim 6, further comprising: means.