JPH0418815A - Serial/parallel-type analog/digital converter and its driving method - Google Patents

Abstract

PURPOSE:To improve resolution and speed by using three-stage pipe line constitution and the interleaving constitution of a final stage. CONSTITUTION:This converter is provided with a first analog/digital(A/D) converter 2 converting the output signal of a first sample-hold(S/H) circuit 1 into a digital value, a first D/A converter 3 converting the conversion result into an analog signal, a second A/D converter 6 converting the output of a subtraction circuit 5 into the digital value, a second D/A converter 8 converting the output of an adder 7 into the analog signal, a third A/D converter 12 converting the output of the adder 7 into the analog signal and a fourth A/D converter 15 converting the output of the subtraction circuit 14 into the digital value. Thus, the serial/parallel type A/D converter with high resolution and high speed can easily be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a series-parallel type analog/digital (A/D) converter and a method for driving the same.

[Conventional technology]

As a conventional series-parallel type A/D converter, a series-parallel type A/D converter as shown in FIG. 3 is known (IEICE Technical Research Report, Vol. 89. No.

205, p25. lCD89-115). This series-parallel type A/D converter includes a Hanwha amplifier 31 and a first sample and hold (1) that samples and holds an input signal.
S/H) circuit 32 and the output of the first S/H circuit 32
A first parallel A/D converter 33 that performs /D conversion, and a second S/H circuit 3 that receives the output of the first S/H circuit 32.
4, a D/A conversion circuit 35 that converts the output of the first parallel A/D converter 33 into an analog signal, and an output of the D/A conversion circuit 35 from the output of the second S/H circuit 34. A subtracter 36 that performs subtraction, a second parallel A/D converter 37 that A/D converts the output of the subtracter, encoders 38, 39, and a parallel A/D converter 33 that connects these encoders. 37
and an adder 40 that adds the outputs of the .

This series/parallel type A/D converter has an 8-bit resolution, and first, the upper 4 bits are A/D converted by the first A/D converter 33.
Next, a subtracter 36 subtracts the voltage obtained by D/A converting the upper bits from the input signal held in the S/H circuit 34, and the remaining voltage is converted into an A/D converter 37 by a second A/D converter 37. D
The lower 5 bits are converted and the lower 5 bits are added, and the upper 4 bits and the lower 5 bits are added to obtain the final 8 bits conversion result. The reason why there is one extra bit in the lower bit is because in order to correct the conversion error in the upper bit, when adding, the upper and lower bits are overlapping by one bit.
This results in a conversion of 4+5-1=8 focuses.

The second S/H circuit 34 performs pipeline operation for upper-level conversion and lower-level conversion, thereby increasing the appearance.
A conversion is performed for each clove.

Moreover, this serial-parallel type A/D converter does not directly amplify the output of the subtracter 36, but A/D converts it again to obtain the lower bits. Therefore, high resolution is required for the lower A/D converter, so two sets of comparators for each lower A/D converter are provided and operated in an interleaved manner, doubling the operating time of the part that requires high resolution. I have to. Therefore, if the sampling frequency of this series-parallel type A/D converter is F, then the operating period is Ts = 1/Fs, and the operating time and accuracy (series-parallel type A/D converter) required for each block that handles analog signals is (based on the input full scale of the D converter) is
The S/H circuit has an operating time Ts (however, the operating time is T, /2 in the sample mode and T, /2 in the hold mode), and the first A/D converter 33 has an operating time of Ts. , the accuracy is 4 bits, and the second A/D converter 37 has an operating time of 2Ts and has an accuracy of 8 bits.

The D/A converter 35 and the subtracter 36 have an operating time of TS/2 and an accuracy of TS/2 for both D/A conversion and subtraction because the output of the subtracter is input to the second A/D converter 37. is 8 bits. Assuming that the input full scale of this series-parallel A/D converter is 2V, the 8-pin A/D converter has I LS
B becomes (1/2")X2[v] = 7.8125[mV], and 8-bit accuracy means that the error is within LSg/2, that is, within about 349mV.

In the example shown in Figure 3, 50Msample/sec (Msps
) conversion speed is reported, and is the fastest among 8-bit array type A/D converters with a CMO5 configuration.

In that case, it becomes Ts -20 nsec.

[Problem to be solved by the invention] Here, the series-parallel type A/D converter described in the prior art is
Consider increasing the resolution to 0 bits.

10 vias), it is necessary to increase the resolution of the first A/D converter 33 or the second A/D converter 370. The resolutions of the first A/D converter and the second A/D converter can be set in the following settings (1) to (1).

(1) First A/D converter 4 bits, second A/D converter 7 bits (11) First A/D converter 5 bits, 7 bits, second A/D converter 6 bits ( ■) First A/D converter 6 bits Second A/D converter 5 pins (iv) First A/D converter 7 bits Second A/D converter 4 bits Resolution is 10 bits In this case, if the input full scale of the series-parallel A/D converter is 2ν, ILSB = (1/2'0)X2[ν] #1.9
5 [mν].

When high resolution is achieved using the conventional method, the requirements for each block that handles analog signals are as follows for the first stage S/H circuit: (i)
~(iv) both have 10-bit precision and operating time Ts (
Ts = I/Fs, Fs is the sampling frequency), but for other blocks, (i) to (iv) are as shown in the following table.

Also, the hardware amount of a parallel A/D converter increases in proportion to 2'' (n is the resolution), so if the heart 1 of a 4-bit parallel A/D converter is 1, the first A/D Transducer, second
The hardware amount of the A/D converter and the overall parallel type A/D converter is (i) to (1), which is similar to that of an adult.

However, since the second A/D converter has two sets of comparators and performs interleaving operation, the amount of hardware is doubled, and the second A/D converter's 4-bit parallel A/D converter The converter has a hard quantity of 2.

By the way, in the case of a conventional 8-pin direct series A/D converter, the 10th A/D converter is 1 and the 2nd A/D converter is 2.
×2, the total is 1+2X2=5.

Therefore, with the conventional technology, a series-parallel type A/
When the D converter is constructed, the precision and operating time of the D/A conversion/subtraction circuit become 10-bit precision, T,/2. If the input full scale of the series-parallel A/D converter is 2V and the sampling speed is 50M5ps, the error is within 0.98mV with 10-bit accuracy, and the operating time is 10ns.
It becomes ec.

Further, the hardware amount of the parallel A/D converter included in the series-parallel A/D converter is 8, assuming that the minimum 4-bit parallel A/D converter is 1. In the conventional technology, the D/A conversion/subtraction circuit has an error within 3.9 mV and an operating time of 10 ns.
It was realized with ec. When configured using CMO3 technology, a serial-parallel A/D converter with 10-bit resolution can be realized using conventional technology by converting the D/A conversion/subtraction circuit to an error of 0.
It must be operated within 98 mV and within an operating time of 10 nsec, which is difficult to realize.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a high-speed serial-parallel A/D converter with higher resolution than conventional A/D converters and a method for driving the same.

[Means to solve the problem]

The series-parallel A/D converter of the present invention includes a first sample-and-hold circuit connected to an input terminal, and a first analog/digital converter that converts the output signal of the first sample-and-hold circuit into a digital value. a digital converter; a first digital/analog converter that converts the conversion result of the first analog/digital converter back into an analog signal; sample-and-hold circuit and this second sample-and-hold circuit.
a first subtraction circuit that subtracts the output of the first digital/analog converter from the output of the hold circuit; and a second subtraction circuit that converts the output of the first subtraction circuit into a digital value.
an analog/digital converter of the first analog/digital converter;
a first adder that adds the conversion result of the digital converter and the conversion result of the second analog/digital converter; and a second digital adder that converts the output of the first adder into an analog signal. /an analog converter, three sample-and-hold circuits that receive the output of the first sample-and-hold circuit, and an output from the third sample-and-hold circuit to the output of the second digital-to-analog converter. a second subtraction circuit that subtracts the value, and a third subtraction circuit that converts the output of the second subtraction circuit into a digital value.
a third digital/analog converter that converts the output of the first adder into an analog signal, and a fourth sample whose input is the output of the first sample and hold circuit.・Hold circuit and this fourth
a third subtraction circuit that subtracts the output of the third digital/analog converter from the output of the sample-and-hold circuit; and a fourth subtraction circuit that converts the output of the third subtraction circuit into a digital value.
an analog/digital converter; and the third analog/digital converter.
a multiplexer that multiplexes the output of the digital converter and the output of the fourth analog/digital converter; the first analog/digital converter, the second analog/digital converter, and the output of the multiplexer; and a second adder that adds .

The method for driving a series-parallel A/D converter of the present invention includes the first
The sample and hold circuit is driven by the first clock φ1, and the second sample and hold circuit is driven by the second clock φ1.
2, and the third sample and hold circuit is driven by a third clock φ
3, and the fourth sample-and-hold circuit is driven by a fourth clock φ
, the second digital/analog conversion circuit and the second subtraction circuit are driven by a clock φ, and the third digital/analog conversion circuit and the second subtraction circuit are driven by a clock φ,
The analog conversion circuit and the third subtraction circuit are clocked by φ6.
The clocks φ1 and φ2 are non-overlapping two-phase clocks with a duty cycle close to 50%, and the clock φ has a period twice that of the clock φ2, and the clock φ2 is 'H'. The clock φ4 is set to be “H” every other period, and the clock φ4 has a period twice that of the clock φ2, and the clock φ4 is set to “H” every other period during which the clock φ2 is “H''.
Let the clock φ be “H” when it does not overlap with the clock φ, and let the clock φ be the clock that becomes “H” when it does not overlap with the clock φ, and
A clock whose period is more than three times as long as the period of the clock φ3 and the period of the clock φ3, and the clock φ6 is a clock obtained by shifting the clock φ5 by 1/2 period so as not to overlap with the clock φ4. do.

〔Example〕

FIG. 1 shows an embodiment of the series-parallel type A/D converter of the present invention.

This series/parallel type A/D converter includes a first S/H circuit 1 connected to an input terminal, and a first parallel type A/D converter that converts the output signal of the first S/H circuit 1 into a digital value. A/D converter 2
, a first D/A converter 3 that converts the conversion result of the first A/D converter 2 into an analog signal again, and a first S
/) (A second S/H circuit 4 whose input is the output of the circuit 1, and a first S/H circuit 4 that subtracts the output of the first D/A converter 3 from the output of this second S/H circuit 4. A subtraction circuit 5, a second parallel A/D converter 6 that converts the output of the first subtraction circuit 5 into a digital value, and the conversion result of the first parallel A/D converter 2, A first adder 7 that adds the conversion result of the second parallel A/D converter 6, and a second D/A converter 8 that converts the output of the first adder 7 into an analog signal. , a third S/H circuit 9 whose input is the output of the first S/H circuit 1, and a second D/H circuit 9 from which the output of the third S/H circuit 9 is input.
A second subtraction circuit 11 that subtracts the output of the A converter 8, a third parallel A/D converter 12 that converts the output of the second subtraction circuit 11 into a digital value, and a first adder. a third D/A converter 13 that converts the output of 7 into an analog signal;
A fourth S/H circuit 10 receives the output of the first S/H circuit 1, and subtracts the output of the third D/A converter 13 from the output of this fourth S/H circuit 10. Third subtraction circuit 14
, a fourth parallel A/D converter 15 that converts the output of the third subtraction circuit 14 into a digital value, and a third parallel A/D converter 15
, the output of the /D converter 12 and the fourth parallel type A/D converter 1
a multiplexer 16 that multiplexes the outputs of the first parallel A/D converter 2 and the second A/D converter 6;
and a second adder 17 that adds the output of the multiplexer 16.

FIG. 2 shows the waveform of the clock that drives the serial-parallel type A/D converter of this embodiment.

φ is a clock that drives the first S/H circuit, φ2 is a clock that drives the second S/H circuit 4, φ is a clock that drives the third S/H circuit 9, φ4 is a clock that drives the fourth S/H circuit 10; φ is a clock that drives the second D/A conversion circuit 8 and second subtraction circuit 11; φ6 is a clock that drives the third D/A circuit 11; This is a clock that drives the conversion circuit 13 and the third subtraction circuit 14.

The clocks φ and φ2 are two-phase clocks with a duty cycle close to 50% and do not overlap with each other, and the period of the clock φ is twice that of the clock φ2, and the clock φ2 is high.
' becomes "H" every other period, and the clock φ4
The period is twice that of clock φ2, and clock φ2 is “H”
It becomes ``H'' when it does not overlap with clock φ in every other period of a certain period, and clock φ5 does not overlap with clock φ3, and the ``H'' period is three times the ``H'' period of clock φ3. The clock φ6 is a clock obtained by shifting the clock φ by 1/2 period so as not to overlap with the clock φ4.

An embodiment of the driving method of the present invention will be described below with reference to FIGS. 1 and 2.

The first S/H circuit 1 samples the analog input signal during the period when the clock φ is “°H”. Then clock φ
1 becomes L''', the first S/H circuit 1 enters the halt mode and holds the sampled input signal.At the same time, the second S/H circuit 4 and the third S/H circuit 9 is in sampling mode (clocks φ2 and φ3 are “H”)
), the output of the first S/H circuit 1 is sampled.

The timing at which the second S/H circuit 4 samples is
Clock φ2 is determined by the timing when it changes from “H” to “L”, and in order to avoid being affected by changes in clock φ during sampling, clocks φ1 and φ2 are set at “H” level. The clocks have periods that do not overlap.

The first parallel A/D converter 2 receives the “H” level of the clock φ2.
When the input signals are compared at the timing T2 when LL passes from ``LL'', the holding time of the first S/H circuit 1 is approximately
I can use a cup.

Next, during the period when the clock φ2 is “L”, the second S/H
The circuit 4 holds the sampled voltage, and during this time the output of the first A/D converter 2 is transferred to the first D/A converter 3.
The signal is converted into an analog signal by a first subtracter 5, and then subtracted from the output of the second S/H@ path 4 by a first subtracter 5. The subtracted signal is input to the second parallel A/D converter 6. The clock φ1 becomes “H” again, and the clock φ1 becomes “H” again.
A comparison is performed in the second A/D converter 6 at timing T3 when the signal goes from P to "L". Therefore, the first glue, /
The A converter 3 and the first subtractor 5 are connected to each other.

/2 (TS = 1/FS, FS is the sampling rate). Further, since the analog signal is inputted to the second A/D converter 6 in this signal path, the accuracy of the first D/A converter 3 and the first subtracter 5 is the same as that of the first The accuracy may be as long as the resolution determined by the A/D converter 2 and the second A/D converter 6. timing T
When the clock φ1 becomes H'' again between T2 and T3, the first S/H circuit 1 is sampling the next input signal, and the first and second stages perform pipeline operation. ing.

At timing T2, clock φ3 changes from H' to °'L'' at the same time as clock φ2, and then clock φ2 changes to “H°
゛, Even if the change of “L” is repeated once, it remains “L”, and when the clock φ2 becomes H for the second time, ° “H”
”. Therefore, the period of clock φ3 is twice that of φ2.
”, the second S/H circuit 4 and the first S/H circuit 4 simultaneously
The output of circuit 1 is sampled, and clock φ3 is “L”
retains its value for a period of time.

The outputs of the first A/D converter 2 and the second A/D converter 6 are added by the first adder 7, and the result is converted into an analog signal by the second D/A converter 8. , is subtracted from the output of the third S/H circuit 9 by a second subtracter 11. The subtracted signal is input to the third A/D converter 12. The addition in the adder 7, the conversion in the D/A converter 8, and the subtraction in the subtracter 11 are performed within the period when the clock φ3 is “L”°.
Effect of change in clock φ3 (clock feedthrough)
In order to avoid this, the clock φ does not overlap with the clock φ3.

, and is performed during the period when the clock φ is "H".

In order to effectively use the period when the clock φ3 is “L”,
The period during which the clock φ is “H” starts from the time when the clock φ1 becomes “H” immediately after the timing T2, and the period when the clock φ is “H”
, and in this case, the duty cycle of the clock φ5 is approximately (3/2)T, which is more than three times the duty cycle of the clock φ3. Comparison is performed in the third A/D converter 12 at timing T when the clock φ5 changes from "H" to "L". Timing T z, T 3. The first A performed respectively at T s
/D converter 2. Second A/D converter6. By aligning the evening and timing of the outputs of the third A/D converter 12 and adding them in the second adder 17, the A/D conversion result of the input signal sampled at timing T can be obtained.

S/H circuit 9. D/A converter8. The accuracy of the subtractor 11 is
Although accuracy up to the final resolution is required, the operating time is
Converter 8. The subtracter 11 obtains approximately (3/2)T, which is three times that of the conventional method.

Furthermore, by setting the clock φ5 to a clock that does not overlap with φ3, it is possible to avoid the influence of clock foot-through of φ3 that existed in the past, and it is possible to perform conversion with higher precision than in the past.

Further, the next input signal inputted to the first S/'H circuit 1 between timings T2 and T3 and sampled at timing T3 is input to the Hall L between timings T and T4.
The second S/H circuit 4 and the fourth S/H circuit 1
sampled at 0. The input signal sampled at timing T is sent to the second S/H circuit 4. 1st A/
D converter 2. First D/A converter3. First subtractor5.
Second A/D converter6. Third S/H circuit9. second D
/'A converter 8. Second subtractor 11. In the same way as the input signal sampled at timing T3 is converted into the final result by the third A/D converter 12 and the second adder 17, the input signal is sent to the second S/H circuit 4. First A/D converter2. First D/A converter3. First subtractor5. Second A
/D converter6. Fourth S/H circuit 10. Third D/A converter 13. Third subtractor 14゜Fourth A/D converter 15
．． The second adder 17 converts it into the final result.

Among these, (third S/H circuit 9. second D/A converter 8. second subtracter 11. third A/D converter 12) and (
Fourth S/H circuit 10. Third D/A converter 13. Third
subtractor 14. The fourth A/D converter 15) has clocks φ3 and φ4. As can be seen from the fact that the clocks φ and φ are out of phase by 180°, the increment operation is performed with the period being twice that of the first and second stages and the phases are shifted.

Therefore, the second adder 17 is connected to the third A/D converter 1
2 and the output of the fourth A/D converter 115 are multiplexed and input.

To put the above operation simply, the serial-parallel A/D converter of the present invention has a three-stage pipeline configuration and an interleaved configuration in the final stage, achieving high resolution and high speed.

Let us consider that the series-parallel A/D converter of this embodiment constitutes a series-parallel A/D converter with a resolution of 10 points, which is higher than the conventional one. At that time, the first A/D converter 2. Second A/D converter6. If the resolution of the third A/D converter 12 is 4 bits, it can be configured with a three-stage vibrating line.

The accuracy and operating time of the parallel A/D converter, D/A converter, and subtractor are similar to those of adults if we summarize what has been described in the embodiments.

As is clear from this, the operating time of the D/A converter and subtracter is three times longer than in the case of the conventional configuration. As a result, even if the accuracy is higher than that of the conventional method, sufficient operation time can be taken, making it easier to implement than the conventional method. Further, the hardware amount of the parallel type A/D converter included in the series/parallel type A/D converter is at most 4, which is 1/2 of that in the case of the conventional technology.

〔Effect of the invention〕

As described above, according to the present invention, a high-resolution, high-speed series-parallel A/D converter can be realized more easily than in the past. Further, the hardware amount of the parallel A/D converter included therein can be reduced to less than half that of the conventional method.

[Brief explanation of the drawing]

1 is a diagram showing an embodiment of the serial-parallel type A/D converter of the present invention; FIG. 2 is a diagram showing a clock for driving the series-parallel type A/D converter of FIG. 1; FIG. 3 is a diagram showing a conventional series-parallel type A/D converter. ■・・ 2・・ 3・・ 4・・ 5・・ 6・・ 7・・ 8・・ 9・・ 10・・ 11・・ 12・・ 13・・ 14・・ 15・・ 16・・ 17・- First S/H circuit, first parallel type A/D converter, first D/A converter, second S/H circuit, first subtracter, second parallel type A/D converter, first Adder Second D/A converter Third S/H circuit Fourth S/H circuit Second subtracter Third parallel A/D converter Third D/A converter Third Subtractor Fourth parallel A/D converter Multiplexer Second adder Series 2

Claims (2)

[Claims] (1) A first sample-and-hold circuit connected to the input terminal; a first analog-to-digital converter that converts the output signal of this first sample-and-hold circuit into a digital value; a first digital/analog converter that converts the conversion result of the /digital converter back into an analog signal; two sample/hold circuits that receive the output of the first sample/hold circuit as input; from the output of the sample-and-hold circuit of the first
a first subtraction circuit that subtracts the output of the digital/analog converter; and a second subtraction circuit that converts the output of the first subtraction circuit into a digital value.
an analog/digital converter; a first adder that adds the conversion result of the first analog/digital converter and the conversion result of the second analog/digital converter; a second converting the output of the adder into an analog signal;
a digital/analog converter; three sample-and-hold circuits that receive the output of the first sample-and-hold circuit;
a second subtraction circuit that subtracts the output of the digital/analog converter; and a third subtraction circuit that converts the output of the second subtraction circuit into a digital value.
an analog/digital converter, and a third converter for converting the output of the first adder into an analog signal.
a digital/analog converter; a fourth sample-and-hold circuit that receives the output of the first sample-and-hold circuit; and converts the output of the fourth sample-and-hold circuit to the third digital-to-analog converter. a third subtraction circuit that subtracts the output of the subtraction circuit; and a fourth subtraction circuit that converts the output of the third subtraction circuit into a digital value.
an analog/digital converter; an output of the third analog/digital converter; and an output of the fourth analog/digital converter.
a multiplexer that multiplexes the outputs of the analog/digital converters of the first analog/digital converter, and a second adder that adds the outputs of the first analog/digital converter, the second analog/digital converter, and the multiplexer; A serial-parallel type A/D converter comprising: (2) In the method of driving a serial-parallel A/D converter according to claim 1, the first sample-and-hold circuit is driven by a first clock φ.
_1, and the second sample and hold circuit is driven by a second clock φ
_2, and the third sample-and-hold circuit is driven by a third clock φ
_3, and the fourth sample and hold circuit is driven by a fourth clock φ
_4, the second digital/analog conversion circuit and the second subtraction circuit are driven by the clock φ_5, and the third digital/analog conversion circuit and the third subtraction circuit are driven by the clock φ_5.
The clocks φ_1 and φ_2 are non-overlapping two-phase clocks with a duty cycle close to 50%, and the clock φ_3 has a period twice that of the clock φ_2, and the clock φ_2 is ゜“H”. “H” every other period
”, and the clock φ_4 is a clock whose period is twice that of the clock φ_2 and becomes “H” every other period during which the clock φ_2 is “H” and does not overlap with the clock φ_3; φ_5 does not overlap with clock φ_3 and “
The clock is characterized in that its "H" period is three or more times the "H" period of the clock φ_3, and the clock φ_6 is a clock obtained by shifting the clock φ_5 by 1/2 period so as not to overlap with the clock φ_4. A method for driving a series-parallel A/D converter.