JPH0419031U

JPH0419031U -

Info

Publication number: JPH0419031U
Application number: JP5831090U
Authority: JP
Priority date: 1990-06-01
Filing date: 1990-06-01
Publication date: 1992-02-18

Description

[Brief explanation of the drawing]

第１図は本考案の逐次比較型Ａ／Ｄ変換器の一
実施例の構成を示すブロツク図、第２図は第１図
の実施例の動作を説明するタイミングチヤート、
第３図は逐次比較動作を模式的に説明する図、第
４図は従来の逐次比較型Ａ／Ｄ変換器の一例の構
成を示すブロツク図、第５図は第４図の例の動作
を説明するタイミングチヤート、第６図は第４図
の例の比較器の動作を説明する特性図である。１……サンプフホールド回路、２……比較器、
３……基準レベル発生回路、４……逐次比較レジ
スタ、５，６……タイミング制御回路。 FIG. 1 is a block diagram showing the configuration of an embodiment of the successive approximation type A/D converter of the present invention, and FIG. 2 is a timing chart explaining the operation of the embodiment of FIG. 1.
Fig. 3 is a diagram schematically explaining the successive approximation operation, Fig. 4 is a block diagram showing the configuration of an example of a conventional successive approximation type A/D converter, and Fig. 5 shows the operation of the example in Fig. 4. FIG. 6 is a characteristic diagram illustrating the operation of the comparator of the example shown in FIG. 4. 1...Sampf hold circuit, 2...Comparator,
3... Reference level generation circuit, 4... Successive approximation register, 5, 6... Timing control circuit.

Claims

[Claims for Utility Model Registration] (1) A comparator that compares the level of an analog signal to be converted into a digital signal with a reference level, a successive approximation register that sequentially stores the output of the comparator, and the successive approximation register. A reference level generation circuit that generates a reference level to be supplied to the comparator in response to an output of a register, and a timing control circuit that generates a clock that drives the reference level generation circuit, the timing control circuit generating a level. A successive approximation type A/D converter characterized in that the clock output during the determination period has a period in which the period becomes longer from the reference level of the upper bits to the reference level of the lower bits. (2) The level determination period is divided into a plurality of sections, the period within each section is the same, and the period of the section on the upper bit side is set shorter than the period of the section on the lower bit side. The successive approximation type A/D converter according to claim 1. (3) Among the above sections, the period of the section on the lower bit side next to the section containing the most significant bit is the shortest, and the period of the section containing the most significant bit is longer, and the period of the section on the lower bit side next to the section containing the most significant bit is the shortest. The successive approximation type A/ according to claim 2, wherein the period is set to gradually increase from the side section.
D converter. (4) The period of several bits lower than the most significant bit is long, the period of the next lower bit is the shortest, and the period is set so that it gradually becomes longer from the lower bit after the bit with the shortest period. The successive approximation type A/ according to claim 1, characterized in that:
D converter.