JPH0164230U - - Google Patents
Info
- Publication number
- JPH0164230U JPH0164230U JP1987157537U JP15753787U JPH0164230U JP H0164230 U JPH0164230 U JP H0164230U JP 1987157537 U JP1987157537 U JP 1987157537U JP 15753787 U JP15753787 U JP 15753787U JP H0164230 U JPH0164230 U JP H0164230U
- Authority
- JP
- Japan
- Prior art keywords
- lower bits
- digital
- adder
- pulse width
- width modulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図は上記実施例におけるパルス幅変調器のブ
ロツク図、第３図は上記実施例における各部の波
形タイムチヤート、第４図は従来のＤ／Ａコンバ
ータの構成図である。
１……Ｄ／Ａコンバータ、２……加算器、３…
…パルス幅変調器、４……パルス発振器、５……
カウンタ、６……比較器。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram of the pulse width modulator in the above embodiment, FIG. 3 is a waveform time chart of each part in the above embodiment, and FIG. 4 is a configuration diagram of a conventional D/A converter. 1...D/A converter, 2...Adder, 3...
...Pulse width modulator, 4...Pulse oscillator, 5...
Counter, 6... Comparator.
Claims (1)
を超える下位ビツトを入力して該下位ビツトの値
に比例したデユーテイのパルス信号を作成するパ
ルス幅変調器、上記デジタルデータの上記下位ビ
ツトを差し引いた残りの上位ビツトに上記パルス
幅変調器の出力を最小位ビツトとして加算する加
算器を有し、該加算器の出力が上記Ｄ／Ａ変換回
路に入力されることを特徴とするデジタル／アナ
ログ変換装置。 A pulse width modulator that inputs the lower bits of digital data that exceed the resolution of the D/A conversion circuit and creates a pulse signal with a duty proportional to the value of the lower bits, and the remainder after subtracting the lower bits of the digital data. A digital/analog conversion device comprising an adder for adding the output of the pulse width modulator as the least significant bit to the most significant bit of the digital/analog converter, the output of the adder being input to the D/A conversion circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157537U JPH0164230U (en) | 1987-10-16 | 1987-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157537U JPH0164230U (en) | 1987-10-16 | 1987-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0164230U true JPH0164230U (en) | 1989-04-25 |
Family
ID=31437065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987157537U Pending JPH0164230U (en) | 1987-10-16 | 1987-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0164230U (en) |
-
1987
- 1987-10-16 JP JP1987157537U patent/JPH0164230U/ja active Pending
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