JPS6429926U - - Google Patents
Info
- Publication number
- JPS6429926U JPS6429926U JP12313187U JP12313187U JPS6429926U JP S6429926 U JPS6429926 U JP S6429926U JP 12313187 U JP12313187 U JP 12313187U JP 12313187 U JP12313187 U JP 12313187U JP S6429926 U JPS6429926 U JP S6429926U
- Authority
- JP
- Japan
- Prior art keywords
- digital data
- bits
- conversion device
- converter
- converting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の第１実施例を示す回路構成図
、第２図は同実施例のＡ／Ｄ変換動作を説明する
ための図、第３図は本考案の第２実施例を示す回
路構成図、第４図は同実施例のＡ／Ｄ変換動作を
説明するための図、第５図は本考案の第３実施例
を示す回路構成図、第６図は同実施例のＡ／Ｄ変
換動作を説明するための図、第７図は従来のＡ／
Ｄ変換装置を示す回路構成図、第８図は第７図の
Ａ／Ｄ変換動作を説明するための図である。
１１……基準電圧発生回路、１２０〜１２８…
…コンパレータ、１３０〜１３８……フリツプフ
ロツプ、１４Ａ〜１４Ｃ……デコーダ、１４１…
…デコード部、１５１〜１５３……フリツプフロ
ツプ。
Fig. 1 is a circuit configuration diagram showing a first embodiment of the present invention, Fig. 2 is a diagram for explaining the A/D conversion operation of the same embodiment, and Fig. 3 shows a second embodiment of the present invention. 4 is a diagram for explaining the A/D conversion operation of the same embodiment, FIG. 5 is a circuit diagram showing the third embodiment of the present invention, and FIG. 6 is a diagram for explaining the A/D conversion operation of the same embodiment. A diagram for explaining the /D conversion operation, FIG. 7 is a diagram for explaining the conventional A/D conversion operation.
FIG. 8 is a circuit configuration diagram showing the D conversion device, and is a diagram for explaining the A/D conversion operation of FIG. 7. 11...Reference voltage generation circuit, 120 to 128 ...
...Comparator, 130 to 138 ...Flip-flop, 14A to 14C...Decoder, 141...
...Decoding section, 15 1 to 15 3 ... flip-flop.
Claims (1)
に変換するＡ／Ｄ変換装置において、アナログ入
力信号が所定のレベル範囲を越えた際に予め設定
した値のデジタルデータを出力する手段を具備し
たことを特徴とするＡ／Ｄ変換装置。 An A/D converter for converting an analog signal into digital data of a predetermined number of bits, characterized by comprising means for outputting digital data of a preset value when the analog input signal exceeds a predetermined level range. A/D conversion device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12313187U JPS6429926U (en) | 1987-08-13 | 1987-08-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12313187U JPS6429926U (en) | 1987-08-13 | 1987-08-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6429926U true JPS6429926U (en) | 1989-02-22 |
Family
ID=31371700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12313187U Pending JPS6429926U (en) | 1987-08-13 | 1987-08-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6429926U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370653A (en) * | 1976-12-07 | 1978-06-23 | Toshiba Corp | Digital output unit |
| JPS5887914A (en) * | 1981-11-18 | 1983-05-25 | Mitsubishi Electric Corp | Output circuit of analog-to-digital conversion |
-
1987
- 1987-08-13 JP JP12313187U patent/JPS6429926U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370653A (en) * | 1976-12-07 | 1978-06-23 | Toshiba Corp | Digital output unit |
| JPS5887914A (en) * | 1981-11-18 | 1983-05-25 | Mitsubishi Electric Corp | Output circuit of analog-to-digital conversion |
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