JPS63181958U - - Google Patents

Info

Publication number
JPS63181958U
JPS63181958U JP7211587U JP7211587U JPS63181958U JP S63181958 U JPS63181958 U JP S63181958U JP 7211587 U JP7211587 U JP 7211587U JP 7211587 U JP7211587 U JP 7211587U JP S63181958 U JPS63181958 U JP S63181958U
Authority
JP
Japan
Prior art keywords
data
generation circuit
trigger
trigger generation
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7211587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7211587U priority Critical patent/JPS63181958U/ja
Publication of JPS63181958U publication Critical patent/JPS63181958U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るトリガ発生回路の一実施
例を示す構成図、第2図は第1図の回路の動作を
説明するためのタイミング図である。第3図は従
来のトリガ発生回路の一例を示す構成図である。 1…アナログ/デイジタル変換器、2…バスバ
ツフア、3…ストレージメモリ、4…アドレスデ
コーダ、5…データセレクタ、6…トリガチヤネ
ル選択回路、7…ラツチ、8…コンパレータ、9
…トリガレベル、10…データバス。
FIG. 1 is a block diagram showing an embodiment of a trigger generation circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1. FIG. 3 is a configuration diagram showing an example of a conventional trigger generation circuit. 1... Analog/digital converter, 2... Bus buffer, 3... Storage memory, 4... Address decoder, 5... Data selector, 6... Trigger channel selection circuit, 7... Latch, 8... Comparator, 9
...Trigger level, 10...Data bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の入力チヤネルとトリガ機能を持つたスト
レージ装置のトリガ発生回路において、選択され
たチヤネルのアナログ/デイジタル変換されたデ
ータをストレージメモリに転送するときに、同時
にデータをラツチすることによりトリガ用のデー
タとするように構成したことを特徴とするトリガ
発生回路。
In the trigger generation circuit of a storage device that has multiple input channels and trigger functions, when transferring the analog/digital converted data of the selected channel to the storage memory, the data for triggering is generated by simultaneously latching the data. A trigger generation circuit characterized in that it is configured to:
JP7211587U 1987-05-14 1987-05-14 Pending JPS63181958U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7211587U JPS63181958U (en) 1987-05-14 1987-05-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7211587U JPS63181958U (en) 1987-05-14 1987-05-14

Publications (1)

Publication Number Publication Date
JPS63181958U true JPS63181958U (en) 1988-11-24

Family

ID=30915284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7211587U Pending JPS63181958U (en) 1987-05-14 1987-05-14

Country Status (1)

Country Link
JP (1) JPS63181958U (en)

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