JPH0267287U - - Google Patents
Info
- Publication number
- JPH0267287U JPH0267287U JP14610688U JP14610688U JPH0267287U JP H0267287 U JPH0267287 U JP H0267287U JP 14610688 U JP14610688 U JP 14610688U JP 14610688 U JP14610688 U JP 14610688U JP H0267287 U JPH0267287 U JP H0267287U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- converter
- signal processing
- selector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図は本考案の実施例であるレーダ信号処理
装置を示す図、第２図は第１図に示す装置の動作
を説明する波形図、第３図は従来から用いられて
いるレーダ信号処理装置を示す図、第４図は第３
図に示す装置の動作を示す波形図である。
図中、１はＡ／Ｄ変換器、２は間引き回路、３
はセレクタ、４は信号処理回路、５は遅延回路、
６は比較回路、７は選択回路、アは受信ビデオ信
号、イはＡ／Ｄ変換器１の出力、ウは選択回路７
の出力を示す。なお、図中同一あるいは相当部分
には同一符号を付してある。
Fig. 1 is a diagram showing a radar signal processing device that is an embodiment of the present invention, Fig. 2 is a waveform diagram explaining the operation of the device shown in Fig. 1, and Fig. 3 is a diagram showing a radar signal processing device used conventionally. A diagram showing the device, Figure 4 is the third
FIG. 3 is a waveform chart showing the operation of the device shown in the figure. In the figure, 1 is an A/D converter, 2 is a thinning circuit, and 3
is a selector, 4 is a signal processing circuit, 5 is a delay circuit,
6 is a comparison circuit, 7 is a selection circuit, A is a received video signal, B is the output of A/D converter 1, C is selection circuit 7
shows the output of In addition, the same reference numerals are given to the same or corresponding parts in the figures.
Claims (1)
／Ｄ変換器、前記Ａ／Ｄ変換器の出力を遅延させ
る遅延回路、遅延回路の出力と前記Ａ／Ｄ変換器
の出力の大小を比較する比較回路、比較回路が発
生する制御信号により、前記Ａ／Ｄ変換回路出力
と遅延回路出力のうち大きい方を選ぶ選択回路、
選択回路出力と前記Ａ／Ｄ変換回路出力を用途に
より切り換えるセレクタ、セレクタの出力の信号
処理を行う信号処理回路を備えたことを特徴とす
るレーダ信号処理装置。 A converting the received video signal into a digital signal
/D converter, a delay circuit that delays the output of the A/D converter, a comparison circuit that compares the output of the delay circuit with the output of the A/D converter, and a control signal generated by the comparison circuit, a selection circuit that selects the larger of the A/D conversion circuit output and the delay circuit output;
A radar signal processing device comprising a selector that switches between a selection circuit output and the A/D conversion circuit output depending on the purpose, and a signal processing circuit that performs signal processing of the output of the selector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14610688U JPH0267287U (en) | 1988-11-09 | 1988-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14610688U JPH0267287U (en) | 1988-11-09 | 1988-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267287U true JPH0267287U (en) | 1990-05-22 |
Family
ID=31415286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14610688U Pending JPH0267287U (en) | 1988-11-09 | 1988-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267287U (en) |
-
1988
- 1988-11-09 JP JP14610688U patent/JPH0267287U/ja active Pending