JPS62201540U - - Google Patents
Info
- Publication number
- JPS62201540U JPS62201540U JP8924486U JP8924486U JPS62201540U JP S62201540 U JPS62201540 U JP S62201540U JP 8924486 U JP8924486 U JP 8924486U JP 8924486 U JP8924486 U JP 8924486U JP S62201540 U JPS62201540 U JP S62201540U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- delay
- detection
- phase shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000010363 phase shift Effects 0.000 claims description 4
- 230000001934 delay Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
Description
第1図は本考案の一実施例を示すブロツク図。
第2図は本考案の一実施例の作用の説明に供する
波形図。第3図はパルス性ノイズ受信のときにお
ける受信機各部のパルス性ノイズの波形図。第4
図は従来例の一例を示す構成図。第5図a〜d、
第6図および第7図は第4図に示した従来例の作
用の説明に供する波形図。第5図eは遅れ移相回
路の特性図。
11……プリエンフアシス回路、12……移相
回路、13……遅延回路、14……スイツチ回路
、15……デイエンフアシス回路、16……ノイ
ズ検出回路、17……ゲートパルス発生回路。
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention. FIG. 3 is a waveform diagram of pulse noise in each part of the receiver when receiving pulse noise. Fourth
The figure is a configuration diagram showing an example of a conventional example. Figure 5 a-d,
6 and 7 are waveform diagrams for explaining the operation of the conventional example shown in FIG. 4. FIG. 5e is a characteristic diagram of the delay phase shift circuit. 11... Pre-emphasis circuit, 12... Phase shift circuit, 13... Delay circuit, 14... Switch circuit, 15... De-emphasis circuit, 16... Noise detection circuit, 17... Gate pulse generation circuit.
Claims (1)
て、検波回路出力を入力としその中の信号成分を
遅延させる移相回路と、前記検波回路出力を前記
遅延とほぼ同一期間遅延させる遅延回路と、外来
パルス性ノイズ検出時に同期して前記遅延の期間
中、検波出力として前記移相回路の出力に代つて
前記遅延回路の出力を切替出力させるスイツチ手
段とを備えたことを特徴とするノイズキヤンセラ
ー。 A noise canceller in an AM receiver, which includes a phase shift circuit that receives the detection circuit output and delays the signal component therein, a delay circuit that delays the detection circuit output by approximately the same period as the delay, and an external pulse A noise canceller comprising a switch means for switching output of the delay circuit as a detection output in place of the output of the phase shift circuit during the delay period in synchronization with noise detection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8924486U JPS62201540U (en) | 1986-06-13 | 1986-06-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8924486U JPS62201540U (en) | 1986-06-13 | 1986-06-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62201540U true JPS62201540U (en) | 1987-12-22 |
Family
ID=30948058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8924486U Pending JPS62201540U (en) | 1986-06-13 | 1986-06-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62201540U (en) |
-
1986
- 1986-06-13 JP JP8924486U patent/JPS62201540U/ja active Pending
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