JPS62117800U

JPS62117800U -

Info

Publication number: JPS62117800U
Application number: JP413486U
Authority: JP
Priority date: 1986-01-16
Filing date: 1986-01-16
Publication date: 1987-07-27
Also published as: JPH0419680Y2

Description

[Brief explanation of the drawing]

第１図は本考案のサンプルホールド制御回路の
一実施例を示す構成図、第２図はその動作状態を
示す波形図、第３図は従来のサンプルホールド制
御回路の一例を示す構成図、第４図はその動作状
態を示す波形図である。１……サンプルホールド回路、２……アナログ
・デイジタル変換回路、３……クロツク発生回路
、４……タイミング回路、５……ゲート回路、６
……論理回路。 FIG. 1 is a block diagram showing an embodiment of the sample-and-hold control circuit of the present invention, FIG. 2 is a waveform diagram showing its operating state, and FIG. 3 is a block diagram showing an example of a conventional sample-and-hold control circuit. FIG. 4 is a waveform diagram showing its operating state. DESCRIPTION OF SYMBOLS 1... Sample hold circuit, 2... Analog-digital conversion circuit, 3... Clock generation circuit, 4... Timing circuit, 5... Gate circuit, 6
...Logic circuit.

Claims

[Scope of utility model registration request]

In the sample-and-hold control circuit that applies a sample/hold signal to the sample-and-hold circuit to control its sampling operation, there is a clock generation circuit that generates a reference clock, and a sample-and-hold signal during actual operation based on this clock. a gate circuit that supplies the clock to the timing circuit in response to a sampling command; and a sample-and-hold circuit that uses the clock as a temporary sample-and-hold signal when the sample-and-hold signal is not generated. A sample and hold control circuit comprising a logic circuit that supplies data to