JPS647352U - - Google Patents
Info
- Publication number
- JPS647352U JPS647352U JP10072987U JP10072987U JPS647352U JP S647352 U JPS647352 U JP S647352U JP 10072987 U JP10072987 U JP 10072987U JP 10072987 U JP10072987 U JP 10072987U JP S647352 U JPS647352 U JP S647352U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- trigger signal
- storing digital
- digital data
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は、この考案に係る装置の一実施例とし
ての要部構成図、第２図は、メモリにおけるアド
レス構成の一例を示す説明図、第３図は、この考
案における基本的な出力作用を説明するためのフ
ローチヤート、第４図は、メモリのアドレス構成
がリングバツフアである場合の説明図、第５図は
、メモリのアドレス構成が第４図に示すリングバ
ツフアである場合の出力作用を説明するためのフ
ローチヤートである。
１１……トリガ発生手段、１３……演算制御手
段、１５……Ａ／Ｄ変換手段、１７……メモリ、
１９……出力手段、２１……メモリバツクアツプ
手段、２３……電源監視手段。
Fig. 1 is a diagram showing the main part of an embodiment of the device according to this invention, Fig. 2 is an explanatory diagram showing an example of address structure in memory, and Fig. 3 is a basic output function in this invention. FIG. 4 is an explanatory diagram for the case where the address structure of the memory is a ring buffer, and FIG. 5 is a flowchart for explaining the output operation when the address structure of the memory is the ring buffer shown in FIG. This is a flowchart for 11...Trigger generation means, 13...Arithmetic control means, 15...A/D conversion means, 17...Memory,
19...Output means, 21...Memory backup means, 23...Power monitoring means.
Claims (1)
バツクアツプ手段を有するメモリと、トリガ信号
を受け取つて前記Ａ／Ｄ変換手段を動作させ、デ
イジタルデータを前記メモリに記憶させる演算制
御手段と、前記メモリに記憶されたデータを読み
込んでこれを出力する出力手段とを備え、前記メ
モリにデイジタルデータを記憶させる際、トリガ
信号によつてセツトされるデータを同時に記憶さ
せるようにしたことを特徴とする波形記憶装置。 a memory having a trigger generation means, an A/D conversion means, and a memory backup means; an arithmetic control means for receiving a trigger signal to operate the A/D conversion means and storing digital data in the memory; It is characterized by comprising an output means for reading data stored in a memory and outputting it, and when storing digital data in the memory, data set by a trigger signal is stored at the same time. Waveform storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10072987U JPS647352U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10072987U JPS647352U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647352U true JPS647352U (en) | 1989-01-17 |
Family
ID=31329067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10072987U Pending JPS647352U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647352U (en) |
-
1987
- 1987-06-30 JP JP10072987U patent/JPS647352U/ja active Pending
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