JPS63155527U - - Google Patents
Info
- Publication number
- JPS63155527U JPS63155527U JP4776587U JP4776587U JPS63155527U JP S63155527 U JPS63155527 U JP S63155527U JP 4776587 U JP4776587 U JP 4776587U JP 4776587 U JP4776587 U JP 4776587U JP S63155527 U JPS63155527 U JP S63155527U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- output
- auto clear
- data
- clear signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す回路構成図
、第２図は同実施例の動作を説明するためのフロ
ーチヤート、第３図は従来のオートクリア回路の
一例を示す回路構成図、第４は同オートクリア回
路の動作を説明するためのフローチヤートである
。
１１…電源スイツチ、１２，１８…フリツプフ
ロツプ、１４…クロツク発生器、１５…ＣＲ回路
、１６，２４…ナンドゲート、１７…アドレスカ
ウンタ、１９…ＲＡＭ、２１１〜２１ｎ…アンド
ゲート、２３１〜２３ｎ…オアゲート。
FIG. 1 is a circuit configuration diagram showing an embodiment of this invention, FIG. 2 is a flowchart for explaining the operation of the same embodiment, and FIG. 3 is a circuit configuration diagram showing an example of a conventional auto clear circuit. The fourth is a flowchart for explaining the operation of the auto clear circuit. 11... Power switch, 12, 18... Flip-flop, 14... Clock generator, 15... CR circuit, 16, 24... NAND gate, 17... Address counter, 19... RAM, 211-21n... AND gate, 231-23n... OR gate.
Claims (1)
電源検出手段の出力によりリセツトされるアドレ
スカウンタと、このアドレスカウンタによりアド
レスされる記憶手段と、上記アドレスカウンタを
インクリメントするとともに対応する記憶手段の
アドレスに「０」データを書込む「０」データ書
込み手段と、上記電源検出手段の出力によりオー
トクリア信号を出力するとともに上記記憶手段の
すべてに「０」データが書込まれたところで上記
オートクリア信号をリセツトするオートクリア信
号発生手段とを具備したことを特徴とするオート
クリア回路。 a power supply detection means for detecting the rise of the power supply; an address counter that is reset by the output of the power supply detection means; a storage means addressed by the address counter; The "0" data writing means for writing "0" data and the output of the power supply detection means output an auto clear signal, and when the "0" data has been written to all of the storage means, the auto clear signal is output. An auto clear circuit characterized by comprising an auto clear signal generating means for resetting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4776587U JPS63155527U (en) | 1987-03-31 | 1987-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4776587U JPS63155527U (en) | 1987-03-31 | 1987-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155527U true JPS63155527U (en) | 1988-10-12 |
Family
ID=30868680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4776587U Pending JPS63155527U (en) | 1987-03-31 | 1987-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155527U (en) |
-
1987
- 1987-03-31 JP JP4776587U patent/JPS63155527U/ja active Pending
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