JPH03127947U - - Google Patents
Info
- Publication number
- JPH03127947U JPH03127947U JP3697490U JP3697490U JPH03127947U JP H03127947 U JPH03127947 U JP H03127947U JP 3697490 U JP3697490 U JP 3697490U JP 3697490 U JP3697490 U JP 3697490U JP H03127947 U JPH03127947 U JP H03127947U
- Authority
- JP
- Japan
- Prior art keywords
- address
- generating
- external memory
- storage means
- address generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の実施例の構成を示すブロツク
図、第２図は本考案の一実施例の動作を示すタイ
ムチヤート、第３図は従来例の動作を示すタイム
チヤートである。
主要部分の符号の説明、１…メモリ素子、１０
…メモリ部、１１…制御部、１２…制御信号発生
部、１３…外部メモリアドレス発生部、１４…内
部メモリアドレス発生部、１５〜１７…切換え回
路。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of an embodiment of the present invention, and FIG. 3 is a time chart showing the operation of a conventional example. Explanation of symbols of main parts, 1...Memory element, 10
...Memory section, 11...Control section, 12...Control signal generation section, 13...External memory address generation section, 14...Internal memory address generation section, 15-17...Switching circuit.
Claims (1)
記憶手段へのアドレスを生成する第１のアドレス
生成手段と、外部メモリへのアドレスを生成する
第２のアドレス生成手段と、前記第２のアドレス
生成手段で生成されたアドレスによる前記外部メ
モリからの読出し動作と、前記読出し動作により
読出された前記外部メモリからのデータの前記第
１のアドレス生成手段で生成されたアドレスによ
る前記記憶手段への書込み動作とを同時に行うよ
う制御する制御手段とを内蔵したことを特徴とす
るメモリ素子。 a storage means for storing data from the outside; a first address generation means for generating an address to the storage means; a second address generation means for generating an address to the external memory; and the second address generation means. a read operation from the external memory using an address generated by the means; and a write operation of data read from the external memory by the read operation to the storage means using an address generated by the first address generating means. What is claimed is: 1. A memory device characterized by having a built-in control means for controlling the operations to be performed at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3697490U JPH03127947U (en) | 1990-04-05 | 1990-04-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3697490U JPH03127947U (en) | 1990-04-05 | 1990-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03127947U true JPH03127947U (en) | 1991-12-24 |
Family
ID=31543676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3697490U Pending JPH03127947U (en) | 1990-04-05 | 1990-04-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03127947U (en) |
-
1990
- 1990-04-05 JP JP3697490U patent/JPH03127947U/ja active Pending
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