JPS5999514U - signal generator - Google Patents

signal generator

Info

Publication number
JPS5999514U
JPS5999514U JP19507382U JP19507382U JPS5999514U JP S5999514 U JPS5999514 U JP S5999514U JP 19507382 U JP19507382 U JP 19507382U JP 19507382 U JP19507382 U JP 19507382U JP S5999514 U JPS5999514 U JP S5999514U
Authority
JP
Japan
Prior art keywords
arithmetic unit
signal
memory
signal generator
analog signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19507382U
Other languages
Japanese (ja)
Inventor
原田 敏正
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP19507382U priority Critical patent/JPS5999514U/en
Publication of JPS5999514U publication Critical patent/JPS5999514U/en
Pending legal-status Critical Current

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  • Recording Measured Values (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の信号発生方法を示すブロック図、第2
図は本考案による信号発生装置の一実施λ/− 例を示すブロック図、第3図は第2図の動作を表オ〕す
流れ図である。
Figure 1 is a block diagram showing a conventional signal generation method;
The figure is a block diagram showing an example of the implementation of the signal generator according to the present invention, and FIG. 3 is a flowchart showing the operation of FIG. 2.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 出力信号のホールド時間及び信号の周期を設定する第1
演算器と、ブ冶グラムによる数値演算を行ない信号を作
成する第2演算器と該演算結果を順次メモリに格納する
第3演算器と、メモリの内−容を順次読み出す第4演算
器と読み出されたメモリの値をアナログ信号に変換する
D/A変換器と、該アナログ信号を一定時間保持するホ
ールダとにより構成される信号発生装置。
The first step is to set the output signal hold time and signal period.
an arithmetic unit, a second arithmetic unit that performs numerical calculations based on programming and creates signals, a third arithmetic unit that sequentially stores the calculation results in a memory, and a fourth arithmetic unit that sequentially reads out the contents of the memory. A signal generating device that includes a D/A converter that converts the output memory value into an analog signal, and a holder that holds the analog signal for a certain period of time.
JP19507382U 1982-12-24 1982-12-24 signal generator Pending JPS5999514U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19507382U JPS5999514U (en) 1982-12-24 1982-12-24 signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19507382U JPS5999514U (en) 1982-12-24 1982-12-24 signal generator

Publications (1)

Publication Number Publication Date
JPS5999514U true JPS5999514U (en) 1984-07-05

Family

ID=30419092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19507382U Pending JPS5999514U (en) 1982-12-24 1982-12-24 signal generator

Country Status (1)

Country Link
JP (1) JPS5999514U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175304A (en) * 1982-04-07 1983-10-14 Teac Co Digital signal generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175304A (en) * 1982-04-07 1983-10-14 Teac Co Digital signal generator

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