JPS61174237U - - Google Patents
Info
- Publication number
- JPS61174237U JPS61174237U JP5640485U JP5640485U JPS61174237U JP S61174237 U JPS61174237 U JP S61174237U JP 5640485 U JP5640485 U JP 5640485U JP 5640485 U JP5640485 U JP 5640485U JP S61174237 U JPS61174237 U JP S61174237U
- Authority
- JP
- Japan
- Prior art keywords
- reference signal
- start level
- comparison start
- level
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims 4
- 230000007423 decrease Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は、本考案の実施例の逐次比較型Ａ／Ｄ
変換器の回路図、第２図ａ，ｂは波形図、第３図
は従来例の波形図である。
１……比較器、２……基準信号発生回路。
FIG. 1 shows a successive approximation type A/D according to an embodiment of the present invention.
A circuit diagram of the converter, FIGS. 2a and 2b are waveform diagrams, and FIG. 3 is a waveform diagram of a conventional example. 1...Comparator, 2...Reference signal generation circuit.
Claims (1)
記基準信号を出力する基準信号発生回路とを備え
、前記基準信号発生回路が、Ａ／Ｄ変換終了時の
信号レベルを次回のＡ／Ｄ変換時の比較開始レベ
ルとして記憶し、次回のＡ／Ｄ変換時にこの比較
開始レベルと新たな入力信号レベルとを比較し、
比較開始レベルが新たな入力信号よりも小さいと
きには、その比較開始レベルから所定の勾配で上
昇する基準信号を出力し、前記比較開始レベルが
新たな入力信号よりも大きいときには、その比較
開始レベルから所定の勾配で下降する基準信号を
出力するように構成してなる遂次比較型Ａ／Ｄ変
換器。 The reference signal generation circuit includes a comparator that compares an input signal and a reference signal, and a reference signal generation circuit that outputs the reference signal, and the reference signal generation circuit uses the signal level at the end of the A/D conversion to be used for the next A/D conversion. This comparison start level is stored as a comparison start level at the time of the A/D conversion, and this comparison start level is compared with a new input signal level at the next A/D conversion.
When the comparison start level is smaller than the new input signal, a reference signal that rises at a predetermined slope from the comparison start level is output, and when the comparison start level is higher than the new input signal, the reference signal is outputted from the comparison start level at a predetermined slope. A sequential comparison type A/D converter configured to output a reference signal that decreases at a slope of .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5640485U JPS61174237U (en) | 1985-04-15 | 1985-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5640485U JPS61174237U (en) | 1985-04-15 | 1985-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174237U true JPS61174237U (en) | 1986-10-30 |
Family
ID=30579965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5640485U Pending JPS61174237U (en) | 1985-04-15 | 1985-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174237U (en) |
-
1985
- 1985-04-15 JP JP5640485U patent/JPS61174237U/ja active Pending
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