JPH01139632U - - Google Patents
Info
- Publication number
- JPH01139632U JPH01139632U JP3444588U JP3444588U JPH01139632U JP H01139632 U JPH01139632 U JP H01139632U JP 3444588 U JP3444588 U JP 3444588U JP 3444588 U JP3444588 U JP 3444588U JP H01139632 U JPH01139632 U JP H01139632U
- Authority
- JP
- Japan
- Prior art keywords
- pulse width
- timing
- control circuit
- floating point
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図は本考案の原理構成を示すブロツク図、
第2図は本考案の一実施例を示すブロツク図、第
3図は本考案の一実施例における分解能を説明す
るための出力波形図、第4図は従来のパルス幅変
調回路構成を示すブロツク図、第5図は浮動小数
点データの一形式を示すデータフオーマツト図、
第6図は従来のパルス幅変調回路の動作を説明す
るためのタイミングチヤートである。
10……パルス幅変調回路、20……PWM駆
動部、23……データラツチ部、24……カウン
タ、26……クロツク部、27……フリツプフロ
ツプ、28……タイミング制御回路、30……D
/Aコンバータ、40……AM駆動部、43……
トランジスタ、60……LPF。
Figure 1 is a block diagram showing the principle configuration of the present invention.
Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is an output waveform diagram for explaining the resolution in an embodiment of the present invention, and Fig. 4 is a block diagram showing the configuration of a conventional pulse width modulation circuit. Figure 5 is a data format diagram showing one format of floating point data.
FIG. 6 is a timing chart for explaining the operation of a conventional pulse width modulation circuit. 10...Pulse width modulation circuit, 20...PWM drive section, 23...Data latch section, 24...Counter, 26...Clock section, 27...Flip-flop, 28...Timing control circuit, 30...D
/A converter, 40...AM drive unit, 43...
Transistor, 60...LPF.
Claims (1)
ルス幅データに変調するパルス幅変調回路におい
て、 前記浮動小数点データの浮号ビツトsおよび仮
数部fをパルス幅変調するPWM駆動部20と、 前記浮動小数点データの指数部eをアナログ変
換するD/Aコンバータ30と、 前記PWM駆動部20からのパルス幅データを
前記D/Aコンバータ30からのアナログ出力に
よつて振幅変調するAM駆動部40とからなるこ
とを特徴とするパルス幅変調回路。 2 前記PWM駆動部20が前記浮動小数点デー
タ用のタイミング制御回路28を有してなり、該
タイミング制御回路28は、前記符号ビツトsお
よび仮数部fをデータラツチ部23にプリセツト
するタイミングと、前記指数部eを前記D/Aコ
ンバータ40にプリセツトするタイミングとを同
時に制御する請求項1記載のタイミング制御回路
。[Claims for Utility Model Registration] 1. In a pulse width modulation circuit that modulates pulse-coded floating point data into pulse width data, a PWM drive that pulse width modulates the floating bit s and mantissa part f of the floating point data. a D/A converter 30 that converts the exponent part e of the floating point data into analog; and amplitude modulates the pulse width data from the PWM drive section 20 using the analog output from the D/A converter 30. A pulse width modulation circuit comprising an AM drive section 40. 2. The PWM drive unit 20 includes a timing control circuit 28 for the floating point data, and the timing control circuit 28 controls the timing for presetting the sign bit s and the mantissa part f in the data latch unit 23, and the timing for presetting the exponent. 2. The timing control circuit according to claim 1, wherein the timing control circuit controls the timing at which the section e is preset in the D/A converter 40 at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3444588U JPH01139632U (en) | 1988-03-17 | 1988-03-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3444588U JPH01139632U (en) | 1988-03-17 | 1988-03-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01139632U true JPH01139632U (en) | 1989-09-25 |
Family
ID=31261153
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3444588U Pending JPH01139632U (en) | 1988-03-17 | 1988-03-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01139632U (en) |
-
1988
- 1988-03-17 JP JP3444588U patent/JPH01139632U/ja active Pending
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