JPS6259870U - - Google Patents
Info
- Publication number
- JPS6259870U JPS6259870U JP12939186U JP12939186U JPS6259870U JP S6259870 U JPS6259870 U JP S6259870U JP 12939186 U JP12939186 U JP 12939186U JP 12939186 U JP12939186 U JP 12939186U JP S6259870 U JPS6259870 U JP S6259870U
- Authority
- JP
- Japan
- Prior art keywords
- waveform
- holding buffers
- converter
- response
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 5
- 238000005070 sampling Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の波形記憶装置の原理を説明す
るブロツク図、第２図は本考案の波形記憶装置の
動作の説明図、第３図は本考案の波形記憶装置の
要部の一実施例の詳細ブロツク図を示す。
１２はＡ／Ｄ変換器、４４は波形メモリ、６２
，６４は保持バツフア、６６，６８はデジタル比
較器、７０は制御手段を示す。
Fig. 1 is a block diagram explaining the principle of the waveform storage device of the present invention, Fig. 2 is an explanatory diagram of the operation of the waveform storage device of the invention, and Fig. 3 is an implementation of the main part of the waveform storage device of the invention. A detailed block diagram of an example is shown. 12 is an A/D converter, 44 is a waveform memory, 62
, 64 are holding buffers, 66 and 68 are digital comparators, and 70 is a control means.
Claims (1)
ツクパルスに応じてデジタル信号に変換するＡ／
Ｄ変換器と、該Ａ／Ｄ変換器の出力側に接続され
た第１及び第２保持バツフアと、該両保持バツフ
アの出力データを上記サンプリング・クロツクパ
ルス以下の可変記録クロツクパルスに応じて記憶
する波形メモリと、上記第１及び第２保持バツフ
アの入出力データを比較するデジタル比較器を含
む制御手段とを具え、該制御手段は上記記録クロ
ツクパルス間に得た上記Ａ／Ｄ変換器からの複数
の波形データのうち順次最小及び最大値のみを上
記第１及び第２保持バツフアに保持する包絡線モ
ードと瞬時波形データを保持するノーマルモード
で選択動作させることを特徴とする波形記憶装置
。 An analog converter that converts an input analog signal into a digital signal in response to high-speed sampling clock pulses.
A D converter, first and second holding buffers connected to the output side of the A/D converter, and a waveform for storing output data of both holding buffers in response to a variable recording clock pulse that is equal to or less than the sampling clock pulse. control means including a memory and a digital comparator for comparing input and output data of the first and second holding buffers; A waveform storage device selectively operated in an envelope mode in which only the minimum and maximum values of the waveform data are sequentially held in the first and second holding buffers, and a normal mode in which instantaneous waveform data is held.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12939186U JPS6259870U (en) | 1986-08-25 | 1986-08-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12939186U JPS6259870U (en) | 1986-08-25 | 1986-08-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6259870U true JPS6259870U (en) | 1987-04-14 |
Family
ID=31025922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12939186U Pending JPS6259870U (en) | 1986-08-25 | 1986-08-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6259870U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52101082A (en) * | 1975-12-31 | 1977-08-24 | Philips Nv | Electrical signal extraction and storage device |
-
1986
- 1986-08-25 JP JP12939186U patent/JPS6259870U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52101082A (en) * | 1975-12-31 | 1977-08-24 | Philips Nv | Electrical signal extraction and storage device |
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