JPH0415070U - - Google Patents
Info
- Publication number
- JPH0415070U JPH0415070U JP5297590U JP5297590U JPH0415070U JP H0415070 U JPH0415070 U JP H0415070U JP 5297590 U JP5297590 U JP 5297590U JP 5297590 U JP5297590 U JP 5297590U JP H0415070 U JPH0415070 U JP H0415070U
- Authority
- JP
- Japan
- Prior art keywords
- data collection
- collection period
- digital oscilloscope
- waveform
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 2
- 238000013480 data collection Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Description
第1図は本考案の一実施例のブロツク図、第2
図は従来技術の一実施例を示すブロツク図である
。
1……アツテネータ、2……プリアンプ、3…
…A/D変換器、4……トリガ回路、5……オー
トトリガカウンタ、6……サンプリングカウンタ
、7……書込み/読出し制御回路、8……クロツ
ク発生回路、9……波形メモリ、10……I/O
ポート、11……μCPU、12……ROM、1
3……RAM、14……トリガイネーブルカウン
タ。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram showing an embodiment of the prior art. 1...Attenuator, 2...Preamplifier, 3...
...A/D converter, 4...Trigger circuit, 5...Auto trigger counter, 6...Sampling counter, 7...Write/read control circuit, 8...Clock generation circuit, 9...Waveform memory, 10... …I/O
Port, 11...μCPU, 12...ROM, 1
3...RAM, 14...Trigger enable counter.
Claims (1)
ル記録するデイジタルオシロスコープにおいて、
入力信号をサンプリングして波形データとして波
形メモリに格納するデータ収集期間中、サンプリ
ングと非同期なマイクロプロセツサの動作を停止
し、データ収集期間終了後、再起動することを特
徴としたデイジタルオシロスコープ。 In a digital oscilloscope, which converts the input signal to be observed and records it digitally,
A digital oscilloscope characterized by stopping the operation of a microprocessor that is asynchronous to sampling during a data collection period in which input signals are sampled and stored as waveform data in a waveform memory, and restarting after the data collection period ends.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5297590U JPH0415070U (en) | 1990-05-23 | 1990-05-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5297590U JPH0415070U (en) | 1990-05-23 | 1990-05-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0415070U true JPH0415070U (en) | 1992-02-06 |
Family
ID=31573752
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5297590U Pending JPH0415070U (en) | 1990-05-23 | 1990-05-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0415070U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6458044A (en) * | 1987-08-28 | 1989-03-06 | Nec Corp | Microcomputer incorporating a/d and d/a converters |
JPS6458043A (en) * | 1987-08-28 | 1989-03-06 | Nec Corp | Microcomputer incorporating a/d and d/a converters |
JPH01177630A (en) * | 1988-01-08 | 1989-07-13 | Hitachi Constr Mach Co Ltd | Microcomputer device |
-
1990
- 1990-05-23 JP JP5297590U patent/JPH0415070U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6458044A (en) * | 1987-08-28 | 1989-03-06 | Nec Corp | Microcomputer incorporating a/d and d/a converters |
JPS6458043A (en) * | 1987-08-28 | 1989-03-06 | Nec Corp | Microcomputer incorporating a/d and d/a converters |
JPH01177630A (en) * | 1988-01-08 | 1989-07-13 | Hitachi Constr Mach Co Ltd | Microcomputer device |
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