JPS62110759U - - Google Patents
Info
- Publication number
- JPS62110759U JPS62110759U JP20128985U JP20128985U JPS62110759U JP S62110759 U JPS62110759 U JP S62110759U JP 20128985 U JP20128985 U JP 20128985U JP 20128985 U JP20128985 U JP 20128985U JP S62110759 U JPS62110759 U JP S62110759U
- Authority
- JP
- Japan
- Prior art keywords
- hold circuit
- sample hold
- converter
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は、本考案の実施例、第２図は、その動
作説明図、第３図は、本考案の他の実施例、第４
図は、その動作説明図、第５図は、従来のＰＣＭ
記録再生装置、第６図は、その動作説明図である
。
１２……ＤＡコンバータ、１３……第１のサン
プルホールド回路、１９……第３のサンプルホー
ルド回路、２０……第２のサンプルホールド回路
。
FIG. 1 is an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is another embodiment of the present invention, and FIG.
The figure is an explanatory diagram of its operation, and Fig. 5 is a conventional PCM.
FIG. 6 is an explanatory diagram of its operation. 12...DA converter, 13...1st sample hold circuit, 19...3rd sample hold circuit, 20...2nd sample hold circuit.
Claims (1)
力されるＤＡコンバータ１２ ｂ 前記ＤＡコンバータの出力が入力される第１
のサンプルホールド回路１３ ｃ 前記ＤＡコンバータの出力が入力される第２
のサンプルホールド回路２０ ｄ 前記第１のサンプルホールド回路の出力が入
力される第３のサンプルホールド回路１９ ｅ 前記第１のサンプルホールド回路に加えられ
る第１のサンプリングパルス ｆ 前記第２と第３のサンプルホールド回路に加
えられる第２のサンプリングパルス 以上の各項を具備することを特徴とするデイジ
タル信号の再生回路。[Claims for Utility Model Registration] a. A DA converter 12 into which the digital signal extracted from the recording medium is input; b. A first converter into which the output of the DA converter is input.
a sample hold circuit 13c; a second sample hold circuit 13c into which the output of the DA converter is input
A sample hold circuit 20 d A third sample hold circuit 19 into which the output of the first sample hold circuit is input e A first sampling pulse f applied to the first sample hold circuit a second sampling pulse applied to the sample-and-hold circuit; A digital signal reproducing circuit characterized by comprising each of the above items.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20128985U JPS62110759U (en) | 1985-12-26 | 1985-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20128985U JPS62110759U (en) | 1985-12-26 | 1985-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62110759U true JPS62110759U (en) | 1987-07-15 |
Family
ID=31164600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20128985U Pending JPS62110759U (en) | 1985-12-26 | 1985-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62110759U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60117450A (en) * | 1983-11-29 | 1985-06-24 | Akai Electric Co Ltd | Circuit for separating reproduced signal into left and right channel signals in digital audio reproducing device |
-
1985
- 1985-12-26 JP JP20128985U patent/JPS62110759U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60117450A (en) * | 1983-11-29 | 1985-06-24 | Akai Electric Co Ltd | Circuit for separating reproduced signal into left and right channel signals in digital audio reproducing device |
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