JPS6454428U - - Google Patents
Info
- Publication number
- JPS6454428U JPS6454428U JP14890787U JP14890787U JPS6454428U JP S6454428 U JPS6454428 U JP S6454428U JP 14890787 U JP14890787 U JP 14890787U JP 14890787 U JP14890787 U JP 14890787U JP S6454428 U JPS6454428 U JP S6454428U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- parallel
- analog
- converts
- combination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案に係るＡ／Ｄ変換器の一実施
例を示すブロツク回路図、第２図は同実施例の動
作を説明するためのタイミング図である。
１１……Ｓ／Ｈ回路、１２……Ａ／Ｄ変換回路
、１３……タイミング発生回路、１４……データ
変換回路、Ｐ１〜ＰＮ……タイミングパルス。
FIG. 1 is a block circuit diagram showing an embodiment of an A/D converter according to this invention, and FIG. 2 is a timing diagram for explaining the operation of the embodiment. 11...S/H circuit, 12...A/D conversion circuit, 13...timing generation circuit, 14...data conversion circuit, P1-PN...timing pulse.
Claims (1)
ホールド回路及びこのサンプルホールド回路のホ
ールド電圧をデジタルデータに変換するアナログ
／デジタル変換回路の組合わせを複数個並列に接
続してなる並列回路と、この並列回路の各組合わ
せを巡回的に位相をずらして動作させるタイミン
グ発生回路と、前記各組合わせの出力データを時
系列に変換するデータ変換回路とを具備するアナ
ログ／デジタル変換器。 A parallel circuit formed by connecting in parallel a plurality of combinations of a sample hold circuit that samples and holds an analog signal and an analog/digital conversion circuit that converts the hold voltage of this sample hold circuit into digital data, and each set of these parallel circuits. An analog/digital converter comprising: a timing generation circuit that operates the combination by cyclically shifting the phase; and a data conversion circuit that converts the output data of each combination into time series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890787U JPS6454428U (en) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890787U JPS6454428U (en) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6454428U true JPS6454428U (en) | 1989-04-04 |
Family
ID=31420649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14890787U Pending JPS6454428U (en) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6454428U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5810921A (en) * | 1981-07-14 | 1983-01-21 | Hitachi Ltd | Analog-to-digital converter |
-
1987
- 1987-09-29 JP JP14890787U patent/JPS6454428U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5810921A (en) * | 1981-07-14 | 1983-01-21 | Hitachi Ltd | Analog-to-digital converter |