JPH0242300U

JPH0242300U -

Info

Publication number: JPH0242300U
Application number: JP11987988U
Authority: JP
Priority date: 1988-09-14
Filing date: 1988-09-14
Publication date: 1990-03-23

Description

[Brief explanation of the drawing]

第１図は本考案に係る同時サンプリング回路の
一実施例を示す図、第２図は第１図回路のタイム
チヤート、第３図は従来例のタイムチヤート、第
４図は従来例を示す図である。１……第１サンプルホールダ群、２……第２サ
ンプルホールダ群、３……マルチプレクサ、５…
…タイミング制御回路。 Fig. 1 is a diagram showing an embodiment of the simultaneous sampling circuit according to the present invention, Fig. 2 is a time chart of the circuit shown in Fig. 1, Fig. 3 is a time chart of a conventional example, and Fig. 4 is a diagram showing a conventional example. It is. 1...First sample holder group, 2...Second sample holder group, 3...Multiplexer, 5...
...Timing control circuit.

Claims

[Claims for Utility Model Registration] A device that simultaneously captures n analog signals into a plurality of sample and hold circuits and sequentially reads out the contents of each sample and hold circuit, which has n sample and hold circuits, and A first sample holder group that introduces analog signals into n sample and hold circuits {S/H(1) to S/H(n)}, and n sample and hold circuits, each of which introduces the n analog signals a second sample holder group that introduces each of mode, and a timing control circuit that controls the second sample holder group to be in the hold mode while the first sample holder group is in the sampling mode.