JPS63143963U - - Google Patents

Info

Publication number
JPS63143963U
JPS63143963U JP3687487U JP3687487U JPS63143963U JP S63143963 U JPS63143963 U JP S63143963U JP 3687487 U JP3687487 U JP 3687487U JP 3687487 U JP3687487 U JP 3687487U JP S63143963 U JPS63143963 U JP S63143963U
Authority
JP
Japan
Prior art keywords
channel
channel selection
scan controller
selection circuit
selection signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3687487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3687487U priority Critical patent/JPS63143963U/ja
Publication of JPS63143963U publication Critical patent/JPS63143963U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は実施例におけるチヤンネルデータの振分け例
を示すデータサイクル図、第3図は実施例におけ
る他のデータサイクル図、第4図は従来の回路図
、第5図は従来のデータサイクル図である。 1…データバツフア、2…D/Aコンバータ、
,3…サンプルホールド回路、4,4
…バツフア、5,6…チヤンネルスキヤンコント
ローラ、7…クロツク発生器、8…カウンタ、9
…チヤンネル選択回路、10…設定器。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
FIG. 3 is a data cycle diagram showing an example of channel data distribution in the embodiment, FIG. 3 is another data cycle diagram in the embodiment, FIG. 4 is a conventional circuit diagram, and FIG. 5 is a conventional data cycle diagram. 1...Data buffer, 2...D/A converter,
3 1 , 3 n ...sample hold circuit, 4 1 , 4 n
...Buffer, 5, 6...Channel scan controller, 7...Clock generator, 8...Counter, 9
... Channel selection circuit, 10... Setting device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力データを時分割で複数のチヤンネルとして
入出力するチヤンネルスキヤンコントローラにお
いて、チヤンネル選択信号を発生するチヤンネル
選択回路と、このチヤンネル選択回路の選択信号
パターンを切換設定する設定器とを備えたことを
特徴とするチヤンネルスキヤンコントローラ。
A channel scan controller that inputs and outputs input data as multiple channels in a time-sharing manner, comprising a channel selection circuit that generates a channel selection signal and a setting device that switches and sets the selection signal pattern of the channel selection circuit. channel scan controller.
JP3687487U 1987-03-13 1987-03-13 Pending JPS63143963U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3687487U JPS63143963U (en) 1987-03-13 1987-03-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3687487U JPS63143963U (en) 1987-03-13 1987-03-13

Publications (1)

Publication Number Publication Date
JPS63143963U true JPS63143963U (en) 1988-09-21

Family

ID=30847684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3687487U Pending JPS63143963U (en) 1987-03-13 1987-03-13

Country Status (1)

Country Link
JP (1) JPS63143963U (en)

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