JPH02101632U - - Google Patents
Info
- Publication number
- JPH02101632U JPH02101632U JP1006889U JP1006889U JPH02101632U JP H02101632 U JPH02101632 U JP H02101632U JP 1006889 U JP1006889 U JP 1006889U JP 1006889 U JP1006889 U JP 1006889U JP H02101632 U JPH02101632 U JP H02101632U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- analog converter
- signal
- analog
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例にかかるデイジタル
アナログ変換装置を示す回路図、第２図は第１図
の回路図の動作を説明するためのタイムチヤート
である。
１……中央演算処理装置（ＣＰＵ）、２……Ｄ
／Ａ変換器、３……第１の入力手段、４……第２
の入力手段、Ｑ１１，Ｑ２１……スイツチ手段を
構成するトランジスター、Ｈ１，Ｈ２……信号ホ
ールド手段。
FIG. 1 is a circuit diagram showing a digital-to-analog converter according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the circuit diagram of FIG. 1. 1...Central processing unit (CPU), 2...D
/A converter, 3...first input means, 4...second
input means, Q 11 , Q 21 . . . transistors constituting switch means, H 1 , H 2 . . . signal hold means.
Claims (1)
号をアナログ信号に変換するデイジタルアナログ
変換器と、 前記デイジタル信号に複数の情報を含ませるた
めに用いた時分割信号に同期して前記デイジタル
アナログ変換器のアナログ出力を複数の出力端に
交互に接続するスイツチ手段と、 前記複数の出力端が前記デイジタルアナログ変
換器のアナログ出力に接続されていない間は、そ
の前に接続されていた際の出力値を維持するよう
にした信号ホールド手段とを有するデイジタルア
ナログ変換装置。[Claims for Utility Model Registration] A digital-to-analog converter that converts a digital signal containing multiple pieces of information in a time-sharing manner into an analog signal, and a time-sharing signal used to include multiple pieces of information in the digital signal. switch means for alternately connecting the analog outputs of said digital-to-analog converter to a plurality of output terminals in synchronization with said digital-to-analog converter; A digital-to-analog converter having a signal hold means configured to maintain an output value when connected to the digital-to-analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1006889U JPH02101632U (en) | 1989-01-31 | 1989-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1006889U JPH02101632U (en) | 1989-01-31 | 1989-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02101632U true JPH02101632U (en) | 1990-08-13 |
Family
ID=31217397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1006889U Pending JPH02101632U (en) | 1989-01-31 | 1989-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02101632U (en) |
-
1989
- 1989-01-31 JP JP1006889U patent/JPH02101632U/ja active Pending